VISVESVARAYA TECHNOLOGICAL UNIVERSITY

BELAGAVI - 590018, KARNATAKA

A Project Proposal Report on

Low-Power RISC-V Microcontroller
By
Alex Rojan - 4SO21EC008

Ashok D’Sa - 4SO21EC012

Nihal NS - 4SO21EC062
Omkar Bhat - 4SO21EC065

Under the Guidance of

Mr Vijay Ganesh P.C
Assistant Professor

Department of Electronics and Communication Engineering

(UG Programme accredited by National Board of Accreditation, New Delhi)

ST JOSEPH ENGINEERING COLLEGE

An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi,
Accredited by NAAC with A+ Grade
Vamanjoor, Mangaluru - 575028, India

November 2024
Project Team

Sl. No USN Name Signature with Date

1 4SO21EC008 Alex Rojan

2 4SO21EC012 Ashok D’Sa

3 4SO21EC062 Nihal N S

4 4SO21EC065 Omkar Bhat

I hereby certify that students have discussed with me and finalized the report.

Mr Vijay Ganesh P.C

Assistant Professor
 TABLE OF CONTENTS
LIST OF FIGURES ......................................................................................................................... I
LIST OF TABLES .......................................................................................................................... II
LIST OF ABBREVIATIONS ....................................................................................................... III
CHAPTER 1 ................................................................................................................................... 1
INTRODUCTION ....................................................................................................................... 1
CHAPTER 2 ................................................................................................................................... 2
LITERATURE SURVEY ........................................................................................................... 2
2.1 A survey on the existing systems ...................................................................................... 2
2.2 Problem definition ............................................................................................................. 5
2.3 Objectives .......................................................................................................................... 6
CHAPTER 3 ................................................................................................................................... 7
METHODOLOGY ...................................................................................................................... 7
3.1 Processor Design ............................................................................................................... 7
3.1.1 Instruction Fetch ......................................................................................................... 7
3.1.2 Decode ........................................................................................................................ 8
3.1.2.1 Register-Register type (R type) ............................................................................ 8
3.1.2.2 Immediate type (I Type) ....................................................................................... 9
3.1.3 Read 1 and Read 2 ...................................................................................................... 9
3.1.4 Execute ...................................................................................................................... 10
3.1.5 Store .......................................................................................................................... 10
3.1.5 PC Update ................................................................................................................. 10
3.2: 4x4 keypad matrix .......................................................................................................... 11
3.3 Memory ........................................................................................................................... 12
3.4: LCD Interfacing.............................................................................................................. 14
CHAPTER 4 ................................................................................................................................. 16
RESULTS & DISCUSSION ..................................................................................................... 16
4.1 R type and I type implementation.................................................................................... 16
4.2 Power consumption of 4x4 keypad matrix ...................................................................... 17
REFERENCES .......................................................................................................................... 18
 LIST OF FIGURES
Figure 3.1.1: FSM for processor ................................................................................................................... 7
Figure 3.2.1: Keypad Matrix ....................................................................................................................... 11
Figure 3.2.2: Keypad Logic Flowchart ....................................................................................................... 11
Figure 3.3.1: Memory interface with microcontroller ................................................................................ 12
Figure 3.3.2: Memory block diagram ......................................................................................................... 13
Figure 3.4.1: Block diagram for LCD ......................................................................................................... 14
Figure 4.1.1: R and I type simulation.......................................................................................................... 16
Figure 4.2.1: Keypad power consumption .................................................................................................. 17

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 LIST OF TABLES
Table 2.1 An overview of the literature survey to identify the gaps………………………………………..2
Table 3.1 R type instructions……………………………………………………………………………….8
Table 3.2 I type instructions………………………………………………………………………………...9

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 LIST OF ABBREVIATIONS

Keyword Abbreviations

RISC Reduced Instruction Set Computer

EBSCO Elton Bryson Stephens Company

FSM Finite State Machine

ALU Arithmetic logic unit

RAM Random Access Memory

LCD Liquid Crystal Display

FPGA Field Programmable Gate Array

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CHAPTER 1

INTRODUCTION
In the evolving landscape of embedded systems, power efficiency and flexibility are paramount.
The RISC-V architecture, known for its simplicity and open-source nature, offers a compelling
platform for developing low-power microcontrollers. Unlike traditional architectures, RISC-V
provides a highly customizable and extensible instruction set, allowing designers to tailor the
microcontroller for specific applications while minimising power consumption. Low-power
microcontrollers are essential in numerous applications, from wearable devices and IoT sensors to
energy-harvesting systems. These applications require components that can operate with minimal
energy, extending battery life and enabling long-term deployment in remote locations. The RISC-
V architecture's modularity and streamlined design make it particularly well- suited for these
energy-sensitive environments.

In this project, we will delve into the design and implementation of a low-power microcontroller
based on the RISC-V architecture. By employing a combination of reduced instruction set
computing principles and state-of-the-art power management strategies, we aim to develop a
microcontroller that achieves significant energy efficiency without compromising performance.
Moreover, this project presents a unique learning opportunity.

Engaging with the RISC-V architecture, we will deepen our understanding of modern
microcontroller design and energy-efficient computing. We will explore the intricacies of
hardware description languages, power management techniques, and the nuances of designing for
low-power applications. This knowledge will enrich our skills and broaden our perspectives as
engineers, equipping us with the expertise to tackle future challenges in embedded systems and
beyond.

The project aims to demonstrate the potential of RISC-V in creating next-generation low-power
microcontrollers and to address the critical need for sustainable and efficient embedded systems
in our increasingly connected world.

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CHAPTER 2

LITERATURE SURVEY
This survey intends to investigate various aspects of microcontrollers, addressing specific research
questions about their design principles, mechanisms, applications, construction, architecture
choices, and instruction sets. The survey leveraged databases such as Google Scholar, Web of
Science, and EBSCO, alongside registers like Free Patents Online and Lens.org, and websites
including ResearchGate, NDL-IIT Kharagpur, and Grafiati. The search was conducted over the
days, focusing on papers published after 2016 to ensure relevance to current developments in the
field. The literature survey adopted a thematic approach, seeking to identify trends, innovations,
and practical applications of microcontrollers in modern electronic systems. Keywords and
synonyms such as "Microcontroller", "RISC", "FPGA", "Low power", and "Architecture" were
utilized to refine the search scope and capture pertinent literature.

2.1 A survey on the existing systems

Table 2.1 An overview of the literature survey to identify the gaps

Sl. Title of the Paper, Name Methodology Gap identified

No. of the Journal, Year

1 Implementation of RISC- Creation of a Processor power

Based Architecture for Low microprocessor in consumption is 132mw.
power applications, IOSR VHDL, Power
Journal of Electrical and consumption of 132mw.
Electronics Engineering,
2013

2 The survey of concepts of Analysis of RISC and Performance dependence

architecture in RISC and CISC architectures, on ISA
CISC computers, impacts on performance
International Journal of and power consumption.
Advance Research, Ideas By detailing the impacts
and Innovations in of ISAs on performance
Technology, 2018 and power consumption,
the research provides
valuable insights into
optimising

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microcontroller designs
for specific applications.

3 Design of Low Power 32- Uniform instruction 16-bit RISC processor

Bit RISC Processor using format, Wallace tree with Von Neumann
Verilog HDL, International multiplier to reduce architecture
Research Journal of propagation delay.
Engineering and
Technology (IRJET), 2019

4 Implementation of Verilog 8-bit calculator design, Limited Functionality

HDL in calculator design supports basic
with FPGA Simulation, mathematical
IEEE, 2020 operations, only
supports integers.

5 AXI Lite Redundant On- Redundant AXI Lite bus Fault Injection Analysis,
Chip Bus Interconnect for interconnect using fault- Reliability Quantification
High Reliability Systems, tolerant and majority
IEEE Transactions on voting mechanisms to
Reliability, 2024 improve SoC reliability

6 On Error Injection for NoC Implementing Robust Only focus on bit-flip

Platforms: A UVM-based Scoreboards in UVM for errors and lack of
Generic Verification Effective Error Injection Quantitative Analysis
Environment, IEEE
Transactions on Computer-
Aided Design of Integrated
Circuits and Systems, 2020

7 Benchmarking-Based Comparison of the Real- Limited Scope and lack of

Investigation on Energy Time Power readings of Detailed Analysis on
Efficiency of Low-Power microcontrollers to its energy consumption
Microcontrollers, IEEE datasheet trends
Transactions on
Instrumentation and
Measurement, 2020

8 Edge Computing: A Survey Survey on design for Does not suggest Security
On the Hardware low power hardware. Hardware for Edge
Requirements in the Devices Hardware
Internet of Things World, Interfaces were not
Future Internet, 2019 standardized

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9 Multilevel Logic Reduction of logic Limited to Small-Scale

Minimization Using K-map levels to improve the Circuits. Lack of
XOR Patterns, IEEE power consumption. Automation
Transactions on Education,
1995

10 A Multi-One Instruction Set Efficient Use of

Computer for Minimalistic Memory Hierarchy was
Microcontroller Architectures, not discussed.
Applications, IEEE Access, Balancing Power, Area,
2021 and Performance,
Importance of
Peripheral Integration in
Microcontroller Design

11 Siwa: a RISC-V RV32I Application of RISC No details on the long-

based Micro-Controller for architecture term reliability
Implantable Medical microcontrollers in
Applications, 2020 precision-based
applications like
medical devices.

12 RISC-V Instruction Set Survey on RISC V Does not discuss the

Architecture Extensions: A extensions and analysis fragmentation risks
Survey, IEEE Access, 2023 on areas of application
where RISC still needs
to develop.

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2.2 Problem definition

Statement:

The demand for faster, more energy-efficient computing has driven the development of diverse
computing architectures and design innovations, shaping the landscape of modern computing. The
open-source RISC-V architecture, with its flexibility and applicability across various domains,
presents a promising platform for such advancements.

Significance:

In an era where the Internet of Things (IoT) and machine learning dominate, the need for
processors that are both low-power and high-performance is critical. The RISC-V architecture is
well-suited for this purpose, not only because of its open-source nature but also due to its
adaptability to custom implementations and potential for optimization. This project aims to
contribute to the industry by exploring design avenues within the RISC-V framework, with the
potential to uncover gaps in existing research or industrial practices that may present opportunities
for further exploration.

Scope:

● Implementation on FPGA: The microcontroller will be implemented on an FPGA to

evaluate and prototype the functionality and design approach.
● Optimization for Low Power: Power-efficient design changes will be explored over the
course of the project, based on iterative evaluations and potential design modifications.
● Benchmarking against Industry Standards: Performance will be benchmarked against
current industry standards to ensure competitiveness and applicability.

Limitations:

● Resource Constraints: FPGA resources may limit certain architectural optimizations or

design features that could be applied in ASIC implementations.
● Power Analysis Accuracy: Power consumption metrics on an FPGA can differ from those
on a final silicon implementation, leading to possible discrepancies in power efficiency
estimates.

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● Scalability: While the design may perform optimally in isolated conditions, scalability for
larger applications or more intensive computational tasks may be limited without further
development.

2.3 Objectives
The primary objectives of the project are to

1. Achieve low power consumption through simulation and FPGA implementation

2. Design a 32-bit input/output compatible microcontroller.

3. Support multiple instruction formats.

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CHAPTER 3

METHODOLOGY
3.1 Processor Design

The finite state machine design

for this processor consists of
seven distinct states: Instruction
Fetch, Decode, Read 1, Read 2,
Execute, Store and Program
counter update. Each of these
states performs a unique function
within the instruction cycle,
progressing in sequence based on
clock signals. The FSM
Figure 3.1.1: FSM for processor transitions between states
depending on the clock’s high
signal, enabling synchronized progression through the stages of instruction execution.

3.1.1 Instruction Fetch

When the processor starts it resets the values of all the component outputs where the processor
clears any existing data and prepares for new operations. This serves as a stable starting point, and
it transitions to the Instruction Fetch state when the clock goes high (clk=1). Upon receiving the
high clock signal, the FSM starts with the Instruction Fetch state, where the current program
counter (PC) value is read. In this state, the processor uses this PC value to fetch the instruction
stored at the corresponding address in RAM. This fetched instruction is then stored, setting the
processor up for the next stage in the sequence. With a low clock signal (clk=0), the FSM remains
in the same state, providing stability if required.

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3.1.2 Decode
In the Decode state, the fetched instruction is parsed into its smaller, constituent parts, such as
operand addresses, destination register addresses, and opcode. This parsing process is crucial, as
it allows the processor to interpret the specific operation required by the instruction. Once decoded,
the FSM awaits a high clock signal to transition to the Read 1 state else it remains in the same state

3.1.2.1 Register-Register type (R type)

Table 3.1 R type instructions

funct7 Operand Operand funct3 Destination Opcode Operation

2 address 1 address Register

0000000 rs2 rs1 000 rd 0110011 Add

0100000 rs2 rs1 000 rd 0110011 Subtract

0000000 rs2 rs1 001 rd 0110011 Shift Left Logical

0000000 rs2 rs1 010 rd 0110011 Set Less Than

0000000 rs2 rs1 011 rd 0110011 Set Less Than Unsigned

0000000 rs2 rs1 100 rd 0110011 XOR

0000000 rs2 rs1 101 rd 0110011 Shift RIght Logical

0100000 rs2 rs1 101 rd 0110011 Shift Right Arithmetic

0000000 rs2 rs1 110 rd 0110011 OR

0000000 rs2 rs1 111 rd 0110011 AND

Table 3.1 shows the decoding that has to occur in the decoder for the register-to-register type. The
bits [31:25] gives the funct7, [24:20] gives the address of the 2nd operand which is referred to as
rs2, [19:15] gives the address of the 1st operand which is referred to as rs1, [14:12] gives the

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address of the funct3, [11:7] gives the address of the destination address which is referred to as rd
and [6:0] gives the opcode. The main speciality of R type is that the operands are stored in the
register set and have to be fetched from the register bank.

3.1.2.2 Immediate type (I Type)

Table 3.2 I type instructions

Immediate Operand 1 funct 3 Destination Opcode Operation

value address Register

imm[11:0] rs1 000 rd 0010011 ADDI

imm[11:0] rs1 010 rd 0010011 SLTI

imm[11:0] rs1 011 rd 0010011 SLTIU

imm[11:0] rs1 100 rd 0010011 XORI

imm[11:0] rs1 110 rd 0010011 ORI

imm[11:0] rs1 111 rd 0010011 ANDI

Table 3.2 shows the decoding that has to occur in the decoder for the immediate type. The bits
[31:0] gives the immediate value, [19:15] gives the address of the 1st operand, which is referred
to as rs1, [14:12] gives the address of the funct3, [11:7] gives the address of the destination address
which is referred to as rd and [6:0] gives the opcode. The main speciality of I type is that the first
operand is stored in the register bank while the other operand comes to the processor directly from
the instruction.

3.1.3 Read 1 and Read 2

Read 1 state precedes the Read 2 state and are similar in operation but are separated as two states
to prevent hazards when reading from the RAM. These states are used to fetch the operands either
from the register or directly from the instruction in the case of Immediate type. The processor uses
the operand address found in the instruction to read the operands from the register bank.

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3.1.4 Execute
The execute state is made up of two modules, one is ALU control and the other being the
Arithmetic and Logic Unit itself. In ALU Control, depending upon the remaining parts of the
instruction like funct7 and funct3 and opcode the ALU select codes are mapped and sent to the
ALU. This mapping aligns with the decoded instruction requirements and sets up the ALU to
perform the necessary calculations. ALU is the stage where the actual computation happens. Using
the inputs from the ALU Control, the ALU performs the arithmetic or logical operation as specified
by the opcode. Once the computation is complete in the next high clock signal the FSM moves to
the store state.

3.1.5 Store
The result computed by the ALU is then prepared for storage, ensuring that the operation is
completed before moving to the next stage. On receiving a high clock signal, the processor stores
the computed result in the register bank in the register address specified by the instruction. This
ensures that all required data and results are saved correctly, maintaining the processor’s data
integrity. Once the write operation is complete, in the next high clock the FSM moves to the PC
Update state else it stays in the same state.

3.1.5 PC Update
Once one whole instruction has been executed the Program Counter value is incremented to
process the next instruction. Wherein, FSM either returns to the Instruction Fetch state or remains
idle, depending on the program’s requirements.

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3.2: 4x4 keypad matrix

A 4x4 keypad matrix is a common input

device used in various electronic projects
and embedded systems for user interaction.
As shown in Figure 3.2.1 it consists of 16
keys arranged in a 4-row by a 4-column
grid. Each key connects a specific row to a
column when pressed, allowing the
detection of the key press through scanning

Figure 3.2.1: Keypad Matrix

techniques.

As shown in Figure 3.2.2, we first initialise all the row pins to logic "0" and column pins to logic
"1" (ROW = 0000, COLUMN = 1111). When a key is pressed, the corresponding column pin is
set to "0". Sequentially send logic "1" to each row and detect changes in column logic to identify
the pressed key. Send the key value in the form of bits or ASCII through the row pins.

Figure 3.2.2: Keypad Logic Flowchart

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3.3 Memory
In the microcontroller design, memory plays a crucial role in managing the flow of data between
various processing units, as it provides the temporary storage needed for data manipulation and
retrieval during computations. For this low-power RISC-V microcontroller, memory is essential
for enabling efficient execution of instructions by holding both operational data and intermediate
results. By incorporating memory directly into the microcontroller's architecture, we improve data
accessibility and system responsiveness, which are critical for applications that require real-time
processing.

Figure 3.3.14: Memory interface with microcontroller

The Figure 3.3.1 shows how the memory interacts with the other units in the microcontroller.
Memory in this project is implemented using a RAM module that operates as a data buffer,
essential for storing inputs, instructions, and intermediate calculation results. This memory system
supports efficient handling of data between the processor and other peripheral modules, allowing
the microcontroller to function smoothly without external memory dependencies. In particular, the
RAM module is designed with 2048 memory locations, each capable of holding 8 bits of data,
making it compact yet sufficient for the memory needs of lightweight processing tasks typically
seen in low-power applications.

The memory will be integral to microcontroller's operation by managing the following critical
tasks:

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1. Instruction Fetching and Execution: During the instruction cycle, memory is used to store
and retrieve instructions that the processor executes sequentially. For instance, in each
cycle, the processor fetches the necessary instruction from memory, decodes it, and then
either stores the result back into memory or prepares it for the next operation. This
continuous access to memory ensures that the microcontroller can handle a sequence of
instructions without delays.
2. Temporary Data Storage: For each operation, intermediate data needs to be temporarily
stored and accessed rapidly. Our RAM module provides this capability, storing values that
will be used in future calculations or passed to peripheral devices. The efficient design of
the memory allows for low-latency access to this data, crucial for maintaining the speed
and reliability of the microcontroller in real-time applications.
3. State Management and Synchronization: The memory’s control signals, such as
busy_mem, full_mem, and empty_mem, allow for real-time state management, ensuring
that read and write operations are coordinated without data overlap or loss. These flags
inform the processor of memory availability, avoiding overwriting data before it has been
read or attempting to read uninitialized data. This capability is particularly valuable in low-
power designs, where idle states help conserve energy while ensuring readiness for active
tasks.

Figure 3.3.25: Memory block diagram

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3.4: LCD Interfacing

The interfacing of an LCD module
involves several key steps as
shown in Figure 3.4.1. Initially, the
pins connected to the LCD (RS,
RW, E, D0-D7) are defined. The
LCD is then configured to operate
in 8-bit mode, with the appropriate
number of display lines and
character font set using the enable
pin. Display and cursor settings are
turned on, the display is cleared,

Figure 3.4.16: Block diagram for LCD and the LCD is set to entry mode to
increment the cursor without
shifting the display. A function is created to send commands and data (characters) through the RS
pin, utilizing the D0-D7 pins. Additionally, a function is designed to send strings to the LCD,
iterating through each character in the string and displaying it by switching the RW pin. To control
the cursor position, a function calculates the desired location based on the row and column of the
display matrix and sends the corresponding command to set the cursor position accurately.

The working of the LCD module in synergy with the code:

Step 1 - Initialization: Define the pins connected to the LCD (RS, RW, E, DO, D1, D2, D3, D4,
D5, D6, D7). Set the LCD to 8-bit mode and the number of display lines and character font using
the enable pin, then turn on the display and cursor settings. Clear the display. Set the LCD to entry
mode (increment cursor, no display shift).

Step 2 - Function to send Data: Setting up function to send commands through the RS pin, send
data (characters) also a function to send a string to the LCD (data is sent through the D0-D7 pins).

Step 3 - Display on the LCD: Create a function to send data to the LCD. Use the data-sending
function to display each character (This is done by switching the RW pin).

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Step 4 - Set Cursor Position: Create a function to set the cursor position on the LCD. Calculate
the location of the cursor based on the row and column of the display matrix. Send the appropriate
command to set the cursor position.

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CHAPTER 4

RESULTS & DISCUSSION

4.1 R type and I type implementation

Figure 4.1.17: R and I type simulation

From the Figure 4.1.1 we see that fetch, decode, execute cycle was implemented for both R and I
type and was found to obey all the currently designed specifications. However, it was found that
the register bank locations 1 and 2 are being skipped. This must be reviewed and improved.

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4.2 Power consumption of 4x4 keypad matrix

Figure 4.2.8: Keypad power consumption

As illustrated in Figure 4.2.1 the total on-chip power consumption for the keypad matrix is 0.104
W. Most of this power (94%) is static, with only 6% attributed to dynamic power. Within the
dynamic power, the majority (87%) is consumed by I/O functions, which includes input from the
keypad. This low dynamic power consumption aligns with the energy-efficient design of the
keypad, which uses a scanning method to detect key presses while minimizing active power usage.

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