P1203EEA

P-Channel Logic Level Enhancement Mode MOSFET

PRODUCT SUMMARY
V(BR)DSS RDS(ON) ID

-30V 12mΩ @VGS = -10V -40A

PDFN 3x3P

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
Drain-Source Voltage VDS -30
V
Gate-Source Voltage VGS ±25
TC = 25 °C -40
TC = 100 °C -25
Continuous Drain Current2 ID
TA = 25 °C -11
A
TA = 70 °C -9
Pulsed Drain Current1 IDM -95
Avalanche Current IAS 45
Avalanche Energy L = 0.1mH EAS 101 mJ
TC = 25 °C 31
TC = 100 °C 12
Power Dissipation PD W
TA = 25 °C 2.2
TA = 70 °C 1.4
Operating Junction & Storage Temperature Range TJ, TSTG -55 to 150 °C

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P-Channel Logic Level Enhancement Mode MOSFET

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS
3
Junction-to-Ambient Steady-State RqJA 55
°C / W
Junction-to-Ambient Steady-State RqJC 4
1
Pulse width limited by maximum junction temperature.
2
Package limitation current is -30A.
3
The value of RqJA is measured with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air
environment with TA = 25°C. The value in any given application depends on the user's specific board design.

ELECTRICAL CHARACTERISTICS (TJ = 25 °C, Unless Otherwise Noted)

LIMITS
PARAMETER SYMBOL TEST CONDITIONS UNITS
MIN TYP MAX
STATIC
Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250mA -30
V
Gate Threshold Voltage VGS(th) VDS = VGS, ID = -250mA -1 -1.5 -2.5
Gate-Body Leakage IGSS VDS = 0V, VGS = ±25V ±100 nA
VDS = -24V, VGS = 0V -1
Zero Gate Voltage Drain Current IDSS mA
VDS = -20V, VGS = 0V , TJ = 125 °C -10
On-State Drain Current1 ID(ON) VDS = -5V, VGS = -10V -95 A
Drain-Source On-State VGS = -4.5V, ID = -9A 13 19
RDS(ON) mΩ
Resistance1 VGS = -10V, ID = -12A 8.8 12
Forward Transconductance1 gfs VDS = -5V, ID = -12A 31 S
DYNAMIC
Input Capacitance Ciss 2760
Output Capacitance Coss VGS = 0V, VDS = -15V, f = 1MHz 437 pF
Reverse Transfer Capacitance Crss 395
Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz 2.5 Ω
Qg(VGS=-10V) 64
Total Gate Charge2
Qg(VGS=-4.5V) 33
2
VDS = -15V, ID = -12A nC
Gate-Source Charge Qgs 10
Gate-Drain Charge2 Qgd 16
2 td(on)
Turn-On Delay Time 21
2 tr
Rise Time VDS = -15V, 25
nS
Turn-Off Delay Time 2 td(off) ID @ -12A, VGS = -10V, RGS = 6Ω 100
Fall Time2 tf 73

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P-Channel Logic Level Enhancement Mode MOSFET

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 °C)

3 IS
Continuous Current -40 A
1 VSD IF = -12A, VGS = 0V
Forward Voltage -1.2 V
Reverse Recovery Time trr 21 nS
IF = -12A, dlF/dt = 100A / mS
Reverse Recovery Charge Qrr 7 nC
1
Pulse test : Pulse Width  300 msec, Duty Cycle  2％.
2
Independent of operating temperature.
3
Package limitation current is -30A.

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P-Channel Logic Level Enhancement Mode MOSFET

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P-Channel Logic Level Enhancement Mode MOSFET

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P-Channel Logic Level Enhancement Mode MOSFET

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P-Channel Logic Level Enhancement Mode MOSFET

A. Marking Information(此产品代码为：B2）

B. Tape&Reel Information:5000pcs/Reel

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P-Channel Logic Level Enhancement Mode MOSFET

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P-Channel Logic Level Enhancement Mode MOSFET

D.Label rule
标签内容(Label content)

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