2014 Fourth International Conference on Advances in Computing and Communications

Digital Feedback Control of a Full-Bridge DC-DC Converter

With Input Voltage Based Gain Scheduling

Nithin George∗ , Vadamalai Natarajan Panchalai† and Elizabeth Sebastian∗

∗ Department of Electrical and Electronics Engineering,
Mar Athanasius College of Engineering, Kothamangalam, Kerala, India
Email:[email protected]
† Naval Physical and Oceanographic Laboratory, Kochi, Kerala, India

Abstract—Digital feedback control of a full-bridge DC-DC input voltages of a full-bridge DC-DC converter was pre-
converter, using a gain scheduled PI controller, is presented in calculated and stored as a look up table. Such a feature
this paper. Input voltage to the converter varies over a large can be interpreted as a form of gain scheduling. In [4],
range; as a result, controller gain designed for one particular
input voltage may not give the optimum performance. Conse- the load resistance of an interleaved buck converter was
quently, gain of the digital PI controller is made a function measured and the gain of the controller was made its
of the varying input voltage, and such a strategy leads to function. Likewise in [7], the controller gain of a full-bridge
the system bandwidth and phase margin having a constant DC-DC converter was made a function of the load current
optimum value. This in turn gives a better transient response, and in [8], it was made a function of the output voltage. For
both with changes in load as well as changes in input voltage.
A low cost 16 bit PIC microcontroller, which has an inbuilt the former, it led to preservation of bandwidth; and in the
ADC and a PWM generation module, is used for implementing latter, it resulted in an almost constant value for the phase
the proposed digital controller. The experimental results from margin.
a 50 W prototype have been provided to show the effectiveness In this paper, a digital PI controller is used for feedback
of this control strategy. control of a full-bridge DC-DC converter, and its gain is
Keywords-gain scheduling; digital controller; full-bridge DC- made a function of the converter input voltage. Input voltage
DC converter; to the converter varies widely and this gain scheduling helps
in preserving the bandwidth and phase margin. The digital
I. I NTRODUCTION controller is implemented on a 16 bit dsPIC30F2010 micro-
controller, which has an inbuilt PWM generation module
Digital feedback control of power converters is gaining and a multi-channel ADC. Design aspects of the digital
popularity of late, mainly due to ever reducing cost of digital controller are discussed, so is the frequency domain impli-
ICs and their improved capabilities. Digital implementation cation of gain scheduling. Further, experimental results from
of feedback control brings with it several features: noise im- a 50 W prototype converter have been provided, to illustrate
munity, easy reconfiguration, multitasking, communication the performance of the proposed control system.
capabilities, etc. Besides, there are several control features
II. C ONVERTER CIRCUIT AND MODEL
that can easily be implemented in digital domain, but whose
analog implementation is too complex [1]. Examples of Phase-shift-modulated full-bridge DC-DC converter is the
such features include sensorless current mode control [2], plant considered for feedback control in this paper. This
controller autotuning [3], gain scheduling [4], etc. symmetrically operating converter has the ability to achieve
Gain scheduling is a type of preprogrammed adaptive soft switching using the transformer leakage inductance.
control, in which the controller parameters are changed Circuit configuration of the converter is shown in Fig. 1;
according to certain system variables [5]. This is done waveforms and converter design equations are detailed
to preserve certain system characteristics like bandwidth in [9].
or phase margin, when the parameters of the plant vary For designing a feedback controller for the converter, its
over a large range. Earlier, in order to implement gain control to output transfer function is required. In [10] this
scheduling, analog techniques were used and this involved has been given as:
use of multipliers, making the system prohibitively costly. 𝑛𝑉𝑖𝑛
𝐺𝑣𝑑 (𝑠) = ( ) ( ) (1)
But with the arrival of low cost microcontrollers this task 𝐿 𝑅𝑑
2
𝑠 (𝐿𝐶) + 𝑠 + 𝑅𝑑 𝐶 + +1
has been made simple and cost effective.
𝑅 𝑅
Several works have been reported, wherein gain schedul-
ing has been used in conjunction with linear control. An where 𝑅𝑑 = 4𝐿𝑘 𝑓𝑠 𝑛2 ; 𝑉𝑖𝑛 is the input DC voltage; 𝑅,
example is [6], where the feedback vector for different the load resistance; 𝑓𝑠 , the switching frequency; 𝐿𝑘 , the

978-1-4799-4363-0/14 $31.00 © 2014 IEEE 347

DOI 10.1109/ICACC.2014.88
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 Leg 1 Leg 2 L Iout Ref Controller Delay DPWM Converter Vout
+
Gc(z) z -1 1/M Gvd(z)
_
Q1 Q3 Lk
C Kfb
R Vout
Vin
ADC & feedback
1:n sensor
Q4 Q2
Figure 2. Block diagram model of the feedback controlled system.

Gating Driver ds PIC

Signals Ciruits 30F2010
The maximum values of 𝑉𝑖𝑛 and 𝑅 have been taken for
the design calculations. This would, in most cases, ensure
stability of the system for a lower value of 𝑉𝑖𝑛 or 𝑅.
Figure 1. Circuit configuration of a full-bridge DC-DC converter. A
microcontroller for signal generation and feedback control is also shown.
For the feedback path, a gain is contributed by the
presence of the ADC and feedback sensor. This gain may
Table I be defined as:
C ONVERTER PARAMETERS 2𝑁𝑎𝑑𝑐 − 1
𝐾𝑓 𝑏 = ⋅𝐻 (5)
𝑉𝑓 𝑠
Parameter Value
Input voltage 𝑉𝑖𝑛 25 V - 60 V Here 𝑁𝑎𝑑𝑐 is the number of bits in the output of the ADC,
Transformer turns ratio 1 : 𝑛 1:1 𝑉𝑓 𝑠 is the full scale voltage of the ADC and 𝐻 is the
Switching frequency 𝑓𝑠 30 kHz feedback sensor gain.
Transformer leakage inductance 𝐿𝑘 6.5 𝜇𝐻 Discrete PWM (DPWM) generator within the microcon-
Filter capacitance C 470 𝜇𝐹 troller is modeled as a gain 1/𝑀 , where 𝑀 corresponds
Filter inductance L 79 𝜇𝐻 to the number for unity duty ratio [12]. The unit delay
Load resistance R 2 Ω − 10 Ω 𝑧 −1 models the computational delay in the microcontroller;
Output voltage 𝑉𝑜𝑢𝑡 10 V 𝐺𝑐 (𝑧) denotes the digital controller to be designed. Sam-
pling frequency of 𝑉𝑜𝑢𝑡 is kept same as the switching
frequency ie., at 30 kHz. When gain scheduling is employed,
transformer leakage inductance referred to primary; 𝐶, the 𝑉𝑖𝑛 would also be sampled at the same rate.
filter capacitance; 𝐿, the filter inductance; and 1 : 𝑛, the The digital controller is chosen to be in the form of a
transformer turns ratio. The steady state DC gain of the Proportional-Integral (PI) controller, and its discrete-time
above transfer function is: transfer function is given by:
𝑛𝑉𝑖𝑛 ( )
𝐺𝑣𝑑𝑠𝑠 = (2) 𝐾𝑖
𝑅𝑑 𝐺𝑐 (𝑧) = 𝐾𝑝 1 + (6)
+1 1 − 𝑧 −1
𝑅
Difference equations corresponding to (6) are given in [12].
From the above relationship, it can be inferred that the gain For designing the digital controller, frequency response
has significant dependence on the load resistance. Thus, method has been be employed here [11]. Based on the
providing feedback control for such a converter is quite requirement for a phase margin of 56∘ , at a cross over fre-
justified. Table. I shows the parameter values of the full- quency of 343 Hz, 𝐾𝑝 and 𝐾𝑖 values are chosen as equal to
bridge DC-DC converter considered in this paper. 1/3. Bode diagram of the loop transfer function 𝐺𝑙𝑜𝑜𝑝 (𝑧) =
III. D IGITAL CONTROLLER DESIGN 𝐾𝑓 𝑏 .𝑧 −1 .𝐺𝑣𝑑 (𝑧)/𝑀 , 𝐺𝑐 (𝑧) and 𝐺𝑙𝑜𝑜𝑝 (𝑧).𝐺𝑐 (𝑧) is shown
in Fig. 3.
To design a digital controller, a block diagram model
of the total system, as shown in Fig. 2, has to be first IV. GAIN SCHEDULING
formed. In the block diagram, the converter is modeled
In linear feedback control, usually the controller gains
by the discretized form of its control to output transfer
are not changed online and they remain fixed to the design
function [11]. It is given by:
[ ] value. For such a situation, the effect of variation in 𝑉𝑖𝑛
𝐺𝑣𝑑 (𝑠) on the system phase margin and gain crossover frequency
𝐺𝑣𝑑 (𝑧) = (1 − 𝑧 −1 )𝒵 (3)
𝑠 is illustrated in Figs. 4 and 5. At the higher extremum of
𝑉𝑖𝑛 , the designed value of 56∘ and 343 Hz is obtained. But
For 𝑉𝑖𝑛 = 60 𝑉 and 𝑅 = 10 Ω, 𝐺𝑣𝑑 (𝑧) is given by:
for the lower extremum, the gain crossover frequency is
0.8029𝑧 + 0.7178 about 153 Hz, while the phase margin is 75∘ . A sluggish
𝐺𝑣𝑑 (𝑧) = (4)
𝑧 2 − 1.687𝑧 + 0.7145 transient response is the main time domain implication of

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 3
Bode Diagram Gloop(z) 10
40 Gain scheduled
Gc(z) Fixed gain

Gain crossover frequency (Hz)

20 Gloop(z).Gc(z)
Magnitude (dB)

0
−20
−40
−60
−80
180

0
Phase (deg)

−180 2
10
25 30 35 40 45 50 55 60
−360 Input voltage Vin (V)

−540 Figure 5. Gain crossover frequency of 𝐺𝑙𝑜𝑜𝑝 .𝐺𝑐 (𝑧) as 𝑉𝑖𝑛 is varied,
1 2 3 4
10 10 10 10 with gain scheduling and with fixed gain control.
Frequency (Hz)

Figure 3. Bode diagram of the 𝐺𝑙𝑜𝑜𝑝 (𝑧), 𝐺𝑐 (𝑧) and 𝐺𝑙𝑜𝑜𝑝 .𝐺𝑐 (𝑧).

90
Gain scheduled
80 Fixed gain
70
Phase margin (degrees)

60

50

40

30

20

10

0
25 30 35 40 45 50 55 60 Figure 6. Gating voltages given to high side switches Q1 (CH3) and
Input voltage Vin (V) Q3 (CH4). MATH = CH3-CH4.

Figure 4. Phase margin of 𝐺𝑙𝑜𝑜𝑝 .𝐺𝑐 (𝑧) as 𝑉𝑖𝑛 is varied, with gain
scheduling and with fixed gain control. 60 V to 25 V.
The change gain scheduling has brought about can be
inferred from Figs. 4 and 5 itself. The phase margin and
such an excessive phase margin and lowered gain crossover gain crossover frequency are found to remain a constant at
frequency. 56∘ and 343 Hz respectively, in spite of variations in 𝑉𝑖𝑛 .
In the proposed gain scheduling scheme, the proportional
gain 𝐾𝑝 of the digital PI controller is made a function of V. EXPERIMENTAL RESULTS
𝑉𝑖𝑛 . Mathematically this can be defined as:
In order to verify the effectiveness of the proposed control
𝑉𝑖𝑛−𝑚𝑎𝑥 system, a 50 W prototype with specifications as mentioned in
𝐾𝑝−𝑑𝑠𝑔𝑛 𝐾𝑝 = (7)
𝑉𝑖𝑛 Table. I was fabricated. In this prototype, the gating signals
where 𝐾𝑝 is the scheduled value of proportional gain; given to the two upper switches Q1 and Q3 (CH3 and CH4
𝑉𝑖𝑛−𝑚𝑎𝑥 , the maximum value for 𝑉𝑖𝑛 ; and 𝐾𝑝−𝑑𝑠𝑔𝑛 is the respectively), is shown in Fig. 6. The input voltage is not
proportional gain as per the original design. Essentially, applied at time of saving the waveforms. MATH channel (M)
this would nullify any reduction in gain brought forth by shows the difference between the signals (CH3-CH4) and its
decrease of 𝑉𝑖𝑛 from its highest value. In the instant case, shape will be similar to the transformer primary voltage.
𝐾𝑝 would increase from 1/3 to 0.8, as 𝑉𝑖𝑛 decreases from The gate to source voltage (CH4) and drain to source

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 14 12
Fixed gain
12 Gain scheduled 10
Output voltage
10 8

Output voltage (V)

Load current (A)

8 6

6 4

4 2
Load current

2 0

0 −2
−2 0 2 4 6
Time (ms)

Figure 7. Gate to source voltage (CH4) and drain to source voltage (CH3) Figure 9. Output voltage transients, when 𝐼𝑜𝑢𝑡 changes as a step from
of Q4, indicating ZVS. 5 A to 1 A; 𝑉𝑖𝑛 = 25 𝑉 .

20
14 12
Fixed gain
Fixed gain
Gain scheduled
12 Gain scheduled 10 15
Output voltage
Output voltage (V)

10 8
Output voltage (V)

Load current (A)

10
8 6
Load current

6 4 5

4 2
0
2 0

−5
0 −2 −2 0 2 4 6 8
−2 −1 0 1 2 3 4 5
Time (ms)
Time (ms)
Figure 10. Output voltage transients for a step application of 𝑉𝑖𝑛 = 25 𝑉 ,
Figure 8. Output voltage transients, when 𝐼𝑜𝑢𝑡 changes as a step from with gain scheduling and with fixed gain control.
1 A to 5 A; 𝑉𝑖𝑛 = 25 𝑉 .

5 A to 1 A, at 𝑉𝑖𝑛 = 25 𝑉 , is shown in Fig. 9. With gain

voltage (CH3) waveform, of switch Q4, for a load current scheduling, a slight undershoot is obtained but it remains
𝐼𝑜𝑢𝑡 = 1.25 A, is given in Fig. 7. The waveforms clearly well within the tolerable limits. In this context, the settling
indicate Zero Voltage Switching (ZVS) taking place in the time with gain scheduling is found to be 1.6 ms, 200 𝜇𝑠
switch. shorter than the fixed gain case. It can thus be inferred that
To bring about a clear comparison between gain schedul- when the 𝑉𝑖𝑛 is at its lower extreme, an improvement in
ing and fixed gain control, both were implemented on the transient response is obtained with gain scheduling. When
prototype; and the transient response of the system, under 𝑉𝑖𝑛 = 60 𝑉 , no much of a change is brought through gain
both the schemes, were subjected to a direct comparison. scheduling, as the gain of the controller has the same value
Fig. 8 shows the output voltage transients produced, for a as the fixed gain case.
step change in 𝐼𝑜𝑢𝑡 from 1 A to 5 A; here 𝑉𝑖𝑛 = 25 𝑉 . The The behaviour of the scheduling process under dynamic
peak transients in both cases is limited to 18%, but with gain conditions is illustrated in Fig. 10. It shows the output
scheduling, the settling time (5% criterion) is about 1.4 ms; voltage transients, for a step application of 𝑉𝑖𝑛 = 25 𝑉 ,
1 ms shorter than the fixed gain case, an improvement of under full load conditions. The overshoot and settling time
about 42%. in the fixed gain case is 22% and 4.5 ms respectively, while
The transients produced, when 𝐼𝑜𝑢𝑡 changes as a step from

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 20 ACKNOWLEDGMENT
Fixed gain
Gain scheduled The authors would like to thank Bineesh P. C. for his
15 helpful suggestions.
R EFERENCES
Output voltage (V)

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