Electronic Devices
Final Term
Lecture - 05
Reference book:
Electronic Devices and Circuit Theory
(Chapter-6)
Robert L. Boylestad and L. Nashelsky , (11th Edition)
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American International University-Bangladesh
TRANSFER CURVE
• To determine ID given VGS:
I D k (VGS VT ) 2
• where VT = threshold voltage or voltage at which
the MOSFET turns on.
• k = constant found in the specification sheet
• k can also be determined by using values at a
specific point and the formula:
ID(on)
k
(VGS(ON) VT) 2
• VDSsat can also be calculated:
VDsat VGS VT
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P -CHANNEL ENHANCEMENT-TYPE MOSFETS
• The p-channel Enhancement-type MOSFET is similar to the n-channel except that the
voltage polarities and current directions are reversed.
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SYMBOLS
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DEPLETION-TYPE MOSFET CONSTRUCTION
• The Drain (D) and Source (S) connect to the to
n-doped regions.
• These N-doped regions are connected via an n-
channel. This n-channel is connected to the
Gate (G) via a thin insulating layer of SiO2.
• The n-doped material lies on a p-doped
substrate that may have an additional terminal
connection called SS.
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BASIC OPERATION
• In Fig. 6.25 the gate-to-source voltage is
set to 0 V by the direct connection from
one terminal to the other, and a voltage
VDD is applied across the drain-to-source
terminals.
• The result is an attraction of the free
electrons of the n-channel for the positive
voltage at the drain.
• The result is a current similar to that
flowing in the channel of the JFET. In fact,
the resulting current with VGS = 0 V
continues to be labeled IDSS.
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BASIC OPERATION
• A Depletion MOSFET can operate in two modes: Depletion or Enhancement mode.
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BASIC OPERATION CONTD.
• In this figure VGS has been set at a negative voltage such as 1 V. The
negative potential at the gate will tend to pressure electrons toward
the p-type substrate (like charges repel) and attract holes from the p-
type substrate (opposite charges attract).
• Depending on the magnitude of the negative bias established by
VGS, a level of recombination between electrons and holes will occur
that will reduce the number of free electrons in the n-channel
available for conduction. The more negative the bias, the higher the
rate of recombination.
• The resulting level of drain current is therefore reduced with
increasing negative bias for VGS for VGS =1 V, 2 V, and so on, to the
pinch-off level of 6 V. The resulting levels of drain current and the
plotting of the transfer curve proceeds exactly as described for the
JFET.
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DEPLETION-TYPE MOSFET IN DEPLETION MODE
• Depletion mode:
• The characteristics are similar
to the JFET.
• When VGS = 0V, ID = IDSS
• When VGS < 0V, ID < IDSS
• The formula used to plot the
Transfer Curve still applies:
VGS 2
ID IDSS(1 )
VP
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ENHANCEMENT MODE
• For positive values of VGS, the positive gate will draw additional electrons (free carriers)
from the p-type substrate due to the reverse leakage current and establish new
carriers through the collisions resulting between accelerating particles.
• As the gate-to-source voltage continues to increase in the positive direction, the drain
current will increase at a rapid rate.
• The application of a positive gate-to-source voltage has “enhanced” the level of free
carriers in the channel compared to that encountered with VGS =0 V. For this reason
the region of positive gate voltages on the drain or transfer characteristics is often
referred to as the enhancement region,
• The region between cutoff and the saturation level of IDSS referred to as the depletion
region.
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DEPLETION-TYPE MOSFET IN ENHANCEMENT
MODE
• Enhancement mode:
• VGS > 0V, ID increases above IDSS.
• The formula used to plot the
Transfer Curve still applies:
(note that VGS is now a positive
polarity)
VGS 2
ID IDSS(1 )
VP
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P-CHANNEL DEPLETION-TYPE MOSFET
• The p-channel Depletion-type MOSFET is similar to the n-channel except that the
voltage polarities and current directions are reversed.
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SYMBOLS
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SUMMARY TABLE
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MOSFET HANDLING
• MOSFETs are very static sensitive. Because of the very thin
SiO2 layer between the external terminals and the layers of
the device, any small electrical discharge can stablish an
unwanted conduction.
• Protection:
• Always transport in a static sensitive bag.
• Always wear a static strap when handling MOSFETS.
• Apply voltage limiting devices between the Gate and
Source, such as back-to-back Zeners to limit any
transient voltage.
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CMOS
• CMOS – Complementary MOSFET p-
channel and n-channel MOSFET on the
same substrate.
• Advantage:
• Useful in logic circuit designs
• Higher input impedance
• Faster switching speeds
• Lower operating power levels
• Application:
• CMOS Inverter
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CMOS INVERTER
• An inverter is a logic element that “inverts” the applied signal. That
is, if the logic levels of operation are 0V (0-state) and 5V (1-state),
an input level of 0V will result in an output level of 5V, and vice
versa.
• Here, both gates are connected to the applied signal and both
drain to the output Vo. The source of the p-channel MOSFET
(Q2) is connected directly to the applied voltage VSS, while the
source of the n-channel MOSFET (Q1) is connected to ground.
• Here, the application of 5V at the input should result in
approximately 0 V at the output. With 5V at Vi (with respect to
ground), VGS1 = Vi and Q1 is “on,” resulting in a relatively low
resistance between drain and source.
• Since Vi and VSS are at 5 V, VGS2 = 0 V, which is less than the
required VT for the device, resulting in an “off” state. The resulting
resistance level between drain and source is quite high for Q2.
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CMOS INVERTER
• A simple application of the voltage-divider rule will
reveal that Vo is very close to 0 V or the 0-state,
establishing the desired inversion process.
• For an applied voltage Vi of 0V (0-state), VGS1 = 0V
and Q1 will be off with VSS2 =-5V, turning on the p-
channel MOSFET. The result is that Q2 will
present a small resistance level, Q1 a high
resistance, and Vo =VSS =5 V (the 1-state).
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End of Lecture-5
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American International University-Bangladesh
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