Serial Audio Interface ( SAI )

02/07/2015 STM32L476 Technical Training

 SAI Introduction
The SAI interface (Serial Audio Interface) is a peripheral
supporting a wide set of audio protocols thanks to its
flexible architecture:
• I2S Philips standards, (Inter-IC Sound),

• I2S LSB or MSB-justified, (Variant of Inter-IC Sound),

• SPDIF Output, (Sony/Philips Digital InterFace)

• PCM, (Pulse Code Modulation)

• TDM, (Time Division Multiplexing)

• AC’97, (Audio Codec ’97 from Intel)

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 SAI Features(1/2)
• A SAI embeds two independent audio sub-blocks
which can be:
• Transmitter and/or receiver
• Master or slave
• Synchronous or asynchronous mode between the audio sub-blocks
• Clock generator for each audio sub-block to target independent audio frequency sampling

• 8-word integrated FIFOs for each audio sub-block.

• Up to 16 slots available
• Mute mode
• Stereo/Mono audio frame capability.
• Companding mode supporting µ-Law and A-Law.

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 SAI Features(2/2)
• Flexible serial interface:
– Configurable data justification (LSB or MSB first),
– Configurable data and slot size,
– Configurable sampling edge for the Communication clock,
– Configurable number of bits per frame,
– Configurable data position within a slot,
– Configurable frame synchronization active level,
– Configurable frame shape
• 2 DMA interfaces : one for each audio sub-block
• 2 Interrupt lines: one for each audio sub-block

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 SAI Block Diagram
STM32L476/486
Interrupt DMA
Request APB bus Request

SAIx
APB Interface

SYNC
Sync Out

OUT
Sub-Block A

SAI_CK_A Clock generator FIFO Serial FS_A

IO Line Management
Sub-Block A 8 x 32b Interface SCK_A
PLL_P SD_A
MCLK_A
PLLSAI1_P

PLLSAI2_P
Sub-Block B FS_B
SAIxEXTCLK
Clock generator FIFO Serial SCK_B
SD_B
SAI_CK_B Sub-Block B 8 x 32b Interface
MCLK_B

SYNC
Sync In

IN
APB Interface

Interrupt APB bus DMA

Request Request

Signal Dir Description

FS_A, FS_B I/O Frame synchronization
SCK_A, SCK_B I/O Bit clock sampling the serial data
SD_A, SD_B I/O Serial Data
02/07/2015MCLK_A, MCLK_B O
STM32L476 Technical Training
Master Clock: can be requested to provide a clock to external codecs
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CMP CMP CMP

STM32L476 Technical Training

SAI In The System

SYNC IO Line SYNC SYNC IO Line SYNC

IN Management OUT IN Management OUT
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 SAI: Internal Synchronization examples (1/3)
• Synchronization of 2 sub-blocks Interrupt
Request
TX or RX - MASTER DMA
Request

SAIx
APB Interface
Sync Out

Sub-Block A

SAI_CK_A Clock generator FIFO Serial FS_A (O)

Sub-Block A 8 x 32b Interface SCK_A (O)
SD_A (I/O)

• MASTER full-duplex or dual lane MCLK_A (O)

Sub-Block B FS_B
Clock generator FIFO Serial SCK_B
SD_B (I/O)
SAI_CK_B Sub-Block B 8 x 32b Interface
MCLK_B

Sync In
APB Interface

Those IOs can be

Interrupt DMA
used by another
STM32L476/486 Request
TX or RX - SLAVE Request function

SYNC
OUT
IO Line Management
• SLAVE full-duplex or dual lane

SYNC
IN
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 SAI: External Synchronization examples (2/3) Interrupt TX or RX - SLAVE DMA

• Synchronization of 2 SAIs Request Request

SAI2
APB Interface
Sync Out

Sub-Block A

SAI_CK_A Clock generator FIFO Serial FS2_A

Sub-Block A 8 x 32b Interface SCK2_A
SD2_A (IO)
MCLK2_A
• Up to four data lanes can work
Sub-Block B
simultaneously Clock generator FIFO Serial
FS2_B
SCK2_B
SD2_B (IO)
SAI_CK_B Sub-Block B 8 x 32b Interface
MCLK2_B

• Minimum IO impact thanks to APB Interface Those IOs, can be

used by another
internal “IO Line manager” Interrupt
TX or RX - SLAVE DMA
function
Request Request

STM32L476/486
Interrupt TX or RX - MASTER DMA
Request Request Synchro !!!

SAI1
APB Interface

Sub-Block A

SAI_CK_A Clock generator FIFO Serial FS1_A (O)

Sub-Block A 8 x 32b Interface SCK1_A (O)
SD1_A (IO)
MCLK1_A (O)

Sub-Block B FS1_B
SCK1_B
Clock generator FIFO Serial
SD1_B (IO)
SAI_CK_B Sub-Block B 8 x 32b Interface
MCLK1_B
Sync In
APB Interface

Those IOs, can be

used by another
Interrupt
Request
TX or RX - SLAVE DMA
Request
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function
 SAI: Synchronous mode examples (3/3)
• Several other configurations are supported:
• If the internal and external synchronization is not used, each sub-block is
independent.
Some examples:
• SAI_A in I2S Philips Master, SAI_B in SPDIF
• SAI_A in TDM SLAVE, SAI_B in AC97
• …
• If the internal or external synchronization is used, the following limitations must be
respected:
• It is not possible to synchronize 2 SAI Sub-Blocks using different protocols characteristics.
• It is not possible to synchronize 2 SAIs using different protocols characteristics.

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 FIFO Feature
• Each audio block in the SAI has its own FIFO
• FIFO depth is 8 words
• CPU or DMA access to the FIFOs
• Data is right-aligned into the FIFO.
• FIFO FLUSH bit to reinitialized the FIFO pointers
• Each access in read from the FIFO will return a word (32-
bit) equivalent to one data
• Each write into the DR will correspond to the FIFO to one
data.
• Programmable FIFO threshold to manage data transfert:
– FIFO FULL, ¾ FIFO, ½ FIFO, ¼ FIFO, FIFO EMPTY

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 Free Protocol Description
The Free protocol (PRTCFG = 0) must be
selected to configure the SAI in:
• I2S Philips Standard mode
• I2S MSB/LSB justified
• TDM mode
• PCM mode

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 Audio Clock configuration
• The clock generators are used only in MASTER mode.
When MCLK is generated (NODIV = 0) When MCLK is not generated (NODIV = 1)

=
256 =
+1
_ (1)
=
2 × = _

= × +1 FRL+1 = any values between 8 and 256

FRL+1 = 8, 16, 32, 64 128 or 256

(1)
When MCKDIV = 0
FMCLK = FSAI_CK

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 Frame synchronization (1/2)
Adjustable parameters
– The Frame length (FRL) • The Channel side identification (FSDEF)
– The Frame active length (FSALL)
– The Frame polarity (FSPOL) • The Frame offset (FSOFF)

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 Frame synchronization (2/2)
• The FS signal shape is completely configurable in order to
target the different audio protocols with their own
specificities.
• The Frame Synchronization signal (FS) role depends on
audio protocol:
– Start of frame, like for instance the PCM/DSP, TDM, AC’97, audio
protocols,
– Start of frame and a channel side identification within the audio
frame like for the I2S, the MSB or LSB-justified protocols
• The Frame synchronization active length can be set from 1
to 128 bit clock.
• The FS active length is usually:
– Half of the frame length in I2S, LSB or MSB-justified modes
– one-bit wide for PCM/DSP or TDM mode
– 16-bit length in AC’97
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 Frame length
• Master mode:
– The audio frame length can be configured up to 256 bit clock,
– If the frame length is greater than the number of declared slots for the
frame, the remaining bits to be transmitted will be extended to 0 or
the SD line will be released to HI-z depending the state of bit TRIS in
the SAI_xCR2 register. In reception mode, the remaining bits are
ignored.
• Slave mode:
– The audio frame length must be used in order to specify to the slave
the number of bit clocks per audio frame sent by the external master.
This feature can be used to detect signal quality errors.
• FS transitions are automatically monitored in order to detect a wrong
placement of the start of frame by generating either an anticipated or late
frame synchronization detection.

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 Audio Slot configuration(1/2)
• The maximum number of slots per audio frame is fixed to 16
– Configured through bits “NBSLOT[3:0] in the SAI_xSLOTR register +1”.
• Each slot can be defined as an active slot, or not
– By setting bit SLOTEN[15:0] in the SAI_xSLOTR register.
• The size of the slots is selected by setting bit SLOTSZ in the
SAI_xSLOTR register.
• It is possible to define the data position into the slot (FBOFF)

02/07/2015 STM32L476 Technical Training 57

 Audio Slot configuration(2/2)
• During the transfer of a inactive slot, 0 value will be forced on the
SD line or the SD line will be released to HI-z depending on TRIS bit
setting in the SAI_xCR2 register
No request to read or write the FIFO linked to this inactive slot

02/07/2015 STM32L476 Technical Training 58

 Specific Feature: Mute Mode
• SAI Transmitter:
– Mute mode can be selected at anytime during an on-going
frame
– Mute mode starts by setting the MUTE bit in SAI_xCR2 register:
– The mute mode bit is strobed only at the end of the frame to
determine if the next frame will be a mute frame or not.
– During Mute mode:
• The FIFO pointers are still incremented.
• SAI still sending bit value 0 or Last values depend of MUTEVAL bit
setting in SAI_xCR2
• SAI Receiver: Mute mode starts by setting the MUTE bit.
– A frame is detected as MUTE when all the active slots have been
strobed with only 0 on SD line in input.
– FLAG MUTEDET is set and an interrupt generated (if enabled),
when the number of consecutive Mute frame is equal to
number set into MUTECNT bits In SAI_xCR2 .
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 Specific Feature: Companding Mode
• Two companding modes are supported: μ-Law and the A-Law log
which are a part of the CCITT G.711 recommendation
• The companding standard employed in the United States and Japan
is the μ-Law and allows 14 bits bits of dynamic range
• The European companding standard is A-Law and allows 13 bits of
dynamic range.
• The μ-Law and A-Law formats encode data into 8-bit code elements
with MSB alignment. Companded data is always 8 bits wide
• Companding standard (μ-Law or A-Law) can be computed based on
1’s complement or 2’s complement representation depending on
the CPL bit setting in the SAI_xCR2 register.

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 Specific Protocol Description
• SPDIF Protocol
• AC’97 Protocol

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 SPDIF Protocol (1/5)
The SAI can provide audio samples using SPDIF protocol.
• To select the SPDIF protocol, set PRTCFG[1:0] in the SAI_xCR1 register
to 01.

– On SPDIF mode, only SD_x IO is used, other IOs are free.

– The data size is forced to 24 bits.
– The data are Manchester encoded (or biphase-mark)
– The SAI generates automatically the preambles
– The SAI generates automatically the parity
– The application has to handle the CS, U and V bit

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 SPDIF Protocol (2/5)
• Symbol Rate:
– The audio sample rate (FS) can be adjusted using the following formula:

FSAI_CK Audio sample rate

_
= 2.8224 MHz 44.1 kHz
64
3.072 MHz 48 kHz
6.144 MHz 96 kHz

• Data format:
• The data register must contain CS,U and V bits, plus the data

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•
SPDIF Protocol (3/5)
The block structure is used to organize the Channel Status, and User
information.
– Each block contains 192 frames
– Each frame contains 2 sub-frames
– Each sub-frame contains 32 bits
– A preamble allows the detection of the block and sub-frame
boundaries
• Preamble B detects the start of new block, and the start of a Channel A
• Preamble M detects the start of a Channel A (when it is not a block boundary)
• Preamble W detects the start of a Channel B

X Y Z Y X Y X Y Z Y
M Ch A W Ch B B Ch A W Ch B M Ch A W Ch B M Ch A W Ch B B Ch A W Ch B

Sub-frame Sub-frame

Frame 191 Frame 0 Frame 1 Frame 191 Frame 0

Start of block Start of block

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•
SPDIF Protocol
Each sub-frame contains
(4/5)
– The preamble
– Up to 24-bit data
– 4 Status bits
• V is the validity bit, it means that the current sample can be directly
converted into an analog signal.
• P is the parity bit of the received sub-frame, it is used to check the
received sub-frame
• U: Is the User data channel, each message is composed of 192 bits
• CS: Is the Channel Status, each message is composed of 192 bits (i.e.
sampling rate, sample length….)

02/07/2015 STM32F7xx Technical Training 65

 SPDIF Protocol
• Biphase-mark data encoding
(5/5)

• Preambles
• The preambles are ‘violating’ the biphase-mark code rules
0 1 2 3

1 UI 2 UI 3 UI 4 UI 5 UI 6 UI 7 UI 8 UI
Previous half-bit = 0

Preamble “B”
Previous half-bit = 1
Missing Transitions !!!
Previous half-bit = 0

Preamble “M”
Previous half-bit = 1

Previous half-bit = 0

Preamble “W”
Previous half-bit = 1
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 AC’97 protocol(1/2)
• The SAI is able to work as an AC’97 link controller.
– To select the AC 97 protocol, set bit PRTCFG[1:0] in the
SAI_xCR1 register to 10.
• The number of slot is fixed to 13 slots:
– Tag slot :slot 0 (16-bit),
– Data slots: slot 1 to slot 12 (20-bit)
Bit FBOFF[5:0] in the SAI_xSLOTR register is ignored
• The frame length is fixed to 256-bit
The SAI_xFRCR register is ignored

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 AC’97 protocol(2/2)
Slot # 0 1 2 3 4 5 6 7 8 9 10 11 12 0

FS (SYNC)

CMD CMD PCM PCM LINE 1 PCM PCM PCM PCM LINE2 HSET IO
DATA_Out TAG
ADDR DATA Center L.SUPR R.SUPR LFE DAC DAC CTRL
TAG
L.Front R.Front DAC

Codec ID: to select target codec

Status Status PCM PCM LINE 1 PCM LINE2 HSET IO

DATA_In TAG
ADDR DATA LEFT RIGHT DAC MIC RSRVD RSRVD RSRVD DAC DAC Status TAG

Slot Request bits to request data from Outgoing Slots from 3 to 12

TAG
PHASE DAT PHASE

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 Anticipated/Late Frame Error
• In SLAVE mode, the FRL must be programmed according to the
frame length provided by the MASTER.
• FRL value is also used to check if the FS active edge occurs at the
expected moment. Anticipated or Late FS error can be detected.
• To resynchronize with the master after Anticipated or Late frame
detection error, four steps should be respected:
1. Disable the SAI (SAIxEN = 0)
2. Flush the FIFO
3. Re-enable the SAI
SAI block will wait for the assertion of FS to restart the synchronization
with master

This detection and flag assertion can detect glitches on the SCK
Clock/FS due to a noisy environment

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 Overrun/Underrun handling
• The FIFO overrun or underrun errors occupy the same bit:
OVRUDR
• The SAI guarantees the data alignment even if underrun
overrun occurs
• Example : FIFO Overrun on Slot 1

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 SAI Interrupt Sources
Interrupt Interrupt How to clear interrupt
Description
source group
FREQ FREQ FIFO request (FIFO threshold reached) SAI_xDR read or write (2)
OVRRUDR Overrun/Underrun error COVRUDR = 1
AFSDET Anticipated frame sync. detected CAFSDET = 1
LFSDET ERROR Late frame sync. detected CLFSDET = 1
CNRDY Codec Not Ready (only in AC’97 mode) CCNRDY = 1
WCKCFG Wrong frame length configuration (1) CWCKCFG = 1
MUTEDET MISC Mute detection CMUTEDET = 1

(1) When WCKCFG is set to 1, the SAI is automatically disabled (SAIxEN=0)

(2) More precisely, when the FIFO level is below the threshold

02/07/2015 STM32L476 Technical Training 71

 I2S Philips Standard at 48 kHz, MASTER
Field name Values Comments
MCKDIV 0 No division
NODIV 0 Generation of the MCLK
CKSTR 1 Signal changed on falling edge
DS 5 20-bit data size
SYNCEN 0 No need to sync the two SAI sub-blocks
LSBFIRST 0 MSb first
MODE 0 Master transmitter
PRTCFG 0 Free protocol for I2S
• FSAI_CK = 12.288 MHz
FRL 63d 64 bits per frame (must be a power of 2 !!)
FSALL 31d 32 bits on each channel
FSOFF 1 First bit starts 1 bit after FS transition
FSPOL 0 FS is active LOW
FSDEF 1 Side channel identification activated for right channel
FBOFF 0 No data offset inside the slot
SLOTSZ 2 Slot size = 32 bits
NBSLOT 1 2 slots structure (Left + right)
SLOTEN 3 Slot 0 and Slot 1 are used and enabled
MSb

MSb

MSb
LSb

LSb

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