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IMPORTANT FEATURES OF 8086:

1) Buses:

Address Bus: 8086 has a 20-bit address bus, hence it can access 220 Byte memory i.e. 1MB. The
address range for this memory is 00000H … FFFFFH.

Data Bus: 8086 has a 16-bit data bus i.e. it can access 16 bit data in one operation. Its ALU and
internal data registers are also 16-bit.
Hence 8086 is called as a 16-bit µP.

Control Bus: The control bus carries the signals responsible for performing various operations such
as RD , WR etc.

2) 8086 supports Pipelining.

It is the process of “Fetching the next instruction, while executing the current instruction”.
Pipelining improves performance of the system.

3) 8086 has 2 Operating Modes.

i. Minimum Mode … here 8086 is the only processor in the system (uni-processor).
ii. Maximum Mode … 8086 with other processors like 8087-NDP/8089-IOP etc.
Maximum mode is intended for multiprocessor configuration.

4) 8086 provides Memory Banks.

The entire memory of 1 MB is divided into 2 banks of 512KB each, in order to transfer 16-
bits in 1 cycle. The banks are called Lower Bank (even) and Higher Bank (odd).

5) 8086 supports Memory Segmentation.

Segmentation means dividing the memory into logical components. Here the memory is divided into 4
segments: Code, Stack, Data and Extra Segment.

6) 8086 has 256 interrupts.

The ISR addresses for these interrupts are stored in the IVT (Interrupt Vector Table).

7) 8086 has a 16-bit IO address ∴ it can access 216 IO ports (216 = 65536 i.e. 64K IO Ports).

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 8086 MICROPROCESSOR
Author: Bharat Acharya
Sem IV – Electronics
Mumbai 2018

ARCHITECTURE OF 8086

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As 8086 does 2-stage pipelining, its architecture is divided into two units:
1. Bus Interface Unit (BIU)
2. Execution Unit (EU)

BUS INTERFACE UNIT (BIU)

1. It provides the interface of 8086 to other devices.
2. It operates w.r.t. Bus cycles .
This means it performs various machine cycles such as Mem Read, IO Write etc to transfer data with
Memory and I/O devices.
3. It performs the following functions:
a) It generates the 20-bit physical address for memory access.
b) Fetches Instruction from memory.
c) Transfers data to and from the memory and IO.
d) Supports Pipelining using the 6-byte instruction queue.

The main components of the BIU are as follows:

a) SEGMENT REGISTERS:
1) CS Register
CS holds the base (Segment) address for the Code Segment.
All programs are stored in the Code Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Code Segment.
Eg: If CS = 4321H then CS × 10H = 43210H è Starting address of Code Segment.
CS register cannot be modified by executing any instruction except branch instructions

2) DS Register
DS holds the base (Segment) address for the Data Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Data Segment.
Eg: If DS = 4321H then DS × 10H = 43210H è Starting address of Data Segment.

3) SS Register
SS holds the base (Segment) address for the Stack Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Stack Segment.
Eg: If SS = 4321H then SS × 10H = 43210H è Starting address of Stack Segment.

4) ES Register
ES holds the base (Segment) address for the Extra Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Extra Segment.
Eg: If ES = 4321H then ES × 10H = 43210H è Starting address of Extra Segment.

b) Instruction Pointer (IP register)

It is a 16-bit register.
It holds offset of the next instruction in the Code Segment.

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 8086 MICROPROCESSOR
Author: Bharat Acharya
Sem IV – Electronics
Mumbai 2018

Address of the next instruction is calculated as CS x 10H + IP.

IP is incremented after every instruction byte is fetched.
IP gets a new value whenever a branch occurs.

c) Address Generation Circuit

The BIU has a Physical Address Generation Circuit. It generates the 20-bit physical address using
Segment and Offest addresses using the formula:

Physical address = Segment Address x 10h + Offset Address

Viva Question: Explain the real procedure to obtain the Physical Address?
The Segment address is left shifted by 4 positions, this multiplies the number by 16 (i.e. 10h) and then the offset address is
added.
Eg: If Segment address is 1234h and 0ffset address is 0005h, then the physical address (12345h) is calculated as follows:
1234h = (0001 0010 0011 0100)binary
Left shift by four positions and we get (0001 0010 0011 0100 0000)binary i.e. 12340h
Now add (0000 0000 0000 0101)binary i.e. 0005h and we get (0001 0010 0011 0100 0101)binary i.e. 12345h.

d) 6-Byte Pre-Fetch Queue {Pipelining – 4m}

It is a 6-byte FIFO RAM used to implement Pipelining.
Fetching the next instruction while executing the current instruction is called Pipelining.
BIU fetches the next “six instruction-bytes” from the Code Segment and stores it into the queue.
Execution Unit (EU) removes instructions from the queue and executes them.
The queue is refilled when atleast two bytes are empty as 8086 has a 16-bit data bus.
Pipelining increases the efficiency of the µP.
Pipelining fails when a branch occurs, as the pre-fetched instructions are no longer useful.
Hence as soon as 8086 detects a branch operation, it clears/discards the entire queue. Now, the next
six bytes from the new location (branch address) are fetched and stored in the queue and Pipelining
continues.

NON-PIPELINED PROCESSOR EG: 8085

Time
F1 E1 F2 E2 F3 E3 F4 E4 F5 E5

Total time taken

PIPELINED PROCESSOR EG: 8086

Time
F1 E1 E2 E3 E4 E5
F2 F3 F4 F5
Overlapping fetching
and execution

Total time taken

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Execution Unit (EU)

1. It fetches instructions from the Queue in BIU, decodes and executes them.
2. It performs arithmetic, logic and internal data transfer operations.
3. It sends request signals to the BIU to access the external module.
4. It operates w.r.t. T-States (clock cycles). ☺For doubts contact Bharat Sir on 98204 08217

The main components of the EU are as follows:

a) General Purpose Registers

8086 has four 16-bit general-purpose registers AX, BX, CX and DX. These are available to the
programmer, for storing values during programs. Each of these can be divided into two 8-bit
registers such as AH, AL; BH, BL; etc. Beside their general use, these registers also have some
specific functions.

AX Register (16-Bits)
It holds operands and results during multiplication and division operations.
All IO data transfers using IN and OUT instructions use A reg (AL/AH or AX).
It functions as accumulator during string operations.
BX Register (16-Bits)
Holds the memory address (offset address), in Indirect Addressing modes.

CX Register (16-Bits)
Holds count for instructions like: Loop, Rotate, Shift and String Operations.

DX Register (16-Bits)
It is used with AX to hold 32 bit values during Multiplication and Division.
It is used to hold the address of the IO Port in indirect IO addressing mode.

b) Special Purpose Registers

Stack Pointer (SP 16-Bits)
It is holds offset address of the top of the Stack. Stack is a set of memory locations operating
in LIFO manner. Stack is present in the memory in Stack Segment.
SP is used with the SS Reg to calculate physical address for the Stack Segment. It used during
instructions like PUSH, POP, CALL, RET etc. During PUSH instruction, SP is decremented by 2 and
during POP it is incremented by 2.

Base Pointer (BP 16-Bits)

BP can hold offset address of any location in the stack segment.
It is used to access random locations of the stack. #Please refer Bharat Sir's Lecture Notes for this ...

Source Index (SI 16-Bits)

It is normally used to hold the offset address for Data segment but can also be used for other
segments using Segment Overriding. It holds offset address of source data in Data Seg, during
String Operations.

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 8086 MICROPROCESSOR
Author: Bharat Acharya
Sem IV – Electronics
Mumbai 2018

Destination Index (DI 16-Bits)

It is normally used to hold the offset address for Extra segment but can also be used for other
segments using Segment Overriding. It holds offset address of destination in Extra Seg, during
String Operations.

c) ALU (16-Bits)
It has a 16-bit ALU. It performs 8 and 16-bit arithmetic and logic operations.

d) Operand Register
It is a 16-bit register used by the control register to hold the operands temporarily.
It is not available to the Programmer.

e) Instruction Register and Instruction Decoder (Present inside the Control Unit)
The EU fetches an opcode from the queue into the Instruction Register. The Instruction
Decoder decodes it and sends the information to the control circuit for execution.

f) Flag Register (16-Bits)

It has 9 Flags.
These flags are of two types: 6-Status (Condition) Flags and 3-Control Flags.
Status flags are affected by the ALU, after every arithmetic or logic operation. They give the status
of the current result.
The Control flags are used to control certain operations.
They are changed by the programmer.

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STATUS FLAGS

1) Carry flag (CY)

It is set whenever there is a carry {or borrow} out of the MSB of a the result
(D7 bit for an 8-bit operation D15 bit for a 16-bit operation)
2) Parity Flag (PF)
It is set if the result has even parity.
3) Auxiliary Carry Flag (AC)
It is set if a carry is generated out of the Lower Nibble.
It is used only in 8-bit operations like DAA and DAS.
4) Zero Flag (ZF)
It is set if the result is zero.
5) Sign Flag (SF)
It is set if the MSB of the result is 1.
For signed operations, such a number is treated as –ve.

6) Overflow Flag (OF)

It will be set if the result of a signed operation is too large to fit in the number of bits available to
represent it. It can be checked using the instruction INTO (Interrupt on Overflow). #Please refer Bharat Sir's
Lecture Notes for this ...

CONTROL FLAGS

1) Trap Flag (TF)

It is used to set the Trace Mode i.e. start Single Stepping Mode.
Here the µP is interrupted after every instruction so that, the program can be debugged.
2) Interrupt Enable Flag (IF)
It is used to mask (disable) or unmask (enable) the INTR interrupt.

3) Direction Flag (DF)

If this flag is set, SI and DI are in auto-decrementing mode in String Operations.

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