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Lab 6-DLD

Dld Lab06

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Rizwan Latif
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33 views7 pages

Lab 6-DLD

Dld Lab06

Uploaded by

Rizwan Latif
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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International Islamic University Islamabad

Faculty of Engineering and Technology


Department of Electrical and Computer Engineering

DIGITAL LOGIC DESIGN LAB

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map

Name of Student: …………………………………..

Roll No.: ……………………………………………

Section: …………………………………………….

Date of Experiment: ………………………………..

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map Page 1


Objectives:
 Develop the truth table for a BCD invalid code detector.
 Use a Karnaugh map to simplify the expression.
 Build and test a circuit that implements the simplified expression.
Equipment Required:
 DMM
 Logic Probe
 Breadboard
 Digital Trainer
 IC: 7400 quad 2-input NAND gate [Qty = 1]
 Resistors: 330-Ω [Qty = 1], 1-kΩ [Qty = 4]
 Connecting wires
Theory:
A powerful mapping technique for simplifying combinational logic circuits was developed by
M. Karnaugh and was described in a paper he published in 1953.The method involved writing
the truth table into a geometric map in which adjacent cells (squares) differ from each other in
only one variable. (Adjacent cells share a common border horizontally or vertically.) When you
are drawing a Karnaugh map, the variables are written in a Gray code sequence along the sides
and tops of the map. Each cell on the map corresponds to one row of the truth table. The output
variables appear as 0’s and 1’s on the map in positions corresponding to those given in the truth
table.

Table 6.1: Truth Table for comparator


Inputs Output
A2 A1 B2 B1 X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map Page 2


As an example, consider the design of a 2-bit comparator. The inputs will be called A 2 A1
and B2 B1 the desired output is HIGH if A2 A1 is equal to or greater than B2 B1.To begin, the
desired output is written in the form of a truth table, as given in Table 6.1. All possible inputs are
clearly identified by the truth table and the desired output for every possible input is given.
Next the Karnaugh map is drawn, as shown in Figure 6.1. In this example, the map is
drawn using numbers to represent the inputs. The corresponding values for the output function
are entered from the truth table. The map can be read in sum-of-products (SOP) form by
grouping adjacent cells containing 1’s on the map. The size of the groups must be an integer
power of 2 (1, 2, 4, 8, etc.) and should contain only 1’s.The largest possible group should be
taken; all 1’s must be in at least one group and may be taken in more than one group if helpful.
After grouping the 1’s on the map, the output function can be determined. Each group is
read as one of the product terms in the reduced output function. Within each group larger than
one, adjacent boundaries will be crossed, causing the variable that changes to be eliminated
from the output expression. A group of two adjacent 1’s will have a single adjacent boundary
and will eliminate one variable. A group of four 1’s will eliminate two variables and a group of
eight 1’s will eliminate three variables. Figure 6.1 shows the groupings for the 2-bit comparator.
Since each group in this case is a group of four 1’s,each product term contains two
variables (two were eliminated from each term). The resulting expression is the sum of all of the
product terms. The circuit can be drawn directly, as shown in Figure 6.2.

Figure 6.1: Karnaugh Map for the Truth Table shown in Table 6.1

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map Page 3


Figure 6.2: Circuit implementation of the comparator given by Truth Table (Table 6.1)

In this experiment, you will use the Karnaugh mapping method to design a BCD invalid code
detector. As you know, BCD is a 4-bit binary code that represents the decimal numbers 0
through 9. The binary numbers 1010 through 1111 are invalid in BCD.You will design a
circuit to assure that only valid BCD codes are present at the input and will signal a warning
if an invalid BCD code is detected.
Procedure:
BCD Invalid Code Detector
a. Complete the truth table shown as Table 6.2 in the report. Assume the output for the ten
valid BCD codes is a 0 and for the six invalid BCD codes is a 1. As usual for
representing numbers, the most significant bit is represented by the letter D and the
least significant bit by the letter A.
b. Complete the Karnaugh map shown as Figure 6.3 in the report. Group the 1’s according to
the rules given in Theory section. Find the expression of the invalid codes by reading the
minimum SOP from the map. Write the Boolean expression in the space provided in the
report.
c. If you have correctly written the expression in step “b”, there are two product terms and you
will see that the letter D appears in both terms. This expression could be implemented
directly as a satisfactory logic circuit. By factoring D from each term, you will arrive at
another expression for invalid codes. Write the new expression in the space provided in the
report.
d. Recall that, for TTL logic, a LOW can light an LED without violating the I OL(16 mA)
specification but a HIGH causes the IOH (400 µA) specification to be exceeded. To avoid
this, the output is inverted and X is used to light the LED with a LOW logic level. The
circuit shown in Figure 6.4 implements the expression from Step 3 but with the output
inverted in order sink rather than source current.

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map Page 4


Figure 6.4

e. Although the circuit shown in Figure 6.4 satisfies the design requirements with only two
gates, it requires two different ICs. In some cases, this might be the best design. However,
using the universal properties of the NAND gate, the OR gate could be replaced with three
NAND gates. This change allows the circuit to be implemented with only one IC 7400.
Change the circuit in Figure 6.4 by replacing the OR gate with three NAND gates.
Draw the new circuit below.

f. Construct the circuit you drew in Step e. Test all combinations of the inputs and complete
truth Table 6.3 in the report. If you have constructed and tested the circuit correctly, the truth
table will be the same as Table 6.2.

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map Page 5


Report for Experiment 6
Objectives:

 Develop the truth table for a BCD invalid code detector.


 Use a Karnaugh map to simplify the expression.
 Build and test a circuit that implements the simplified expression.

Data and Observations:

Table 6.2: Truth Table for BCD invalid code detector Table 6.3: Truth Table for BCD invalid code detector
constructed in step e

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map Page 6


Minimum sum-of-products read from map:

X=

Factoring D from both product terms gives

X=

Figure 6.3: K-Map for Table 6.2

Proteus Task:
Apply the K-map reduction method on the following and implement the circuit on Proteus. Verify the circuit
by truth table.
I. F (A, B, C, D) = ∑(0, 2, 5, 7, 8, 10, 13, 15)
II. F (P, Q, R) = π(0,3,6,7)

Experiment No. 6: Logic Circuit Simplification using Karnaugh Map Page 7

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