DIGITAL ELECTRONICS LAB Department of EEE
CONTENT
PAGE
SL.NO DATE NAME OF THE EXPERIMENTS SIGNATURE
NO
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Exp. No: 1 Date:
VERIFICATION OF BASIC DIGITAL ICS
AIM:
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1.
Digital IC trainer kit - 1
2.
AND gate IC 7408 1
3.
OR gate IC 7432 1
4.
NOT gate IC 7404 1
5.
NAND gate IC 7400 1
6.
NOR gate IC 7402 1
7.
EX-OR gate IC 7486 1
8.
Connecting wires As required
THEORY:
a. AND gate:
An AND gate is the physical realization of logical multiplication operation. It is an
electronic circuit which generates an output signal of ‘1’ only if all the input signals are
‘1’.
b. OR gate:
An OR gate is the physical realization of the logical addition operation. It is an electronic
circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.
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C. NOT gate:
A NOT gate is the physical realization of the complementation operation. It is an electronic
circuit which generates an output signal which is the reverse of the input signal. A NOT gate is
also known as an inverter because it inverts the input.
D. NAND GATE
A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’ if all the
input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.
A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all the inputs
are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.
E. Ex-OR GATE
An Ex-OR gate performs the following Boolean function,
A B = ( A . B’ ) + ( A’ . B )
It is similar to OR gate but excludes the combination of both A and B being equal to one. The
exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal
either ‘0’ or ‘1’.
PROCEDURE:
1. Connections are given as per the circuit diagram
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for all gates.
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RESULT:
Thus the truth table of all the basic digital ICs was verified.
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CIRCUIT DIAGRAM:
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EX.NO: 2 DATE:
HALF ADDER AND HALF SUBTRACTOR
AIM
1. To design and set up half adder and half subtractor using
a. EXOR gates and AND gates
b. NAND gates
COMPONENTS REQUIRED
IC Trainer kit, IC 7400, IC 7486
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. EXOR gates, AND gates IC 7474 2
3. Connecting wires As required
THEORY
The simplest binary adder is called half adder. Half adder has two input bits and two
output bits. One output bit is the sum and the other is the carry. They are represented by‘S’
and ‘C’ respectively in logic symbol.
The simplest binary subtractor is called half Subtractor. It has two input bits and two
output bits. One output bit is the Difference and the other is borrowed. They are represented by
‘D’ and ‘B’ respectively in logic symbol
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TABULATION:
Truth table of Half Adder Truth table of Half Subtractor
Inputs Output Inputs Output
A B S C A B D BOR
0 0 0 0 0 0 0 0
0 1 1 0 0 1 1 1
1 0 1 0 1 0 1 0
1 1 0 1 1 1 0 0
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PROCEDURE:
1. Verify whether all the wires and components are in good condition
2. Set up a half adder circuit and feed all the input combinations
3. Observe the output corresponding to input combinations and enter it in the Truth
table
4. Repeat the above steps for half subtractor circuits
RESULT
Half adder and the half subtractor circuits are set up using logic gates and verified the
result.
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EX.NO: 3 DATE:
MULTIPLEXER AND DEMULTIPLEXER
AIM:
To construct the circuit of multiplexer and demultiplexer and to study their working
APPARATUS REQUIRED:
Sl..No Name of the apparatus Range Quantity
1. Digital IC trainer kit - 1
2 Connecting wires -
THEORY:
A Multiplexer is a combinational logic circuit, which can select any one of the numbers
of inputs and route it to a single output. Multiplexers are available with four, eight and sixteen
inputs and a single output. It is also called data selector. The basic multiplexer has several data
input lines and a single output line. The selection of a particular input line is controlled by a set of
selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations
determine which input is selected. Therefore, multiplexer is ‘many into one’ and it provides the
digital equivalent of an analog selector switch.
A Demultiplexer has a single input and many outputs. The input to a demultiplexer can
be routed to any of the output channels. For this reason, a demultiplexer is also known as data
distributor. The selection of specific output line is controlled by the values of n selection lines.
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PROCEDURE:
A) MULTIPLEXER:
1. Connect the circuit as per the circuit diagram.
2. For various inputs note the corresponding outputs.
3. Verify the truth table of multiplexer.
B. DEMULTIPLEXER:
1. Connect the circuit as per the circuit diagram.
2. For various inputs note the corresponding outputs.
3. Verify the truth table of demultiplexer
RESULT:
Multiplexer and Demultiplexer circuits were constructed and their operations were
verified.
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EX.NO: 4 DATE:
REALISATION OF FLIP FLOPS USING LOGIC GATES
AIM:
To verify the characteristic table of RS, D, JK, and T Flip flops .
APPARATUS REQUIRED:
S.NO NAME OF THE APPARATUS RANGE QUANTITY
1. Digital IC trainer kit 1
2. NOR gate IC 7402
3. NOT gate IC 7404
4. AND gate ( three input ) IC 7411
5. NAND gate IC 7400
6. Connecting wires As required
THEORY:
A Flip Flop is a sequential device that samples its input signals and
changes its output states only at times determined by clocking signal. Flip Flops
may vary in the number of inputs they possess and the manner in which the
inputs affect the binary states.
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RS FLIP FLOP
The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset
when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is
low. When both the inputs are high the output is in an indeterminate state.
D FLIP FLOP:
To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the
same time. This is obtained by making the two inputs complement of each other.
JK FLIP FLOP:
The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave
like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the
clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse. When the clock
pulse is zero both the AND gates are disabled and the Q and Q’ output retain their previous
values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the
inputs are high the output toggles continuously. This is called Race around condition and this
must be avoided.
T FLIP FLOP:
This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs
together. T Flip Flop is also called Toggle Flip Flop.
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PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and observe the status of all the flip flops.
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RESULT:
The Characteristic tables of RS, D, JK, T flip flops were verified.
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CIRCUIT DIAGRAM: ENCODER
DECODER:
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EX.NO: 5 DATE:
DESIGN AND IMPLEMENT ENCODER AND DECODER
AIM:
To design and implement encoder and decoder using logic gates.
APPARATUS REQUIRED:
SL.NO NAME RANGE QUANTITY
1 Nand gate 7408 1
2 OR gate 7432 3
3 NOR gate 7404 1
4 IC trainer kit - 1
5 Patch chords -
THEORY: ENCODER:
An encoder is a digital circuit that performs inverse operation of decoder.An encoder
has 2n input lines and n output lines.An encoder accepts an active level on one of its inputs
representing a digit such as a decimal/octal digit and it converts to coded output.Encoder
encodes different types of messages into various forms.In digital circuits it encodes a decimal
value into a binary word.
The encoded binary word has number of bits associated with it.The number of bits
depends upon the ddecimal value which is being encoded.For example in case decimal values
ranging from 0 to 7 the number of bits required to encode these values is 3.
DECODER:
A decoder is multi input and multi output combinational logic circuit which converts
coded input into coded outputs,where the input and output coded are different.
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TABULATION: ENCODER:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
TABULATION: DECODER:
INPUT OUTPUT
E A1 A0 D3 D2 D1 D0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
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PROCEDURE:
ENCODER:
1. Connect the supply from the trainer kit through patch cords;also connect
circuit as per circuit diagram.
2. Give the input to A,B &EN through switch.
3. Observe the output Y0 to Y3 on the trainer kit through LED’s.
ENCODER:
1. Connect the supply from the trainer kit through patch cords; also connect
circuit as per circuit diagram.
2. Give the connection to I0,I1,I2 &I3.
3. Observe the output Y0,Y1 on the trainer kit through LED’s.
RESULT:
Truth tables of encoder and decoder are verified.
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CIRCUIT DIAGRAM:
3-BIT ASYNCHRONOUS UP COUNTER
Clock QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
9 0 0 1
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EX.NO: 6 DATE:
DESIGN AND IMPLIMENTATION OF ASYNCHRONOUS
UP & DOWN COUNTER
AIM:
To design and implement the 3 bit up and down counter using IC 7476
APPARATUS REQUIRED: -
S.No Name of the Apparatus Range Quantity
1. IC - 7476 - 2
2. TRAINER kIT
3. Bread Board - 1
4. Connecting wires and probes As required
THEORY:
When counter is checked such that each flip flop on the counter is called asynchronous
counter. The clock signal is connected to the clock pulse of Ton and Toff condition. The first stage
is used to arrive the J and K input at 2nd stage.
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CIRCUIT DIAGRAM:
3-BIT ASYNCHRONOUS DOWN COUNTER
Clock QC QB QA
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1
9 1 1 0
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PROCEDURE:
1. Connections are made as per circuit diagram.
2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA, QB
& QC for IC 7476
3. Truth table is verified
RESULT:
Thus the asynchronous up and down counter truth table was verified .
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