Module 3

Shift Registers and

counters
 Register
● A register is a memory device that can be used
to store more than one-bit information
● A register is usually realized using several flip-
flops with common control signals that control
the movement of data to and from the register.
(shifting data 1s and 0s)
● A register can consist of one or more FF to
store and shift data.
● Functions of Register : data storage and data
movement
 Basic Shift Register Function

√ A number of FF’s connected together.

√ Data may be shifted into and shifted out of
them
√ Shifting of data may be in serial or in parallel
form
√ Data may be rotated left or right
√ Shift Register consists of an arrangement of
Flip-flops.
√ An n bit shift register needs ‘n’ D flip-flops
√ Important in applications, involving storage and
transfer data in digital system.
 Shift Registers
●Multi-bit register that moves stored data bits
left/right ( 1 bit position per clock cycle)

●Shift Left is towards MSB

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 1 1 1 LSI 1 1 1 LSI

●Shift Right (or Shift Up) is towards LSB

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
RSI 0 1 1 1 RSI 0 1 1
 The flip-flop as a storage element

Still remember the truth table for D flip flop?

D CLK Q Q’_________________
1 1 0 SET (stores a 1)
0 01 RESET (stores a 0)
 The flip-flop as a storage element

When a 1 is on D, Q When a 0 is on D, Q
becomes a 1 at becomes a 0 at
triggering edge of CLK triggering edge of CLK
or remains a 1 if already or remains a 0 if already
in the SET state in the RESET state
 Type of register

i. Serial In / Serial Out Shift Registers (SISO)

ii. Serial In /Parallel Out Shift Registers (SIPO)
iii. Parallel In / Serial Out Shift Registers (PISO)
iv. Parallel In / Parallel Out Shift Registers
(PIPO)
Basic data movement in shift
registers
 Serial-In, Serial-Out Shift Registers
● Serial data is transferred into a register. i.e one bit at a
time
● New bit is clocked into the first flip-flop at each clock
pulse
● Previous bit is transferred to the next FF
● The bit on the last flip-flop is shifted out
Serial In, Serial Out Shift Register (SISO)

FF0 FF1 FF2 FF3

Clear 0 0 0 0
1010 0 0 0 0
101 0 0 0 0 0
10 1 0 0 0 00
1 0 1 0 0 000
Clear 1 0 1 0 0000
Serial-in ,Serial-out with JK Flip-
flop
Serial In, Parallel Out Shift register (SIPO)

● Data bits entered serially (right-most bit first)

● Difference from SISO is the way data bits are taken
out of the register – in parallel.
● Output of each stage is available
 Parallel-In, Serial-Out Shift Registers
● Data entered simultaneously into registers on parallel
lines.
● Data are transferred out serially. i.e one bit at a time
● A signal shift/(LOAD) allows to enter data in parallel form
and shifted out serially.
 4-bit parallel in/serial out shift register (PISO)

When signal = 1,
● SHIFT

When signal = 0,
LOAD
 4-bit parallel in/serial out shift register (PISO)

When signal = 0,
● LOAD

G1 – G3
enabled
 4-bit parallel in/serial out shift register (PISO)

When signal = 1,
● SHIFT

G4 – G6
enabled
Example : Show the data input waveform for 4-bit register with parallel input
and clock shift/load waveform…4-bit parallel in/serial out shift register (PISO)
Parallel In, Parallel Out Shift Register (PIPO)

● Immediately following simultaneous entry of all data bits,

it appear on parallel output.
 Counters
●A counter is a set of flip-flops(FFs) whose
states change in response to pulses applied at
the input to the counter.
●A counter is used for counting the number of
clock pulses.
●Its output is normally used for generating
binary count sequence
●Count may be binary UP or binary down
●An n bit counter needs n flip-flops
n
●An n bit counter has atmost 2 states.
●A Binary counter counts the sequence in binary
UP or DOWN.
 Types of Counters
Asynchronous counters (ripple counters or
serial counters)

●It is the simplest type and easy to design

●In this type the FF’s doesn’t change the
states exactly the same time
●Output of one FF is used as the clock for
next FF
Synchronous counters (parallel
counters)

●All FFs are working with same clock

pulse.
●Faster than asynchronous counter
 Asynchronous Counters Synchronous Counters
In this type of counter FFs are In this type of counter there is no
connected in such a way that the connection between the output of
output of first FF drives the clock for the first FF and clock input of the
the second FF, the output of the next FF and so on.
second, the clock of the third and so
on.
All the FFs are not clocked All the FFs are clocked
simultaneously. simultaneously
Design and implementation is very Design and Implementation
simple even for more number of becomes tedious and complex as
states. the number of states increases
Main drawback of these counters is Since clock is applied to all the FFs
their low speed as the clock is simultaneously the total
propagated through a number of propagation delay is equal to the
FFs before it reaches the last FF. propagation delay of only one FF.
Hence they are faster.
 Modulus of a counter

● It is the total number of states possible for a

counter
● Eg: a mod 8 counter has 8 different states
● A mod n counter has n different states.

● With an n bit counter we can design at most a

n
mod 2 counter
 Asynchronous Counters
General design

● All flip flops are connected in toggle mode.

● Output of one FF is the clock for next FF.
● Input clock is given to first flip-flop.
● Output are taken from all flip-flops.
● MSB is from last FF and LSB is from first FF
● An n bit counter needs n flip-flops.
 Asynchronous Counters

For binary UP counter:

a) Positive edge triggered FF: connect Q’ of one FF
as the clock for next FF
b) Negative edge triggered : connect Q of one FF as
the clock for next FF
For binary Down counter:
c) Positive edge triggered FF: connect Q of one FF
as the clock for next FF
d) Negative edge triggered : connect Q’ of one FF
as the clock for next FF
(Negative 2- bit asynchronous/ ripple counter
edge
triggered)

Timing
Diagram
 Working
● The counter is initially reset to 00

● When the first clock pulse is applied, FF1 toggles

and Q1 goes high(output is 01)

● At the next clock FF1 toggles and clock of FF2 is

activated(output 10)

● At the next clock FF1 toggles and Q1 changes

from 0 to 1 (output is 11)
2-bit ripple up counter using T FF
 3-bit up counter

Counter Q2 Q1 Q0 Counter Q2 Q1 Q0
State State
0 0 0 0 4 1 0 0
1 0 0 1 5 1 0 1
2 0 1 0 6 1 1 0
3 0 1 1 7 1 1 1
2 bit down counter
 Working
● The counter is initially reset to 00

● When the first clock pulse is applied FF1 toggles and

Q1 goes high and Q’ goes to low , so FF2 toggles
(output is 11)

● At the next clock FF1 toggles and clock does not

affect FF2 (output 10)

● At the next clock FF1 toggles and Q1’ changes from 0

to 1 (output is 01)
 Mod-N Asynchronous Counters
● Modulus Counters, or simply MOD counters, are defined
based on the number of states that the counter will
sequence through before returning back to its original
value.

● For example, a 2-bit counter that counts from 002 to 112 in

binary, that is 0 to 3 in decimal, has a modulus value of 4
( 00 ! 1 ! 10 ! 11, and return back to 00 ) so would
therefore be called a modulo-4, or mod-4, counter.
 Mod 10 Asynchronous Counter
● Such counters are generally referred to as Decade Counters.
● A decade counter requires resetting to zero when the output count
reaches the decimal value of 10, ie. when output = 1010 and to do
this we need to feed this condition back to the reset input.
 Decade Counter Truth Table
Clock Output bit Pattern Decimal
Count QD QC QB QA Value

1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 Counter Resets its Outputs back to Zero
Logic Diagram of a Mod-10 Counter
 MOD-6 Asynchronous Up
Counter
● MOD 6 asynchronous counter will require 3 flip
flops and will count from 000 to 101

● Once the Counter reaches 101, next positive edge

of the clock will make all three inputs of NAND
gate as 1 and will set its output to 0 which is
connected to CLR of all the flip flops thereby
forcing all the flip flops to reset to 0. With the
result counter is reset to 000.
 Shift Register Counter (Ring Counter)

● Shift register counter is basically a shift register with

serial output connect back to serial input to produce
sequences. (That is, A shift register with feed back)
● Have 2 types :-
(i) Johnson Counter = complement of output (Q’) of
st
last FF is connected back to D input of 1 FF.
(inverse feed back)
(ii) Ring Counter = utilize one FF for each state in it
sequence. Q Output of last FF is connected back to
st
D input of 1 FF. (direct feedback)
 Johnson Counter / Shift counter / Twisted
Ring Counter

● A shift register in standard SISO with a feedback.

● The Q output of each stage is connected to the D
input of the next stage.
● Connect Q’ of last FF to the D input of first FF.
● Take output from all FFs.
Construct a 3 bit Johnson counter
Johnson Counter or shift counter

Truth table for a 3 bit Johnson counter

Binary Equivalent
Q2 Q1 Q0 State
Count
0 0 0 1 0
0 0 1 2 1
0 1 1 3 3
1 1 1 4 7
1 1 0 5 6
1 0 0 6 4
0 0 0 1 0
0 0 1 2 1
Johnson Counter or shift counter
Working of 3 bit Johnson

● Assume that initially all flip-flops are in reset state. So

Q2,Q1,Q0 = 000
● Since Q2’ connected to D0, after first clock pulse Q0
goes to 1. So new output will be 001.
● For next clock Q0 and Q1 goes to 1 and output
becomes 011.
● for third clock all output goes to high and it is 111
 Johnson Counter or shift counter

Now what happens for fourth clock

th
● Q2’ is now 0 and it is given to D0, so after 4 clock
this 0 will comes at Q2’ resulting an output of 110
th th
● Then for 5 clock output is 001 and for 6 clock it is
100.
th
● For 7 clock onwards this sequence repeats
● That is it has the following sequence of outputs
000,001,011,111,110,100,000….
Johnson Counter or shift counter

General behaviour of Johnson counter

● N bit Johnson counter needs n FF
● Reverse feedback is given
● It has 2xN states.
● It repeats the sequence after 2xN clocks
Example : 4 bit-bit Johnson counters )
Example : Five-bit Johnson counters (also
called switched tail counter or twisted tail
counter)

Construct a 3 bit shift counter using the above figure

 Ring Counter or circulating register

Connection
● Connect a shift register in standard SISO format.
● Connect Q of last FF to the D input of first FF. (that is
give positive feedback)
● Take output from all FFs.
3 – bit ring counter
3 bit Ring Counter – State Diagram
RING Counter

Truth table for a 3 bit ring counter: assume that initial

condition is 001
Q2 Q1 Q0 State Binary Equivalent Count

0 0 1 1 1

0 1 0 2 2

1 0 0 3 4

0 0 1 1 1

0 1 0 2 2

1 0 0 3 4
Ring Counter or circulating register

Working
● Assume that initially Q2 and Q1 are 0 and Q0 is 1.
● This 1 will shift to right for each clock pulse resulting
the 010. for the next clock output is 100.
● For the third clock it is again 001. and the sequence
repeats.
Ring Counter

General behaviour of ring counter

● N bit ring counter needs N FF
● Positive feedback is given
● It has N states.
● It repeats the sequence after N clocks
● The initial status is circulated.
● If all output is zero initially. Then the outputs remains
zeros forever.
● And if all are ones initially, then the output remains 1
forever.
Example : 4 bit Ring Counter
4 - Bit Ring Counter – State
Diagram
Synchronous
Counters
 Design of Counters

1. Determine the number of FFs required

2. Draw the State Diagram
3. Select the type of FF and draw Excitation Table
4. Obtain the Minimal Expression
No of FFs
n
● N <=2
● Where N is the number of States

State Diagram
● A counter is first described by a state diagram, which is shows the
sequence of states through which the counter advances when it is
clocked
T flip-flop Excitation Table

States Input
Present Next T
0 0 0
0 1 1
1 0 1
1 1 0
JK flip-flop
JK flip-flop
("X" is "don't care")

States Inputs
Present Next J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
 Synchronous Counters
● In Synchronous Counter, the external clock signal
is connected to the clock input of EVERY individual
flip-flop within the counter so that all of the flip-
flops are clocked together simultaneously (in
parallel) at the same time giving a fixed time
relationship.
● In other words, changes in the output occur in
“synchronisation” with the clock signal.
● The result of this synchronization is that all the
individual output bits changing state at exactly the
same time in response to the common clock
signal with no ripple effect and therefore, no
propagation delay.
 3 bit Up counter
● A 3 bit up counter requires 3 flip flops.
● The counting sequence is 000, 001, 010, 011, 100, 101, 110, 111

3 bit Up counter – State Diagram

 CIRCUIT EXCITATION TABLE
PRESENT STATE NEXT STATE T3 T2 T1

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
 Simplified Expression from Truth Table
K-MAP FOR T1

K-MAP FOR T2
 Simplified Expression from Truth Table
K-MAP FOR T3
LOGIC DIAGRAM
4 BIT UP COUNTER USING JKFF
 Present State Next State

Q4 Q3 Q2 Q1 Q4 Q3 Q2 Q1 J4 K4 J3 K3 J2 K2 J1 K1

0 0 0 0 0 0 0 0 1 0 x o x 0 x 1 x
1 0 0 0 1 0 0 1 0 0 x 0 x 1 x x 1
2 0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
3 0 0 1 1 0 1 0 0 0 x 1 x x 1 x 1
4 0 1 0 0 0 1 0 1 0 x x 0 0 x 1 x
5 0 1 0 1 0 1 1 0 0 x x 0 1 x x 1
6 0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x
7 0 1 1 1 1 0 0 0 1 x x 1 x 1 x 1
8 1 0 0 0 1 0 0 1 x 0 o x 0 x 1 x
9 1 0 0 1 1 0 1 0 x 0 o x 1 x x 1
10 1 0 1 0 1 0 1 1 x 0 o x x 0 1 x
11 1 0 1 1 1 1 0 0 x 0 1 x x 1 x 1
12 1 1 0 0 1 1 0 1 x 0 x 0 0 x 1 x
13 1 1 0 1 1 1 1 0 x 0 x 0 1 x x 1
14 1 1 1 0 1 1 1 1 x 0 x 0 x 0 1 x
15 1 1 1 1 0 0 0 0 x 1 x 1 x 1 x 1
 MOD 6 Counter

● In a mod-6 counter you are using a 3-bit counter that actually has 8
states. However, when the counter reaches the seventh state (Q2 =
1, Q1 = 1, Q0 = 0), you force the counter to return to the state (Q2 =
0, Q1 = 0, Q0 = 0)...
● For this you use an NAND gate, whose output is connected with the
CLEAR inputs of the flip-flops.
Mod 6 Counter – State Diagram
 MOD 6 COUNTER
CIRCUIT EXCITATION TABLE
PRESENT STATE NEXT STATE T3 T2 T1

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 0 0 0 1 0 1
1 1 0 x x x x x x
1 1 1 x x x x x x
 Simplified Expression from Truth Table
K-MAP FOR T1

K-MAP FOR T2
 Simplified Expression from Truth Table
K-MAP FOR T3
3 bit down counter
3 bit up down counter