RISC-V Instruction Set

Architecture (ISA)

Introduction
Machine Instruction Characteristics
Types of Operands
Addressing Modes
Instruction Formats
Program execution
Summary
Instruction Set Architecture
(ISA)

Introduction ❑ Overview
Machine Instruction Characteristics
❑ Hierarchy of Computer Languages
Types of Operands ❑ General Concepts:
Addressing Modes RISC-V Processor Architecture
Instruction Formats
Program execution
Summary
 Overview

computer
programmer

assembly language aware of the register and memory

machine language structure, the types of data
register
ALU cache

computer
designer

3
 Hierarchy of Computer Languages

• A programming
language that uses
symbolic names to
represent operations, • Instructions consist
registers and of 0’s and 1’s.
Microprogram control
memory locations. • Directly executed by
• Readability hardware

4
 Compiler and Assembler HLL
Faster, easier, portable

Assembly
Accessible to system hardware.
Efficiency: control over hardware,
more compact coding
Learn how to develop compiler.
Learn how to design an ISA.

Compilers translate high-level programs to Assemblers translate

machine code: assembly to machine
→ either directly, or Indirectly via an code.
assembler. 5
 General Concepts:
RISC-V Processor Architecture

◼ Developed by Krste Asanovic, David Patterson and colleagues at

UC Berkeley in 2010
◼ First widely accepted open-source computer architecture
◼ Underlying design principles:
• Consistent instruction format
Simplicity favors • Same number of operands (two sources and
one destination)
regularity • Easier to encode and handle in hardware

Make the • simple, commonly used instructions

• decode and execute instructions -simple, small,
common case and fast
• complex instructions (that are less common)
fast performed using multiple simple instructions
6
 5-Stage RISC-V – basic components

clock

ALU

Register/Memory

control
Register file

8
5-Stage RISC-V – instruction execution cycle

Fetch Decode Execute Memory Writeback

(F) (D) (E) (M) (WB)
Instruction Set Architecture
(ISA)

Introduction
Machine Instruction ❑ Elements of a Machine
Characteristics Instruction
Types of Operands
Addressing Modes ❑ Instruction Representation
Instruction Formats ❑ Instruction Types
Program Execution
❑ Number of Addresses
Summary
❑ Instruction Set Design
 Elements of an Instruction

Elements Description
Operation code o Specifies the operation to be performed a
binary code (e.g., lw, sw, add, sub).
(Opcode)
Source operand o The operation may involve one or more
reference source operands, that is, operands that are
inputs for the operation.
Result operand o The operation may produce a result.
reference
(Destination).
Next instruction o This tells the processor where to fetch the
reference next instruction after the execution of this
instruction is completed. Invisible
11
+ Example: Elements of an instruction

Source Operand

Destination
Operand

Opcode
• 32-bit addresses
• indicate the relative byte
distance of each statement
from the beginning of the
program’s code area
• assembly language instructions, each 4
bytes long
◼ Generally, Source and Destination operands can be in one
of four areas:

o Main or virtual memory :

Memory address for both must be supplied.
o Processor (CPU) registers : One or more registers that can
be referenced by instructions.
o Immediate : The value of the operand is contained in the
field in the instruction executed.
o I/O device – Instruction specifies the I/O module and device
for the operation

15
 Operand: From Operand: Memory
I/O
Example 2:
Operand: Register Operand:
Immediate value

Next instruction is
where ELSE is located,
offset 12 from the line

Current Ins. : 0020

Next Ins. : 002c 16
 It is difficult for the
programmer to deal
with binary
representations of
machine instructions.

◼ Thus, it has become common

practice to use a symbolic
representation of machine
instructions.

◼ Opcodes are represented by

1100011 abbreviations, called
mnemonics, that indicate the
1100011
1100011
1100011
1100011 operation.
1100011
17
 18
+From Assembly to Machine Instruction
◼ Translating the language:

English: Total is assigned the sum of Total and stuff.

High-Level Language: Total = Total + stuff

A statement in a high-level language is translated
typically into several machine-level instructions

lw x20,Total 10000a17
lw x21, stuff 000a2a03
add x20, x20, x21 10000a97
la x18, Total ffcaaa83
sw x20,0(x18) ……

Assembly Language: Machine Code:

◼ Example:
Instruction type Machine code Symbolic representation description
(hex)
R-type 02832283 lw x5, 40(x6) Transfer content of memory location at x6+40 to
register x5.

What the processor What the

(CPU) see. programmer see.
◼ During execution cycles:
o an instruction is read
into a Pipeline
Register (IR) in the
processor.
o The processor
extract the data from
the various
instruction fields to
perform the required
operation.

19
 Instruction format

◼ An instruction format defines the layout of the bits of an

instruction, in terms of its constituent fields.
◼ An instruction format must include an opcode and, implicitly or
explicitly, zero or more operands.
◼ The format must, implicitly or explicitly, indicate the addressing
mode for each operand.
◼ For most instruction sets, more than one instruction format is
used.

William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.469. 20
 Machine Instruction Representation

◼ Each instruction is represented by a sequence of bits that

divided into fields, corresponding to the constituent elements of
the instruction.

R
I
U
S
SB
UJ

21
 Instruction Types

Instruction
Types

Data Data Data Upper Control

Processing processing Storage Immediate
/storage SB-type
R-type I-type S-type UI-type UJ-type

o Arithmetic and o Load o Store o Conditional

logic o Immediate jump.
instructions. arithmetic o Unconditional
jump

Figure: instruction types.

22
25
 Branch (SB-type) Instructions

Imm[10:0] Imm[4:1]

(UJ-type)
 27
+ Example 1: Deriving instruction
machine code from assembly code
line Assembly code Machine code Machine
(bin) code (hex)
58: myMult: …

… ……..

cc: lw x10 12(x2)

d0: lw x11 0(x2)

d4: jal x1 myMult

d8: sw x10 24(x2)

address memory address memory

cc d4
cd d5
ce d6
cf d7
d0 d8
d1 d9
d2 da
d3 db
 Number of Addresses

◼ One of the traditional ways in describing processor architecture

is using the number of addresses contained in each instruction .

What is the maximum

number of addresses one
might need in an instruction?

◼ In most architectures, most instructions have one, two, or three

operand addresses.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.432. 28
 Example: Program to execute PUSH C
PUSH D
PUSH E
4 instructions MUL
ADD
PUSH B
6 instructions PUSH A
SUB
10 instructions
DIV
POP Y
(d) No-address
instruction

8 instructions

William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.417. 29
How Many Addresses?

◼ Number of addresses per instruction is a basic design decision.

◼ More addresses: ◼ Fewer addresses:

◼ More complex ◼ Less complex (powerful?)

(powerful?) instructions. instructions.
◼ Fewer instructions per ◼ More instructions per
program. program.
◼ More registers: ◼ Faster fetch/execution of
→ Inter-register operations instructions.
are quicker.

30
◼ Four common instruction formats:

(a) Zero-address instruction.

(b) One-address instruction

(c) Two-address instruction.

(d) Three-address instruction.

31
 Instruction Set Design
◼ The most important of these fundamental design issues include
the following: o How many operations?
o What can they do?
Operation o How complex are they?
o The mode(s)
by which the
Addressing Data Types
address of an
operand is
o The various
specified.
types of data.

Instruction
Registers
Formats

o Number of CPU registers available. o Length of opcode field.

o Which operations can be performed o Number of addresses.
on which registers?
32
Instruction Set Architecture
(ISA)

Introduction
Machine Instruction
Characteristics
Data types
Addressing Modes
Instruction Formats
Program Execution
Summary
Overview

34
35
Example : various lengths of data.

◼ The integers may be 8, 16, 32, or 64 bits long.

Byte lb x10, 0(x7)

lh x10, 0(x7)
Half-word

lw x10, 0(x7)
Word

Double-word ld x10, 0(x7)

36
Example 2: various length of data

register register

37
Example: data length for floating point.

◼ The floating-point type actually refers to a set of types that are

used by the floating-point unit and operated on by floating-point
instructions → IEEE 754 standard.

38
Instruction Set Architecture
(ISA)

Introduction ❑ Overview
Machine Instruction ❑ Immediate Addressing
Characteristics
❑ Direct Addressing
Types of Operands
❑ Indirect Addressing
Addressing Modes
Instruction Formats ❑ Register Addressing
Program execution ❑ Register Indirect Addressing
Summary ❑ Displacement Addressing
 Overview

◼ Two issues arise in specifying the operands addresses and

operations of instructions:

How the address of an How the bits of an

operand is specified? instruction are organized?

◼ A variety of addressing techniques has been employed to be

able to reference a large range of locations in main memory or,
for some systems, virtual memory.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.474. 40
 Notations: A = contents
of an address
field in
instruction.

R = contents
of an address
field in
instruction that
refers to a
register.

EA = actual
(effective)
address of the
location
containing the
referenced
operand.

(X) = contents
of memory
Figure: Addressing modes. location X or
register X.
William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.458. 41
 operand

(a) Immediate Addressing

◼ The simplest form of

addressing, in which the
operand value is present in the
instruction.
◼ Can defines and uses constant
111111111111 00110 000 00101 0010011 or set initial values of variables.
f f f 3 0 2 9 3

The size of the number is

◼ Saving one restricted to the size of the
memory/register address field.
William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.476. 42
 (b) Direct Addressing

◼ The address field contains the

Effective Address (EA) of the
x86 operand.

Requires only one It provides only a limited

memory reference and no address space.
special calculation.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.476. 43
 (c) Indirect Addressing
Look in A, find
address (A), and look
there for operand.
◼ Solution for the limitation of
the address range in direct
addressing → to have the
address field address of a
word in memory, full-length
address of the operand.
Not in RISC-V, not in x86
Three or more memory
references could be required
No particular advantage.
to fetch an operand; slower.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.477. 44
 (d) Register Addressing

◼ Similar to direct addressing,

except the address field refers to
a register rather than a main
memory address.
◼ The programmer need to decide
which values should remain in
registers and which should be
stored in main memory.

No time consuming It has limited number of

memory references needed registers → provides a
→ faster. limited address space.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.476. 45
 (e) Register Indirect Addressing

◼ Similar to indirect addressing.

◼ The advantages and

x86 limitations of register indirect
mov cx,[edi] addressing are basically the
same as for indirect
addressing.

Register indirect addressing uses one less memory

reference than indirect addressing.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.478. 46
 (f) Displacement Addressing

◼ A very powerful mode of

addressing combines the
capabilities of direct
addressing and register
3 common displacement indirect addressing.
addressing techniques:
◼ Address field hold two values:
Relative addressing o A = base value
o R = register that holds
Base-Register addressing
displacement
Indexed addressing (or vice versa)

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.478. 47
(f.1) Relative Addressing
◼ Also called PC-relative addressing, the implicitly referenced register is
the Program Counter (PC).
R = PC
EA = A + (PC)
◼ The next instruction address (shown in PC) is added to the address
field to produce the EA.

48
 Offset = Target – Source
= ELSE – PC
Displacement Addressing. = 2c – 20
= c (hex) or 12(dec)

(1) Relative addressing

+(ve) for jumping
forward.
–(ve) for jumping
backwards

PC=20
Need to go to
ELSE which i
in 0000002c

49
(f.2) Base-Register Addressing
EA = A + R

o A holds displacement.
o R holds pointer to base address.

Load instruction Store instruction

EA = sign(imm11:0) + rs1
50
Displacement Addressing.

(2) Base-register addressing

register content
Base-register s3
displacement
addressing
s4
t0
base
t1
t2
a0
a7
Assume data segment
 (f.3) Indexed Addressing

EA = A + R

o A = base
o R = displacement
o Good for accessing arrays

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.479. 52
 .data
X86 array1 byte 10h,11h,12h,13h
Displacement Addressing. array2 word 123h,234h,345h,456h
array3 dword 123456h, 23456789h

(3) Indexed addressing .code

main PROC
mov eax,0 Base
mov ecx,4

L1:
mov bx, array2[eax]
add eax,2
call dumpregs
LOOP L1
exit Displacement
main ENDP

53
 Table: Basic addressing modes.

William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.459. 54
Instruction Set Architecture
(ISA)

Introduction
Machine Instruction
Characteristics
Types of Operands
Addressing Modes ❑ Simple statement
Program execution ❑ Conditional statement
X86 Instruction Formats ❑ Calling a procedure
Summary
❑ Calling a nested procedure
Program execution
(a simple statement)
◼ Example 1:

f= (g+h) – (i+j)

56
 memory

Program execution Address content

before after

0x 1000 0000 21 1e
(a simple statement) 0x 1000 0001 00 00
0x 1000 0002 00 00
◼ Example 2: 0x 1000 0003 00 00
0x 1000 0004 06 06
g= h + A[8] 0x 1000 0005 00 00
0x 1000 0006 00 00
0x 1000 0007 00 00
0x 1000 0008 10 10
0x 1000 0009 00 00
0x1000 000A 00 00
0x 1000 000B 00 00
0x1000 000C 11 11
0x1000 000D 00 00
0x1000 000E 00 00
0x 1000 000F 00 00
0x 1000 0010 12 12
0x 1000 0011 00 00
0x 1000 0012 00 00
0x 1000 0013 00 00 57
Program execution
(a conditional statement)
◼ Example 3:

if(i==j)

f=g+h;

else

f=g-h;

58
Program execution
(calling a procedure)

1. Put parameters in argument registers;

2. Transfer control to the procedure;

3. Acquire the registers required by the procedure;

4. Perform the procedure task;

5. Put the result in return value register;

6. Return the control to the caller.

 Program execution
(calling a procedure)

1. Put parameters in stack

argument registers;
sp 7fff_fff0
7fff_ffef
7fff_ffee
7fff_ffed
7fff_ffec

a0 0000 0004
a1 0000 0003
s0 Caller’s fp
sp 7fff fff0
7fff_ffd1
7fff_ffd0
60
 Program execution
(calling a procedure)

2. Transfer control to the stack

procedure;
- Update pc to mult.
0x30: - Update ra. sp 7fff_fff0
7fff_ffef
7fff_ffee

0x50:
7fff_ffed
7fff_ffec
a0 0000 0004
a1 0000 0003
s0 Caller’s fp
sp 7fff fff0
ra 0000 0030 7fff_ffd1
7fff_ffd0
61
pc= 0000 0050
 Program execution
(calling a procedure)
3. Acquire the registers
required by the procedure;
stack
- Allocate stack frame
- Push in the registers
sp 7fff_fff0
7fff_ffef
7fff_ffee

32 bytes frame (mult)

7fff_ffed
7fff_ffec

a0 0000 0004
a1 0000 0003
s0 Caller’s fp
sp 7fff ffd0
ra 0000 0030
7fff_ffd1
sp 7fff_ffd0
pc= 0000 0050
 Program execution
(calling a procedure)
3. Acquire the registers
required by the procedure;
stack
- Allocate stack frame
- Push in the registers
sp 7fff_fff0
7fff_ffef
7fff_ffee
00000030

32 bytes frame (mult)

7fff_ffed
7fff_ffec
a0 0000 0004
a1 0000 0003
ra 0000 0030
sp 7fff ffd0
s0 Caller’s fp 7fff_ffd1
sp 7fff_ffd0
 Program execution
(calling a procedure)
3. Acquire the registers
required by the procedure;
- Allocate stack frame
- Push in the registers

sp 7fff_fff0
7fff_ffef
7fff_ffee
00000030

32 bytes frame (mult)

7fff_ffed
7fff_ffec

Caller’s
a0 0000 0004
fp
a1 0000 0003
ra 0000 0030 7fff_ffe8
sp 7fff ffd0
s0 Caller’s fp

sp 7fff_ffd0
 Program execution
(calling a procedure)
3. Acquire the registers
required by the procedure;
- Allocate stack frame
- Push in the registers

fp sp 7fff_fff0
7fff_ffef
7fff_ffee
00000030

32 bytes frame (mult)

7fff_ffed
7fff_ffec

Caller’s
a0 0000 0004
fp
a1 0000 0003
ra 0000 0030 7fff_ffe8
sp 7fff ffd0
s0/fp 7fff fff0

sp 7fff_ffd0
 3. Acquire the registers
fp sp
Program execution
7fff_fff0
required by the procedure;
7fff_ffef
- Allocate stack frame
7fff_ffee
(calling a procedure) 00000030
- Push in the registers
7fff_ffed
7fff_ffec

Caller’s fp
7fff_ffe8

32 bytes frame (mult)

00000004
7fff_ffe4

00000003
7fff_ffe0

a0 0000 0004
a1 0000 0003
ra 0000 0030
sp 7fff ffd0
s0/fp 7fff fff0

sp 7fff_ffd0
 fp sp
Program execution
7fff_fff0
7fff_ffef
7fff_ffee
(calling a procedure) 7fff_ffed
7fff_ffec
00000030

Caller’s fp

32 bytes frame (mult)

7fff_ffe8

00000004
7fff_ffe4

00000003
7fff_ffe0

a0 0000 000c
a1 0000 0003
ra 0000 0030 4. Perform the
sp 7fff ffd0 procedure task
s0/fp 7fff fff0

sp 7fff_ffd0
 fp sp
Program execution
7fff_fff0
7fff_ffef
7fff_ffee
(calling a procedure) 7fff_ffed
7fff_ffec
00000030

Caller’s fp

32 bytes frame (mult)

7fff_ffe8

00000004
7fff_ffe4

00000003
7fff_ffe0

a0 0000 000c
a1 0000 0003
ra 0000 0030
sp 7fff ffd0
s0/fp 7fff fff0

5. Put the result in

sp 7fff_ffd0
return value register;
 fp sp
Program execution
7fff_fff0
7fff_ffef
7fff_ffee
(calling a procedure) 7fff_ffed
7fff_ffec
00000030

Caller’s fp
7fff_ffe8

00000004
7fff_ffe4

00000003
7fff_ffe0

a0 0000 000c
a1 0000 0003
6. Return control
ra 0000 0030
-retrieve ra, s0/fp
sp 7fff ffd0 - Pop / free the stack
s0/fp Caller’s fp frame
sp 7fff_ffd0
Program execution
(calling a nested procedure)
Program execution
(calling a nested procedure) Executing main
fp 7fff_fff0
Return address, ra

32-byte
Caller’s frame pointer

Argument registers

………
7fff_ffd0

0x00c0:
0x0030:
 Program execution Executing addmult
(calling a nested procedure) 7fff_fff0
Return address, ra

32-byte
Caller’s frame pointer

Argument registers

………
fp 7fff_ffd0
Return address, ra

Caller’s frame pointer

32-byte
Argument registers

………
7fff_ffb0

0x00c0:
0x0030:
 Program execution Executing add
(calling a nested
7fff_fff0
procedure)
Return address, ra

32-byte
Caller’s frame pointer

Argument registers

………
7fff_ffd0
Return address, ra

Caller’s frame pointer

32-byte
Argument registers

………
fp 7fff_ffb0
Return address, ra

32-byte
Caller’s frame pointer

0x0030: Argument registers

………
7fff_fe90
 Program execution Return to addmult
(calling a nested procedure) 7fff_fff0
Return address, ra

32-byte
Caller’s frame pointer

Argument registers

………
fp 7fff_ffd0
Return address, ra

Caller’s frame pointer

32-byte
Argument registers

………
7fff_ffb0

0x00c0:
0x0030:
 Program execution
(calling a nested procedure)
fp
Return to main
7fff_fff0
Return address, ra

32-byte
Caller’s frame pointer

Argument registers

………
7fff_ffd0

0x00c0:
0x0030:
Activity: https://ripes.me/ (RISC-V online assembler)
Instruction Set Architecture
(ISA)

Introduction
Machine Instruction
Characteristics
Types of Operands
Addressing Modes
X86 Instruction Formats
Summary
x86 Instruction Format
+ x86 Instruction Format
+ x86 Instruction Format
+ x86 Instruction Format
+ x86 Instruction Format
+ x86 Instruction Format
+ x86 Instruction Format
+x86: add instruction
+x86: add instruction
 Instruction Length

◼ This decision affects, and is affected by:

❑ memory size,
❑ memory organization,
❑ bus structure,
❑ processor complexity, and
❑ processor speed.

◼ Trade off between powerful instruction repertoire and saving

space.

◼ Other issues: Instruction length equal or multiple to memory

transfer length (bus system)?
William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.469. 87
 Variable-Length Instructions

◼ Designer may choose instead to provide a variety of instruction

formats of different lengths.
◼ This tactic makes it easy to provide a large repertoire of
opcodes, with different opcode lengths.
◼ Addressing can be more flexible, with various combinations of
register and memory references plus addressing modes.
◼ With variable-length instructions, these many variations can be
provided efficiently and compactly

William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.473. 88
 4.6 Summary

◼ This chapter discussed on what an instruction set does by

examining the types of operands and operations that may be
specified by machine instructions.

◼ Described the various types of addressing modes common in

instruction sets.

◼ Present an overview of essential characteristics of machine

instructions.

◼ Summarize the issues and trade-offs involved in designing an

instruction format.

William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.413, 457. 89