Lecture 12 Circuits Family - Part 1
Lecture 12 Circuits Family - Part 1
– VLSI DESIGN
Dr. Touhidur Rahman
Professor,
Dept. of EEE, Brac University
[email protected]
Introduction
Ids 1.2
P = 24
Vout Vout 0.9
16/2 0.6
Vin P = 14
0.3
P=4
0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin
Pseudo-nMOS Power
en
Y
A B C
Dynamic Logic
■ Dynamic gates uses a clocked pMOS pullup
■ Two modes: precharge and evaluate
2 2/3 1
A Y Y Y
1 A 4/3 A 1
Y
The Foot
precharge transistor Y Y
Y inputs inputs
f f
A
foot
footed unfooted
Monotonicity
violates monotonicity
during evaluation
A
A=1