UNIT-3

Logic Design With Behavioral

Models of Combinational And
Sequential Logic
 Contents
• Behavioral models of multiplexers, Encoders and decoders
• Data flow model of a LFSR machines with multi cycle operations
• Algorithmic state machine charts for behavioral modelling
• ASMD charts
• Behavioral models of counters, Shift registers and register files
• Switch de-bounce
• Meta stability and
• Synchronizers for asynchronous signals
 Behavioral models of multiplexers,
Encoders and decoders

•Here, present the Verilog models to illustrate alternate level

sensitive behavioral descriptions, and the results of
synthesizing them into ASIC library.
 Behavioral models of multiplexers

• A Four channel, 32-bit

Multiplexer
Verilog Code
Alternate model for Multiplexer using if-else
 Another alternate:
Nested conditional assignments
8x3 Encoder
Verilog code for 8x3 Encoder
Alternate description
Alternate model using if-else
Alternate description
Synthesized Circuit for 8x3 Priority Encoder
3x8 Decoder
 Alternate description
• always @ (code)
Synthesized circuit of 3x8 Decoder
 Seven Segment Display
• Accepts 4-bit words representing BCD digits
and displays their decimal value.

• The display has active-low illumination

outputs, and can be implemented with
combinational logic.
Verilog code
 Dataflow models of a Linear Feedback Shift
Register (LFSR)
• LFSRs are commonly used in data compression circuits implementing
a signature analysis technique called Cyclic Redundancy Check (CRC).

• Autonomous LFSRs are used in applications requiring pseudo random

binary numbers. (Eg: Random pattern generator)
 Dataflow models of a Linear Feedback Shift
Register (LFSR)
• LFSR with modulo-2 (ex-or) addition
• c1,c2,…., cn are binary tap coefficients
•CN = 1, as Y[N] is directly connected to left most register (flip
flop).

•In general CN-j+1 =1, then the input to stage j is formed as the
ex-or of Y[j-1] and Y[N], for j=2,3,…., N
• Verilog code of
8-Cell autonomous
LFSR
Data movements in LFSR with modulo-2
addition
Algorithm model Verilog code for LFSR
 Alternate loops
• A for loop has the form
for(initial statement; control_expression; index_statement)
statement_for_execution;

• Initial statement - execute once to initialize a register variable (integer or reg)

that controls the loop.
• If control expression is True, the statement for execution will execute.
• After this index statement will execute (to increment a counter)
• Then activity flow will return to beginning of the for statement and check again
• If control expression is False, the loop terminates and activity flow will
proceeds to next statement after statement for execution.
• A for loop is used to assign values to bits within a register after it has
been initialized to x.
 Additional loop constructs in Verilog
For describing repetitive algorithms, the following alternate
loops can be used in Verilog.
•repeat
•while
•forever
repeat loop construct
• A repeat loop is used in the fragment of code below to initialize a
memory array
• Register contents after execution of the for loop
 Majority circuit
• A majority circuit asserts its output if a majority of the bits of an input
word are asserted.
Simulation results for majority circuit
 While loop
•Syntax:
While (expression) statement;

• Eg: The statement below increments a synchronous counter while

enable is asserted.

while(enable)
begin @ (posedge clock)
count <= count + 1;
end
 Machines with multi cycle operations
•Some of the digital machines have repetitive operations
distributed over multiple clock cycles

•This activity can be modeled in Verilog by a synchronous

cyclic behavior
- that has as many nested edge sensitive event control expressions
as are needed to complete the operations.
 Eg: Machine to form the sum of four
successive samples of data path

•Store the samples in registers and then use multiple adders

to form the sum

•Or it could use one adder to accumulate the sum

sequentially.
Verilog code
•A
Synthesized Circuit
for four-sample adder
 Algorithmic State Machine (ASM) Charts for
Behavioral Modeling
• A machine’s activity consists of synchronous sequence of operations
on the registers of its data paths, usually under the direction of a
controlling state machine.
• State Transition Graphs (STG) – indicate the transitions that result
from inputs that are applied when a state machine is in a particular
state
• But, STGs do not directly display the evolution of states under the
application of input data.

• Alternative format for STG : ASM charts

 ASM Charts
• Principle: ASM Charts are an abstraction of the functionality of a
sequential machine, and are a key tool for modeling their behavior.

• Similar to software flow charts, but display the time sequence of

computational activity (eg. Register operations)
- as well as the sequential steps that occur under the influence of machine’s
inputs.

• An ASM chart focuses on the activity of the machine, rather than on

the contents of all the storage elements
• ASM charts can be very helpful in describing the behavior of
sequential machines, and in designing a state machine to control a
datapath.
 Fundamental elements of ASM chart
• A State box
• Decision box
• A Conditional box
 Role of elements in ASM chart
• A State box represents the state of the machine between
synchronizing clock events

• The values of the variables in the decision boxes determine the

possible paths through the block under the action of the inputs.

• Conditional outputs are placed in a conditional box on an ASM chart,

some times annotated with the register operations
• Eg: ASM Chart for a vehicle
speed controller
 ASMD Charts
•State machine usage: To control register operations on a
data path in a sequential machine that has been portioned
into a controller and a data path.

•The controller is generally described by an ASM chart.

•The ASM charts that are modified by annotating each of its

paths to indicate the concurrent register operations that
occur in the associated data path unit, when the state of the
controller makes a transition along the path are called as
ASMD Charts.
 Uses of ASMD charts
•Help to clarify the design of a sequential machine by
separating the design of its data path from the design of the
controller
- while maintaining a clear relationship between the two units.

•Register operations that occur concurrently with state

transitions are annotated on a path of the chart.
 ASMD Chart - Example
• Two stage pipeline register
• a) Pipeline architecture of
2:1 Decimator
• b) ASMD Chart
 Behavioral models of Counters, Shift
Registers and Register files
• A Counter generates a sequence of related binary words

• A Register stores data that can be retrieved and/or overwritten under

the control of a host processor.

• The cells of Shift register exchange contents in a systematic and

synchronous manner.

• Register files are a collection of registers that share the same

synchronizing and control signals.
 Counters
• The counter could be modeled
- By choosing a state consisting of content of the register holding the count
- Or to associate the state with the activity of the machine, which consists of idling,
incrementing, or decrementing.
• Two versions of ASM chart has been shown in next slide (without & with
conditional output boxes).
• The activity of the counter has three states
- Idling (S_idle)
- Incrementing (S_incr) and
- Decrementing (S_decr)
• The asynchronous Active low reset signal, reset drives the state to S_idle
 ASM Chart for up-down counter
• ASM Chart for a behavioral
model of an up-down counter
having synchronous reset

a) without conditional output

boxes, and
b) with conditional output
boxes for register operations
output generated by state
machine
 ASMD chart for a 4-bit binary counter
• a) with asynchronous
active-low reset
• b) synchronous
active-low reset
Verilog code of Counter
Verilog code of Ring Counter
Data movements in a 8-bit ring counter
• Synthesized circuit of ring counter from
Verilog behavioral description
3-bit up-down counter with additional features
(load initial count and enable the counting activity)
 Shift Registers
• A 4-bit Shift register below declares an internal 4-bit register, which
creates data_out by a continuous assignment to the LSB of the
register
- and forms the register contents synchronously from concatenation of the
scalar data_in with the three leftmost bits of the register
Verilog code
4-bit Shift register with reset and parallel
load
Verilog code
 Barrel Shifter
• This type of shifters are used in digital signal processors to avoid
overflow problems
- By scaling the input and output of a data path operation.

• Scaling is accomplished by shifting the bits a word to the left or right

- Shifting a word to the right effectively divides the word by a
power of 2
- and shifting the word to the left multiplies the word by a power
of 2
Verilog code – Barrel Shifter
8-bit Barrel Shifter with registered output

Data movement
• Synthesized circuit
 Universal Shift Register
• It is an important unit of digital machines that employ a bit-slice
architecture, with multiple identical slices of a 4-bit shift register
chained together with additional logic to form a wider and more
versatile data path.
• Its features include
- Synchronous reset
- Parallel inputs
- Parallel outputs
- Bidirectional serial input form either the LSB or MSB
- Bidirectional serial output to either the LSB or MSB
• Four Modes of operation
• A) Serial-in, Serial-out – Unidirectional Shift Register

• B) Parallel –in, Serial-out – Parallel to Serial data converter

• C) Serial-in, Parallel-out – Serial to Parallel data converter

• D) Parallel-in, Parallel-out – combined with shift operations, allows it to

perform any of the operations of less versatile
unidirectional shift registers
4-bit Universal Shift register
Verilog code – Universal Shift Register
Simulation Results
 Register files and Arrays of Registers
(Memories)
• A Register file consists of a small no. of registers and is integrated with
additional logic.
• It supports write and nondestructive read operations
• Usually implemented by D-flip-flops

• Limitation: Register files are not used for mass storage, because they
occupy significantly more silicon area than compiled memory.
A 32-word register file in tandem with an ALU
having 32-bit data path
Verilog code
 Switch debounce, Metastability, and
Synchronizers for asynchronous signals
• A hardware latch can enter the meta stable state if pulse at one of its
inputs is too short, or both inputs asserted simultaneously or within a
small interval each other.
• A transparent latch enter metastable state, if the data are unstable at
edge of the enable input.
• A D-flip flop can enter metastable state, if the data are unstable at
setup interval preceding the clock edge or if the clock pulse is too
narrow.
• A push button input
device with closure
bounce
A NAND latch configuration for eliminating
the effects of switch closure bounce
e
•Example of metastability
 Synchronizers for Asynchronous input
signals
•Circuit, when width of
the asynch input signal
> period of clock
• Circuit, when width of
the asynch input signal
< period of clock
• Waveforms without
Metastability condition
• Waveforms having
Metastability condition