Department of Electronics and Communication

Engineering

Question Bank

191EC721- Embedded and Real Time Systems

Year : IV

Semester : VIII

Prepared by :Mr. D.Ruban Thomas

Mr. S.Prabhu Kumar
Assistant Professor

ECE Department
 Branch : ECE Subject Code : 191EC721

Year / Sem: IV/VII Subject Name: Embedded and Real Time Systems

Question Bank

Unit-I Introduction to Embedded System Design

[CO1.1]Complex systems and microprocessors– [CO1.2]Embedded system design process –Design example:
Model train controller- [CO1.3]Design methodologies- Design flows - Requirement Analysis – Specifications-
System analysis and architecture design – [CO1.4] Quality Assurance techniques - [CO1.5] Designing with
computing platforms – Consumer electronics architecture – [CO1.6]Platform-level performance analysis.

CL
S.No Questions CO
Level
Computer has a built-in system clock that emits millions of regularly spaced electric
pulses per called clock cycles.
1 a) second CO1.1 CL1
b) millisecond
c) microsecond
d) minute
The operation that does not involves clock cycles is
a) Installation of a device
2 b) Execute CO1.1 CL1
c) Fetch
d) Decode
The number of clock cycles per second is referred as
a) Clock speed
3 b) Clock frequency CO1.1 CL1
c) Clock rate
d) Clock timing
CISC stands for
a) Complex Information Sensed CPU
4 b) Complex Instruction Set Computer CO1.1 CL1
c) Complex Intelligence Sensed CPU
d) Complex Instruction Set CPU
Which of the following processor has a fixed length of instructions?
a) CISC
5 b) RISC CO1.1 CL1
c) EPIC
d) Multi-core
A circuitry that processes that responds to and processes the basic instructions that
are required to drive a computer system is _____
6 a) Memory CO1.2 CL1
b) ALU
c) CU
d) Processor
What does API stand for?
7 a) address programming interface CO1.2 CL1
b) application programming interface
 c) accessing peripheral through interface
d) address programming interface
Which activity is concerned with identifying the task at the final embedded systems?
a) high-level transformation
8 b) compilation CO1.2 CL1
c) scheduling
d) task-level concurrency management
In which design activity, the loops are interchangeable?
a) compilation
9 b) scheduling CO1.2 CL1
c) high-level transformation
d) hardware/software partitioning
Which design activity is in charge of mapping operations to hardware?
a) scheduling
10 b) high-level transformation CO1.2 CL1
c) hardware/software partitioning
d) compilation
UML stands for ___.
a. Unified Manipulation Language
11 b. Unified Modeling Language CO1.3 CL1
c. Universal Manageable Language
d. None of the above
___ are typically found during system integration
a. Bugs
12 b. Defects CO1.3 CL1
c. Insects
d. None of the above
In Embedded System Design Process ___ is used to create a more detailed
description of what we want.
a. System integrating CO1.3
13 CL1
b. Architecture
c. Specification
d. Requirements
In UML events, ___ follows the model of a procedure call in a programming
language.
a. Signal event CO1.3
14 CL1
b. Data event
c. Call event
d. Time out event
___ is used for fetching instructions from the memory.
a. Control unit
15 b. Execution unit CO1.3 CL1
c. Memory unit
d. ALU
Degree to which design specifications arefollowed in manufacturing the product
is called
a. Quality Control
16 CO1.4 CL1
b. Quality of conformance
c. Quality Assurance
d. None of the mentioned
Which of the following is not included infailure costs?
a. rework
17 CO1.4 CL1
b.repair
c. failure mode analysis
 d.none of the mentioned
Which requirements are the foundation from which quality is measured?
a) Hardware
18 b) Software CO1.4 CL1
c) Programmers
d) None of the mentioned
Which of the following is not included in External failure costs?
a) testing
19 b) help line support CO1.4 CL1
c) warranty work
d) complaint resolution
Who identifies, documents, and verifies that corrections have been made to the
software?
20 a) Project manager CO1.4 CL1
b) Project team
c) SQA group
d) All of the mentioned
Which of the following is not included in failure costs?
a) rework
21 b) repair CO1.5 CL1
c) failure mode analysis
d) none of the mentioned
A_____ view shows the system hardware and how software components are
distributed across the processors in the system.
22 a) physical CO1.5 CL1
b) logical
c) process
d) all of the mentioned
Which of the following is an architectural conflict?
a) Using large-grain components improves performance but reduces maintainability
b) Introducing redundant data improves availability but makes security more difficult
23 CO1.5 CL1
c) Localizing safety-related features usually means more communication so degraded
performance
d) All of the mentioned
Which of the following designed system factors are optimized or enhanced for an
embedded application?
24 a) Performance CO1.5 CL1
b) Reliability
c) Efficiency
d) All the above
Which of the following is not included in Architectural design decisions?
a) type of application
25 b) distribution of the system CO1.5 CL1
c) architectural styles
d) testing the system
Which of the following allows the reuse of the software and the hardware
components?
26 a) platform based design CO1.6 CL1
b) memory design
c) peripheral design
d) input design
27 Which of the following is the design in which both the hardware and software are CO1.6 CL1
considered during the design?
 a) platform based design
b) memory based design
c) software/hardware codesign
d) peripheral design
What does API stand for?
a) address programming interface
28 b) application programming interface CO1.6 CL1
c) accessing peripheral through interface
d) address programming interface
In which design activity, the loops are interchangeable?
a) compilation
29 b) scheduling CO1.6 CL1
c) high-level transformation
d) hardware/software partitioning
Which of the following is a meet-in-the middle approach?
a) peripheral based design
30 b) platform based design CO1.6 CL1
c) memory based design
d) processor design
Which of the following is approximated during hardware/software partitioning,
during task-level concurrency management?
31 a) scheduling CO1.6 CL1
b) compilation
c) task-level concurrency management
d) high-level transformation
Which design activity is in charge of mapping operations to hardware?
a) scheduling
32 b) high-level transformation CO1.6 CL1
c) hardware/software partitioning
d) compilation

]
 PART – B [4 Marks]

S.No Questions CO CL Level

1 Interpret the importance of DCC in train controller CO1.1 CL2

Analyze the features of SDL Specification language with suitable
2 CO1.1 CL3
diagrams.
Mention the requirements for designing a GPS moving map in embedded
3 CO1.1 CL2
system design process.

List out the challenges of high performance embedded platforms which

4 CO1.1 CL2
act as heterogeneous multiprocessors.

5 Give a thorough explanation of the value of structural description. CO1.2 CL2

Mention the requirements needed to design an embedded system and how

6 CO1.2 CL3
to determine them

Propose a method for understanding the architectural design of a

7 CO1.3 CL3
complex system by using CRC Cards.

Sketch and explain a hierarchical design flow model using hardware

8 CO1.3 CL3
software design system methodology.

Elaborate the important criterions that can be considered for design

9 CO1.4 CL2
reviews in Quality Assurance process
How to design an embedded system employ computing boards should be
10 CO1.5 CL3
explained in detail.

With an example in consumer electronics, explain the embedded system

11 CO1.5 CL3
design with computing platform .

12 Illustrate system level performance analysis with neat diagram. CO1.6 CL3

PART C (12 marks)

S.No Questions CO CL Level

Summarize the different factors involved in embedded system design

1 CO1.1 CL3
process of GPS moving map with necessary illustrations.
Compare the hierarchical and successive refinement model design for
2 CO1.2 CL2
an embedded system with suitable diagrams.
Develop the design methodologies and design flow used in embedded
3 CO1.3 CL4
Systems.
Assuming the design of model train controller, draw a state diagram for
a behavior that sends the command bits on the track. The machine
4 CO1.3 CL2
should generate the address, generate the correct message type, include
the parameters and generate the error correcting code (ECC).
 Illustrate with diagrams the system design methods using water fall,
5 CO1.3 CL2
spiral and successive refinement model.
Justify the need of Quality Assurance techniques in embedded design
6. CO1.4 CL2
and explain.
Elaborate following in detail as per system level design analysis.
CO1.5 CL3
(i) Consumer electronics architecture.
7 CO1.5 CL2
(ii) Platforms and operating systems.
CO1.5 CL2
(iii) Flash file systems.
With necessary diagram explain the need of platform level performance
8 CO1.6 CL2
analysis.
 UNIT II - ARM PROCESSOR AND PERIPHERALS
[CO2.1]ARM Architecture Versions – ARM Architecture – [CO2.2]Instruction Set –[CO2.3] Stacks and
Subroutines – [CO2.4]Features of the LPC 214X Family – [CO2.5]Peripherals – The Timer Unit –
[CO2.6]Pulse Width Modulation Unit – [CO2.7]UART – Block Diagram of ARM9 and [CO2.8]ARM
Cortex M3 MCU.
S.No Questions CO CL Level
ARM stands for
a) Advanced Rate Machines
1 b) Advanced RISC Machines CO2.1 CL1
c) Artificial Running Machines
d) Aviary Running Machines
Princeton architecture is also known as
a) von Neumann architecture
2 b) Harvard CO2.1 CL1
c) RISC
d) CISC
The main importance of ARM microprocessors is providing operation
with
3 a) Low cost and low power consumption CO2.1 CL1
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management
ARM processors where basically designed for
a) Main frame systems
4 b) Distributed systems CO2.1 CL1
c) Mobile systems
d) Super computers
The address space in ARM is
a) 224
5 b) 264 CO2.2 CL1
c) 216
d) 232
The address system supported by ARM systems is/are______
a) Little Endian
6 b) Big Endian CO2.2 CL1
c) X-Little Endian
d) Both Little & Big Endian
Memory can be accessed in ARM systems by instructions.
i) Store ii) MOVE iii) Load iv) arithmetic v) logical
7 a) i, ii, iii
CO2.3 CL1
b) i, ii
c) i, iv, v
d) iii, iv, v
RISC stands for
a) Restricted Instruction Sequencing Computer
8 b) Restricted Instruction Sequential Compiler CO2.3 CL1
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer
In the ARM, PC is implemented using
a) Caches
9 b) Heaps CO2.3 CL1
c) General purpose register
d) Stack
The additional duplicate register used in ARM machines are called as
10 a) Copied-registers CO2.3 CL1
b) Banked registers
 c) Extra registers
d) Extential registers
Which LCD display is present in LPC 2148 Development Board?
a) 8*8 LED
11 b) 2*32 LCD CO2.4 CL1
c) 2*16 LCD connected peripherally
d) 2*16 LCD on-chip
Who is the founder of LPC2148 board?
a) Intel
12 b) Atmel CO2.4 CL1
c) Motorola
d) Philips
LPC 2148 pro development board has on chip memory.
a) 500k
13 b) 625k CO2.4 CL1
c) 512k
d) 425k
The USB controller provides high speed interface to laptop/PC with a
speed of
a) On-chip USB with 12Mb/s CO2.4
14 CL1
b) On-chip USB with 15Mb/s
c) Peripheral USB with 12Mb/s
d) Peripheral USB with 15Mb/s
Which IDE is supported by LPC2148 board?
a) Code Blocks
15 b) AVR Studio 4 CO2.4 CL1
c) Keil uVersion 4
d) Walldorf
Timer in the board has compare and capture channels.
a) 3 and 4
16 b) 4 and 3 CO2.5 CL1
c) 4 and 4
d) 3 and 3
Which of the following helps in the generation of waveforms?
a) timer
17 b) inputs CO2.5 CL1
c) outputs
d) memory
What is the clock source for the timers?
a) some external crystal applied to the micro-controller for executing
the timer
18 CO2.5 CL1
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Average power is reduced by using ______?
a) Pulse Width Modulation
19 b) Continuous Wave Modulation CO2.6 CL1
c) Angular Modulation
d) Demodulation
In what technique the signal’s energy is distributed in the form of
pulses?
a) Pulse Width Modulation
20 CO2.6 CL1
b) Continuous Wave Modulation
c) Angular Modulation
d) Demodulation
Percentage of the time at which signal is ON is referred to as ______?
21 CO2.6 CL1
a) Input Cycle
 b) Output Cycle
c) Duty Cycle
d) Incoming Cycle
What does UART stand for?
a) universal asynchronous receiver transmitter
22 b) unique asynchronous receiver transmitter CO 2.7 CL1
c) universal address receiver transmitter
d) unique address receiver transmitter
How is data detected in a UART?
a) counter
23 b) timer CO 2.7 CL1
c) clock
d) first bit
What rate can define the timing in the UART?
a) bit rate
24 b) baud rate CO 2.7 CL1
c) speed rate
d) voltage rate
What is the processor used by ARM7?
a) 8-bit CISC
25 b) 8-bit RISC CO 2.7 CL1
c) 32-bit CISC
d) 32-bit RISC
Which of the signal is set to one, if no data is transmitted?
a) READY
26 b) START CO 2.7 CL1
c) STOP
d) TXD
How is the baud rate supplied?
a) baud rate voltage
27 b) external timer CO 2.7 CL1
c) peripheral
d) internal timer
What is the processor used by ARM7?
a) 8-bit CISC
28 b) 8-bit RISC CO 2.8 CL1
c) 32-bit CISC
d) 32-bit RISC
What is the instruction set used by ARM7?
a) 16-bit instruction set
29 b) 32-bit instruction set CO 2.8 CL1
c) 64-bit instruction set
d) 8-bit instruction set
Architecturally, speed modes present in Cortex-M processors are
a) 2
30 b) 3 CO 2.8 CL1
c) 4
d) 5
In Cortex-M processors, NVIC stands for
a) Nested Voltage Interrupt Controller
31 b) Nested Variable Interrupt Controller CO 2.8 CL1
c) Nested Velocity Interrupt Controller
d) Nested Vectored Interrupt Controller
 Part B
S.No Questions CO CL Level
How do Harvard and Von Neumann styles of architecture vary from one
1. CO2.1 CL2
another?
2. Compare CISC Architecture vs. RISC Architecture CO2.1 CL2

3. Justify the ARM Nomenclature. CO2.1 CL3

From the fundamentals, draw the architecture of ARM processor with
4. CO2.2 CL3
relevant explanation
5 How does an ARM work? Elucidate the features of ARM CO2.2 CL2
6 Is it possible for a processor to support both little and big-endian methods? CO2.2
CL3
Explain LOAD AND STORE INSTRUCTION

7 In the subroutine, specify whether a return statement is necessary. CO2.3 CL2

8 Provide a list of features of LPC 214x processor CO2.4 CL3

9 Elaborate the peripherals used in LPC 2148 family CO 2.5 CL3
10 Elucidate the concept of PWM with required diagrams. CO2.6 CL2
11 Outline the working of a UART in LPC214x in detail. CO2.7 CL2
12 Draw the architecture of ARM Cortex M3 MCU processor and describe its
CO2.8 CL2
functional units.

PART C

CL
S.No Questions CO
Level
Draw the architecture of ARM processor and explain its functional
1. CO2.1 CL2
units.
[i] Examine the operation of the BL instruction, including the state of
ARM registers before and after its operation. CO2.2 CL2
2.
[ii] Calculate the value to be given in PWMMR0 and PWMMR3 to get a CO2.6 CL2
pulse train of period 5ms and duty cycle of 25% in ARM.
Write a program to find the sum of 4X + 9Y + 4Z, where X = 2, Y = 3 and Z
3. CO 2.2 CL2
= 4 using ARM Processor instruction set.
Generalize the types of stacks and subroutines supported by ARM
4 CO2.3 CL3
processor.
Outline the procedure to generate the square wave from Timer unit in
6 CO 2.4 CL3
LPC214x chip with an example code.
Determine the values to be entered in the PWMPCR register for the
7 following situations? i) Single edge control for PWM3 ii) Double edge CO 2.6 CL3
control for PWM3 iii) Single edge control for PWM1, 2 and 3
With necessary illustrations explain the features of the ARM 9 processor
8 CO 2.7 CL2
Core.
Draw the architecture of ARM Cortex M3 MCU processor and describe
9 CO 2.8 CL2
its functional units.
 UNIT III EMBEDDED PROGRAMMING

[CO3.1]Components for embedded programs- [CO3.2]Models of programs- [CO3.3]Assembly, linking and

loading – [CO3.4]compilation techniques- [CO3.5]Program level performance analysis – [CO3.6]Software
performance optimization – [CO3.7]Program level energy and power analysis and optimization – [CO3.8]Analysis
and optimization of program size- [CO3.9]Program validation and testing.
PART – A
CL
S.No Questions CO
Level
1. In the below drawn schematic, what does an arrow between the circles indicate?

CO 3.1 CL1

a. Present state
b. Next state
c. State transition
d. Don't care condition
2. Where are signals received from, at the output decoder in generalized form of
Mealy circuit?
A. Input of memory elements
B. Output of memory elements
C. External inputs CL1
CO 3.1
D. External outputs
a. A & D
b. B & C
c. B & D
d. A & C
3. A queue follows __________
a) FIFO (First In First Out) principle
CL1
b) LIFO (Last In First Out) principle CO 3.2
c) Ordered array
d) Linear tree
4. Which of the following model is used to show how data flows through a sequence
of processing steps?
a) Object models CL1
CO 3.2
b) system model
c) semantic data models
d) data flow model
5. Which of the following is also known as loader?
a) locater
CL1
b) linker CO 3.3
c) assembler
d) compiler
6. __________ converts the programs written in assembly language into machine
instructions.
a) Machine compiler CL1
CO 3.3
b) Interpreter
c) Assembler
d) Converter
7. The assembler stores all the names and their corresponding values in ______
CL1
a) Special purpose Register CO 3.3
b) Symbol Table
 c) Value map Set
d) None of the mentioned
8. Which of the following gives the final control to the programmer?
a) linker
CL1
b) compiler CO 3.3
c) locater
d) simulator
9. What is the first stage of the compilation process?
a) pre-processing
CL1
b) post-processing CO 3.4
c) compilation
d) linking
10. Which of the following produces an assembler file in the compilation process?
a) pre-processor
CL1
b) assembler CO 3.4
c) compiler
d) post-processing
11. Which file is converted to an object file?
a) hex file
CL1
b) decoded file CO 3.4
c) coded file
d) assembly file
12. Which of the following processes the source code before it goes to the compiler?
a) compiler
CL1
b) simulator CO 3.4
c) pre-processor
d) emulator
13. During the execution of the instructions, a copy of the instructions is placed in
the ______
a) Register CL1
CO 3.5
b) RAM
c) System heap
d) Cache
14. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz
respectively. Suppose A can execute an instruction with an average of 3 steps and
B can execute with an average of 5 steps. For the execution of the same
instruction which processor is faster? CL1
CO 3.5
a) A
b) B
c) Both take the same time
d) Insufficient information
15. The clock rate of the processor can be improved by _________
a) Improving the IC technology of the logic circuits
CL1
b) Reducing the amount of processing done in one step CO 3.5
c) By using the overclocking method
d) All of the mentioned
16. An optimizing Compiler does _________
a) Better compilation of the given piece of code
CL1
b) Takes advantage of the type of processor and reduces its process time CO 3.5
c) Does better memory management
d) None of the mentioned
17. The ultimate goal of a compiler is to ________
a) Reduce the clock cycles for a programming task
CL1
b) Reduce the size of the object code CO 3.5
c) Be versatile
d) Be able to detect even the smallest of errors
18. HTTP request is between
a) client and host
CL1
b) client and server CO 3.6
c) server and host
d) user and serve
19. Which of the following is not the layer of the OSI Model?
a) Transport Layer
CL1
b) Network Layer CO 3.6
c) Session Layer
d) Atomic Layer
20. Which of the following helps in reducing the energy consumption of the
embedded system?
a) compilers CL1
CO 3.7
b) simulator
c) debugger
d) emulator
21 Which of the following help to meet and prove real-time constraints?
a) simulator
CL1
b) debugger CO 3.7
c) emulator
d) compiler
22 Which of the following is an important ingredient of all power optimization?
a) energy model
CL1
b) power model CO 3.7
c) watt model
d) power compiler
23 Which loop transformation reduces the energy consumption of the memory
systems?
a) loop permutation CL1
CO 3.8
b) loop tiling
c) loop fission
d) loop fusion
24 LSD stands for ________________
a) Lean Software Development
CL1
b) Live Software Development CO 3.8
c) Less Software Data
d) Least Software Dataloss
25 A value ____________ technique is used to identify waste.
a) Mapping
CL1
b) Stream CO 3.9
c) Stream Mapping
d) Flow
26 Which of the following testing is related to the boundary value analysis?
a. White box and black box testing
CL1
b. White-box testing CO 3.9
c. Black box testing
d. None of the above
27 Which testing technique is used for usability testing?
a. White-box testing
CL1
b. Grey box testing CO 3.9
c. Black Box testing
d. Combination of all
28 Which of the following term describes testing?
a) Finding broken code
CL1
b) Evaluating deliverable to find errors CO 3.9
c) A stage of all projects
d) None of the mentioned
29 What is Cyclomatic complexity?
a) Black box testing
CL1
b) White box testing CO 3.9
c) Yellow box testing
d) Green box testing
30 White Box techniques are also classified as
a) Design based testing
CL1
b) Structural testing CO 3.9
c) Error guessing technique
d) None of the mentioned
31 The testing in which code is checked
a) Black box testing
CL1
b) White box testing CO 3.9
c) Red box testing
d) Green box testing
32 Behavioral testing is
a) White box testing
CL1
b) Black box testing CO 3.9
c) Grey box testing
d) None of the mentioned
 PART-B

CL
Level
S.No Questions CO

1 Design a seat belt controller using Finite-State Machine CO 3.1 CL2

2 Examine the Data flow graph for the expression: x = a*b + 5*(c − d) CO 3.1 CL2

3 Outline the significance of CDFG. CO 3.2 CL2

4. In compilation process, explain the role of Assemblers CO 3.3 CL2

5. In compilation process, explain the role of Linkers CO 3.3 CL3

6. Compute the Compilation Process with DFG and its Assembly code CO 3.4 CL3
Illustrate with necessary explanation about the Measurement-driven
7. CO 3.5 CL2
Performance Analysis
8. Encapsulate the Loop Optimizations used in software performance optimization CO 3.6 CL3
Outline the Cache-oriented loop optimizations & Performance optimization
9 CO 3.7 CL2
strategies
10 How program size is optimized and analyzed? CO 3.8 CL3

11 Compare black box and white box testing methods for system design. CO 3.6 CL2

12 How to do clear box testing? CO 3.9 CL3

PART - C
 CL
S.No Questions CO
Level
Explore the components of embedded program and discuss in detail about each
1 CO 3.1 CL2
component.
[i] Can you apply code motion to the following example? Explain [6]
for(i = 0; i<N;i++)
for(j =0;j,M;j++) CO 3.2 CL1
2
z[i][j] = a[i] * b[i][j]; CO 3.9 CL1

[ii] Discuss in detail about the various techniques used in “black box testing”.[6]
[i]Find the cyclomatic complexity of the CDFG for the code fragment given: [6]
if(a < b) {
if(c < d)
x = 1;
else
x = 2;
}
3 CO 3.4 CL1
else {
if(e < f)
X = 3;
else
X = 4;
}
[ii] With a neat flowchart, explain the steps involved in compiling a program.[7]
4 Outline the Program level energy and power analysis and optimization. CO 3.7 CL4

5 With the help of a flow chart describe the basic compilation process. CO 3.4 CL2

6 Enumerate the different techniques used in software performance optimization. CO 3.6 CL3
Illustrate the Control /Data flow graph for a While loop with necessary diagrams
7 CO 3.4 CL2
and explain.
Compare various program validation and testing methods done for system
8 CO 3.8 CL3
design.
 UNIT IV - REAL TIME SYSTEMS
[CO4.1] Structure of a Real Time System –– [CO4.2] Estimating program run times – [CO4.3] Task
Assignment and Scheduling – [CO4.4] Fault Tolerance Techniques – [CO4.5] Reliability, Evaluation
– [CO4.6] Clock Synchronization.
S.No Questions CO CL Level
In real time operating system
a) all processes have the same priority
1 b) a task must be serviced by its deadlineperiod CO4 .1 CL1
c) process scheduling can be done only once
d) kernel is not required
Hard real time operating system has _____ jitter than a soft real time
operating system.
2 a) less
CO4 .1 CL1
b) more
c) equal
d) none of the mentioned
For real time operating systems, interruptlatency should be
a) minimal
3 b) maximum CO4 .1 CL1
c) zero
d) dependent on the scheduling
What is the Real-time systems?
a) Used for monitoring events as they occur
4 b) Primarily used on mainframe computers CO4 .1 CL1
c) Used for real-time interactive users
d) Used for program development
The __________ Operating System pays more attention to the meeting
of the time limits.
5 a) Network CO4 .1 CL1
b) Distributed
c) Online
d) Real-time
When the System processes data instructions without any delay is called
as
6 a) online system CO4 .1 CL1
b) real-time system
c) instruction system
d) offline system
Which of the following is correct in real time?
a) non-preemptive kernels
7 b) preemptive kernels CO4 .2 CL1
c) neither preemptive nor non-preemptive kernels
d) pre-emptive kernels or non pre-emptive kernels
_____ have been developed specifically for pipelined systems.
a) Utility software
8 b) Speed up utilities CO4 .2 CL1
c) Optimizing compilers
d) None of the mentioned
The pipelining process is also called as ______
9 a) Superscalar operation CO4 .2 CL1
b) Assembly line operation
 c) Von Neumann cycle
d) None of the mentioned
What does WCTE stand for?
a) wait case execution time
10. b) wait case encoder time CO4 .2 CL1
c) worst case execution time
d) worst code execution time
What is the high speed memory between the main memory and the CPU
called?
a) Register Memory
11. CO4 .2 CL1
b) Cache Memory
c) Storage Memory
d) Virtual Memory
In ____________ mapping, the data can be mapped anywhere in the
Cache Memory.
12. a) Associative
CO4 .2 CL1
b) Direct
c) Set Associative
d) Indirect
Which of the following defines the task which must be executed at every
defined unit of time?
a) aperiodic task
13. CO4 .3 CL1
b) periodic task
c) job
d) process
Which of the following is an aperiodic task requesting the processor at
unpredictable times?
a) job
14. CO4 .3 CL1
b) aperiodic task
c) sporadic
d) periodic task
Which of the following schedulers take decisions at run-time?
a) pre-emptive scheduler
15. b) non pre-emptive scheduler CO4 .3 CL1
c) dynamic scheduler
d) static scheduler
The ____________ scheduling algorithm schedules periodic tasks using
a static priority policy with preemption.
a) earliest deadline first
16. CO4 .3 CL1
b) rate monotonic
c) first cum first served
d) priority
Rate monotonic scheduling assumes that the __________
a) processing time of a periodic process is same for each CPU
burst
17. b) processing time of a periodic process is different for each CPU CO4 .3 CL1
burst
c) periods of all processes is the same
d) none of the mentioned
18. There are two processes P1 and P2, whose periods are 50 and 100
CO4 .3 CL1
respectively. P1 is assigned higher priority than P2. The processing
 times are t1 = 20 for P1 and t2 = 35 for P2. Is it possible to schedule
these tasks so that each meets its deadline using Rate monotonic
scheduling?
a) yes
b) no
c) maybe
d) none of the mentioned
A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a
period of 80 and a CPU burst of 35. The total CPU utilization is?
a) 0.90
19. CO4 .3 CL1
b) 0.74
c) 0.94
d) 0.80
Earliest deadline first algorithm assigns priorities according to _______
a) periods
20. b) deadlines CO4 .3 CL1
c) burst times
d) none of the mentioned
Using EDF algorithm practically, it is impossible to achieve 100 percent
utilization due to __________
a) the cost of context switching
21. CO4 .3 CL1
b) interrupt handling
c) power consumption
d) all of the mentioned
What type of fault remains in the systemfor some period and then
disappears?
a) Permanent
22. CO4 .4 CL1
b) Transient
c) Intermittent
d) All of the mentioned
Which of the following approaches areused to achieve reliable
systems?
a) Fault prevention
23. CO4 .4 CL1
b) Fault removal
c) Fault tolerance
d) All of the mentioned
Exception handling is a type of
a) forward error recovery mechanism
24. b) backward error recovery mechanism CO4 .4 CL1
c) All of the mentioned
d) None of the mentioned
All fault-tolerant techniques rely on
a) Integrity
25. b) Dependability CO4 .4 CL1
c) Redundancy
d) None of the mentioned

Which of the following Error Detection checks is not a part of

Application detection?
26. a) Hardware checks CO4 .5 CL1
b) Timing checks
c) Reversal checks
d) Coding checks
 Non-occurrence of improper alteration ofinformation is known as
a) Available Dependability
27. b) Confidential Dependability CO4 .5 CL1
c) Maintainable Dependability
d) Integral Dependability
In N-version programming which is theindependent generation of N,
the value of Nis
a) greater than 1
28. CO4 .5 CL1
b) less than 1
c) greater than 2
d) less than 2
In distributed systems, a logical clock isassociated with
a) each instruction
29. b) each process CO4 .6 CL1
c) each register
d) none of the mentioned
If timestamps of two events are same, thenthe events are
a) concurrent
30. b) non-concurrent CO4 .6 CL1
c) monotonic
d) non-monotonic
If a process is executing in its criticalsection
a) any other process can also execute in itscritical section
31. b)no other process can execute in its criticalsection CO4 .6 CL1
c) one more process can execute in its criticalsection
d)none of the mentioned
For proper synchronization in distributed systems
a) prevention from the deadlock is must
32. b) prevention from the starvation is must CO4 .6 CL1
c) prevention from the deadlock & starvationis must
d) none of the mentioned
The main advantage of centralized system for clock synchronization is
_____
33. a) Time is fixed CO4 .6 CL1
b) Time is unambiguous
c) There is no time delay
d) There is no jitter
 PART B (4 marks)

S.No Questions CO CL Level

CO4 .1
1 Generalize the performance measures for real time systems? CL2

CO4 .1
2 Outline the structure of a real time systems CL3

CO4 .2
3 How to estimate program run times? CL3

CO4 .2
4 Justify the need for accounting of pipelining CL3

5. How the task is assigned and What are the parameters needed? CO4 .3 CL2

6 Outline the uniprocessor scheduling algorithms. CO4 .3 CL2

7 Brief the ways of assigning priorities in scheduling. CO4 .3 CL4

8 Articulate the features of offline and online scheduling? CO4 .3 CL2

9 Attain the performance degradation of a fault tolerant system CO4 .4 CL3

10. Identify the fault types based on temporal behavior classification. CO4 .4 CL2

11. Interpret the malicious or byzantine failures. CO4 .5 CL2

12. Articulate the synchronization problem and hybrid synchronization. CO4 .6 CL3
 PART C (12 marks)

S.No Questions CO CL Level

1 Demonstrate the structure of a real time system. CO4 .1 CL2

2 How to reduce the program run times? Explain CO4 .2 CL3

From the mathematical concepts explain Identical Linear Reward

3 CO4 .3 CL3
functions in Uniprocessor scheduling.
Determine the utilization bound for the RM algorithm and explain it in
4 CO4 .3 CL3
detail.
[i] Discuss briefly about the performance degradation of a fault tolerant
system.[6]
5 CO4 .4 CL3
[ii] Discuss in detail about the timing requirements with respect to
release time and deadline for different types of processes.[6]
With necessary illustrations explain the following redundancy in fault
tolerant systems.
6 (i) Hardware Redundancy (4) CO4 .4 CL2
(ii) Software Redundancy (4)
(iii) Information Redundancy (4)
Justify the ways of Obtaining Device-Failure Rates and Measuring Error
7. CO4 .5 CL3
Propagation Time.

8. Examine the synchronization problem and temporal synchronization. CO4 .6 CL2

 Unit V - PROCESSES AND OPERATING SYSTEMS
[CO 5.1] Introduction – Multiple tasks and multiple processes – Multirate systems- [CO 5.2]Preemptive
real-time operating systems- [CO 5.3]Priority based scheduling- [CO 5.4]Interprocess communication
mechanisms – [CO 5.5]Evaluating operating system performance- [CO 5.6]power optimization strategies
for processes – [CO 5.7]Example Real time operating systems-POSIX-Windows CE. - [CO 5.8]Distributed
embedded systems – [CO 5.9]MPSoCs and shared memory multiprocessors. – [CO 5.10]Design Example
- Audio player, Engine control unit – Video accelerator.

S.No Questions CO CL Level

Which of the following works by dividing the processors time?
a) single task operating system
1 b) multitask operating system CO5 .1 CL1
c) kernel
d) applications
Which of the following decides which task can have the next time slot?
a) single task operating system
2 b) applications CO5 .1 CL1
c) kernel
d) software
Which of the following provides a timeperiod for the context
switch?
a) timer
3 CO5 .1 CL1
b) counter
c) time slice
d) time machine
Preemptive, priority based scheduling guarantees ____________
a) hard real time functionality
4 b) soft real time functionality CO5 .2 CL1
c) protection of memory
d) none of the mentioned
Real time systems must have ____________
a) preemptive kernels
5 b) non preemptive kernels CO5 .2 CL1
c) preemptive kernels or non preemptive kernels
d) neither preemptive nor non preemptive kernels
Priority inversion is solved by use of _____________
a) priority inheritance protocol
6 b) two phase lock protocol CO5 .2 CL1
c) time protocol
d) all of the mentioned
Choose one of the disadvantages of the priority scheduling algorithm?
a) it schedules in a very complex manner
b) its scheduling takes up a lot of time
7 CO5 .3 CL1
c) it can lead to some low priority process waiting indefinitely for the
CPU
d) none of the mentioned
Round robin scheduling falls under the category of ____________
a) Non-preemptive scheduling
8 b) Preemptive scheduling CO5 .3 CL1
c) All of the mentioned
d) None of the mentioned
 With round robin scheduling algorithm in a time shared system ___
a) using very large time slices converts it into First come First served
scheduling algorithm
9 b) using very small time slices converts it into First come First served CO5 .3 CL1
scheduling algorithm
c) using extremely small time slices increases performance
d) using very small time slices converts it into Shortest Job First algorithm
Rate monotonic scheduling assumes that the __________
a) processing time of a periodic process is same for each CPU burst
10. b) processing time of a periodic process is different for each CPU burst CO5 .3 CL1
c) periods of all processes is the same
d) none of the mentioned
Earliest deadline first algorithm assigns priorities according to ____
a) periods
11. b) deadlines CO5 .3 CL1
c) burst times
d) none of the mentioned
What is Interprocess communication?
a) allows processes to communicate and synchronize their actions when
using the same address space
12. b) allows processes to communicate and synchronize their actions CO5 .4 CL1
c) allows the processes to only synchronize their actions without
communication
d) none of the mentioned
Which of the following two operations are provided by the IPC facility?
a) write & delete message
13. b) delete & receive message CO5 .4 CL1
c) send & delete message
d) receive & send message
Messages sent by a process __________
a) have to be of a fixed size
14. b) have to be a variable size CO5 .4 CL1
c) can be fixed or variable sized
d) none of the mentioned
The Zero Capacity queue __________
a) is referred to as a message system with buffering
15. b) is referred to as a message system with no buffering CO5 .4 CL1
c) is referred to as a link
d) none of the mentioned
In the non blocking send __________
a) the sending process keeps sending until the message is received
16. b) the sending process sends the message and resumes operation CO5 .4 CL1
c) the sending process keeps sending until it receives a message
d) none of the mentioned
Which of the following can periodically trigger the context switch?
a) software interrupt
17. b) hardware interrupt CO5.5 CL1
c) peripheral
d) memory
 Which interrupt provides system clock in the context switching?
a) software interrupt
18. b) hardware interrupt CO5.5 CL1
c) peripheral
d) memory
Context switching is ……..
A. part of spooling
19. B. part of polling CO5.5 CL1
C. part of interrupt handling
D. part of a paging
Which of the following is an important ingredient of all power
optimization?
a) energy model
20. CO5.6 CL1
b) power model
c) watt model
d) power compiler
Which of the following helps in reducing the energy consumption of the
embedded system?
21. a) compilers
CO5.6 CL1
b) simulator
c) debugger
d) emulator
Which one of the following is a real time operating system?
a) RTLinux
22. b) VxWorks CO5.7 CL1
c) Windows CE
d) all of the mentioned
What is an operating system?
a) interface between the hardware and application programs
23. b) collection of programs that manages hardware resources CO5.7 CL1
c) system service provider to the application programs
d) all of the mentioned
Which memory storage is widely used in PCs and Embedded Systems?
a) EEPROM
24. b) Flash memory CO5.8 CL1
c) SRAM
d) DRAM
Because of virtual memory, the memory can be shared among
____________
a) processes
25. CO5.8 CL1
b) threads
c) instructions
d) none of the mentioned
Effective access time is directly proportional to ____________
a) page-fault rate
26. b) hit ratio CO5.8 CL1
c) memory access time
d) none of the mentioned
What does MP3 stands for?
27. CO5.9 CL1
a) MPEG audio layer 3
 b) MKV video layer 3
c) MPEG video layer 3
d) JPEG audio layer 3
Which of the following does the overall functions like controlling the
MP3 files reading from the memory and applying them to audio codec
and controlling playback process from control keys?
28 a) MCU CO5.9 CL1
b) USB
c) MPMan
d) AM tuner
As the temperature is low, the _________valve speeds up the engine idle
speed to fast idling.
a) nozzle
29 CO5.10 CL1
b) throttle
c) air
d) none of the mentioned
When the engine is cold, the __________ plate will be in closed position.
a) nozzle
30 b) throttle CO5.10 CL1
c) air
d) none of the mentioned

PART B (4 marks)

S.No Questions CO CL Level

Predict the services of operating system in handling multiple tasks and

1 CO5 .1 CL2
multiple processes

2 Interpret Asynchronous input for a control panel CO5 .1 CL3

Justify that Engine Control Unit is an embedded system. Explain in detail

3 CO5 .1 CL3
the hardware and software components of Engine Control Unit.

4 Analyse priority-based scheduling in detail. CO5.1 CL2

5. Outline the concepts of Semaphore CO5. CL2

6 Illustrate Message Passing in just a few words. CO5.3 CL2

7 Elaborate the concept of mailboxes. CO5.3 CL2

8 How to measure operating system performance? CO5.3 CL2

 9 Demonstrate the architecture of WinCE. CO5.4 CL3

10. Demonstrate the Portable Operating System Interface (POSIX). CO5.6 CL2

11 Infer in detail about the architecture of Audio player. CO5.7 CL2

Identify the features of pre-emptive execution with the help of a

12 CO5.8 CL2
Sequence diagram

PART C (12 marks)

S.No Questions CO CL Level

[i] With relevant examples, bring out the difference between clock CO5.1
1 driven scheduling approach and priority driven scheduling approach.[6] CL2
[ii] With neat sketches, explain the working of video accelerator.[6]
Compare the principle, merits and limitations of Inter-process CO5.2
2 CL3
communication mechanism.
Illustrate in detail about CO5.3

3 [i] Characteristics of distributed embedded System.[6] CL3

[ii] Architecture of Distributed Embedded System with neat sketches.[6]

Explain the concepts of Multiprocessor System-On-Chip (MPSoC) and CO5.4

4
Shared memory multiprocessors used in embedded applications. CL2
Discuss about the features and services of windows CE real time operating CO5.7
5
system CL2
Develop the working of Engine control unit in detail. CO5.10
i)Theory of operations and requirements. (2)
ii)Specification (3)
6
iii)System Architecture (3) CL3
iv)Component designing and testing (2)
v)System integration and testing (2)
From design flow analysis to architectural design, illustrate Audio Player CO5.10
7
using UML methodology. CL3
Evaluate the system design technique for large data analysis using video CO5.10
8
accelerator CL3