CHP 10 Boolean Logic MS
CHP 10 Boolean Logic MS
10 Boolean logic
1 a OR gate
b NAND gate
c XOR gate
2 A B C Working area X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
4 a A B Working area X
0 0 0
0 1 1
1 0 1
1 1 1
b OR gate
5 a A B C Working area X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
b As the output X exactly matches input C, the entire logic circuit could be removed and
the output connected directly to the input C.
6 a A B C Working area X
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
b AND gate
7 a (A AND NOT B) AND (B OR C)
or
(A. ).(B + C)
b
c T A P Working area X
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
9 a
b A B C Working area X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
c X Y Z Working area Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
A B C Working area X
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
12 a
b A B C Working area X
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1