

C H A P T E R 04C


ARITHMETIC FOR
COMPUTERS

1
 
 Tailoring the ALU
to the MIPS

How could we implement the set-

on-less-than instruction (slt) on
the ALU design?

2
Let us first remember the slt instruction:

# rd=1 if rs<rt , set on less than instruction

slt rd, rs, rt

 produces a 1 (rd=1) if rs < rt

 produces a 0 (rd=0) if rs>= rt
3
Example:
slt $t0, $s3, $s4
# $t0 = 1 if $s3 < $s4
# $t0 = 0 if $s3 ≥ $s4
Example:
slt C, A, B
# C = 1 if A < B
# C = 0 if A ≥ B 4
 Note: slt is an
arithmetic instruction
 Note: 32 1-bit ALUs,
are connected in order
to construct a 32-bit
ALU
5
 We could implement the slt
instruction by
1. Subtracting: (A - B).

Note: ALU supports subtraction

6
2. If (A - B) < 0, it implies that A < B.
a. It implies also that the sum of the
subtraction is a negative number
b. the sign-bit of the above sum,
(which is the leftmost bit) = 1.
c. the final result (of slt after subtraction)
should be (thirty-one 0s and one 1:
0000 0000 0000 0000 0000 0000 0000 0001
7
d. the final result of the slt consists of
31 zeros and a 1 at the LSB.
e. In the design of the 32-bit-ALU we
could make all the 1-bit ALUs to
output 0, except the LSB 1-bit-
ALU which should output the
sign-bit (1) of the subtraction A-B

8
3. If (A - B) ≥ 0, it implies that A ≥ B

a. It implies also that the sum of the

subtraction is a positive number
b. the sign-bit of the above sum,
(which is the leftmost bit) = 0.
c. the final result (after the
subtraction) should be:
0000 0000 0000 0000 0000 0000 0000 0000
9
d. the final result of the slt consists of
31 zeros and another 0 at the
LSB.
e. In the design of the 32-bit-ALU we
could make all the 1-bit ALUs to
output 0, except the LSB 1-bit-
ALU which should output the
sign-bit (0) of the subtraction A-B
10
4. Summarizing SLT:
a. Subtract:
 Set the CarryIn of the LSB-ALU
to 1
Note: The LSB-ALU is the top 1-
bit ALU, in the diagram)
 Set the Binvert to 1.
11
b. Extent the big multiplexer with
another input
i. Call this new input Less
ii. the Less input of all 1-bit ALUs
receives the value 0, except the
Less input of the LSB-ALU
iii.the Less input of the LSB-ALU
should be connected to the
output (called Set) of the adder of
the last ALU (the last ALU is the
sign-bit-ALU or ALU31). 12
5. The following figure shows two
diagrams.
a. The top diagram is the 1-bit
ALU to be used for all 1-bit
ALUs except the last ALU (the
sign-bit-ALU or ALU31).
13
b. The bottom diagram is to be
used for the last ALU (the sign-
bit-ALU or ALU31).

i. the bottom diagram includes

an overflow box. (Whatever is
in the box detects an
overflow)
14
 Binvert Operation
CarryIn

a
0

Result
b 0 2

Less 3

a. CarryOut

Figure. Implementing slt. (a) 1-bit ALU to be used for

all 1-bit ALUs except the last ALU (the sign-bit-ALU
or ALU31). 15
 B i n v e rt O p e r a ti o n
C a r ryI n

a
0

R e s u lt
b 0 2
1

L e ss 3
Set

O v e r flo w
O v e rfl o w
d e t e c tio n
b.

Figure. Implementing slt. (b) diagram to be

used for the last ALU (the sign-bit-ALU or
16
ALU31).
 For slt: (a) CarryIn=1, Binvert=1,
and Operation = opcode for slt.
 The Set output of the last 1-bit-
ALU is the input to the Less
input of the first 1-bit-ALU.

17
 B i n v e rt C a rr yI n O p e r a ti o n

a 0 C a rr yI n
b 0 A L U 0 R e s ult 0
L e s s
C a r r y Out

a 1 C a rry I n
b 1 A L U 1 R e s ult 1
0 L e s s
C a r r y Out

a 2 C a rr yI n
b 2 A L U 2 R e s ult 2
0 L e s s
C a r r y Out

C a rr yI n

a 3 1 C a rr yI n R e s ult 3 1
b 3 1 A L U 3 1 S e t
0 L e s s O v e r fl o w

Figure: Implementing slt C, A, B, 18

where number A: a …a a a and number B: b …b b b

 (inverts every b input for the FA)
B i n v e rt = C a rr yI n = O p e r a ti o n =3= slt (every
mux will output
its 4th input, the
1 C a rr yI n Less Input)
0 A L U 0
Less = SET =
C a r r y Out

0 C a rry I n
1 A L U 1
Less = 0
C a r r y Out

Result =
0 C a rr yI n
0 A L U 2
Less = 0
C a r r y Out

C a rr yI n

0 C a rr yI n
0 A L U 3
Less = 0 SET =output of the FA =
Carry Out

Example SLT when A<B: Assume a 4-bit computer.

19
slt regC, regA, regB, where regA = 0001 and regB = 0010,
 (1 inverts every b input for the FA)
B i n v e rt =1 C a rr yI n =1 O p e r a ti o n =3= slt (every
mux will output
its 4th input, the
1 C a rr yI n Less Input)
0 1 A L U 0
Less = SET =
C a r r y Out

0 C a rry I n
1 0 A L U 1 0
Less = 0
C a r r y Out

Result =
0 C a rr yI n
0 1 A L U 2 0
Less = 0
C a r r y Out

C a rr yI n

0 C a rr yI n 0
0 1 A L U 3
Less = 0 SET =output of the FA =
Carry Out

Example SLT when A<B: Assume a 4-bit computer. 20

slt regC, regA, regB, where regA = 0001 and regB = 0010,
 B i n v e r t(Binvert =? ) C a rr yI n =? O p e r a ti o n = 3= slt (every
mux will output
its 4th input, the
0 C a rr yI n Result = Less = SET = Less Input)
1 A L U 0
Less = SET =
C a r r y Out

1 C a rry I n Result = Less =

0 A L U 1
Less = 0
C a r r y Out

Result =
0 C a rr yI n Result = Less =
0 A L U 2
Less = 0
C a r r y Out

C a rr yI n

0
Result = Less =
C a rr yI n
0 A L U 3
Less = 0 SET =output of the FA =
Carry Out

Example SLT when A>B: Assume a 4-bit computer.

slt regC, regA, regB, where regA = 0010 and regB = 0001, 21
 1 (Binvert =1 Inverts every = 3= slt (every
B i n v e rt
b input for the FA)
C a rr yI n =1 O p e r a ti o n
mux will output
1 its 4th input, the
0 C a rr yI n Result = Less = SET = Less Input)
1 0 A L U 0
Less = SET =
C a r r y Out

1 C a rry I n Result = Less = 0

0 1 A L U 1
Less = 0
C a r r y Out

Result =
0 C a rr yI n Result = Less = 0
0 1 A L U 2
Less = 0
C a r r y Out

C a rr yI n

0
Result = Less = 0
C a rr yI n
0 1 A L U 3
Less = 0 SET =output of the FA =
Carry Out

Example SLT when A>B: Assume a 4-bit computer. slt regC, regA, regB,
Where regA = 0010 and regB = 0001 22
conditional branch:
MIPS must support conditional branch,
depending on whether two registers
contain equal or unequal values.

In order to test if two numbers (A

and B) are equal subtraction is
used: If (A - B) = 0 then A = B

23
 The easiest way to test for equality is to
NOR all the Results of all 1-bit ALUs. (NOR
gate: Inverting the output of the OR gate).
Therefore, if all inputs of the NOR gate are
0, the NOR gate outputs 1.
OR gate NOR gate
a b c=a+b NOR
0 0 0 1 a

0 1 1 0 b
c

1 0 1 0
1 1 1 0
24
Test for equality Diagram: In order to test if two numbers (A and
B) are equal, subtraction is used: If (A - B) = 0 then A = B
B n e g a te O p era ti o n

a0 Carry I n R e sult 0 If the output of the NOR

b0 AL U0
Le ss gate =1, all its inputs = 0.
C a rry O ut If, after subtraction, all
inputs of the NOR gate
a1 C a rr yIn
have the value 0,
R e sult 1
b1 AL U1 then A = B
0 Le ss
C a rry O ut

a2 C a rr yIn R e sult 2
b2 AL U2
0 Le ss
C a rry O ut

R e sult3 1
a 31 C a rr yIn
b 31 AL U31 Set
0 Le ss O v erfl o w

25
If all the Results (from all 1-bit-
ALUs) are 0's then the output of
NOR gate is 1.
If the NOR gate outputs 1, then A –
B = 0 or A = B
Binvert and CarryIn are both 1
when subtracting. They are both 0
when adding. Binvert and CarryIn
are connected together and the
new input is called Bnegate. 26
The following symbol is commonly used to
represent an n-bit ALU. An n-bit ALU
receives, as major inputs, two n-bit
numbers, A and B.
ALU operation

n lines for n bits

A
ALU Zero
result (n lines for n bits)
n lines for n bits
B Overflow

27
Carryout
 Multiplication
 Multiplication is more
complicated and time consuming
than addition
 Multiplication is accomplished

0
via shifting and addition
 Multiplication takes more time
and more area (more hardware)
28
Example of multiplication in decimal:

Multiplicand 1 0 0 0 ten
Multiplier x 1 0 0 1 ten
1000 1stpartial product (1x1000)
0000 2ndpartial product (0x1000)
0000 3rdpartial product (0x1000)
1000 4thpartial product (1x1000)
Product 1 0 0 1 0 0 0 ten Final Product

29
Example of multiplication in decimal:

Multiplicand 2 3 9 ten
Multiplier x 1 2 3 ten
717 1st partial product (3x239)
478 2ndpartial product (2x239)
239 3rd partial product (1x239)
Product 29397 ten Final Product

30
 The sign of the product
depends on the signs of the
multiplicand and multiplier
If the signs are the same, the
product is positive
If the signs are different, the
product is negative
31
 The number of digits in the
product is larger
 The length of the product of
an n-bit multiplicand
and an m-bit multiplier
is n+m bits long

32
When two binary numbers are
multiplied, both numbers must
be in true (uncomplemented)
form

33
Steps of the partial product method
of binary multiplication:

1. Determine the sign of the

product (from the signs of the
multiplicand and multiplier).
2. Change any negative numbers
into true (uncomplemented) form.
(Find the 2's complement of only
the negative numbers) 34
3. Starting with the least significant
bit (LSB) of the multiplier,
generate the partial products.
Each successive partial
product is shifted by one bit
to the left
4. Add each successive partial
product to the sum of the
previous partial products, until the
final product is found. 35
5. If the sign (determined in step 1)
is
a. negative, find the 2's
complement of the product
(final product) and attach the
sign (1) to the product.
b. positive, leave the product
(final product) as it is and
attach the sign (0) to the
product. 36
 Example
(multiplication) in binary:

Multiply the signed binary numbers:

0101 0011 (multiplicand)
and 1100 0101 (multiplier).

37
 Solution:
0101 0011 (multiplicand)=
=64+16+2+1= +83
1100 0101 (multiplier) is negative
0011 1011 =32+16+8+2+1=59
(therefore –59)
The answer should be at the end
(+83)x(-59)= -4897
38
 Step 1:

The sign of the multiplicand is 0

and the sign of the multiplier is1.
The sign of the product will be 1
(negative)
39
 Step 2:

The 2's complement of the

multiplier 1100 0101 is
0011 1011

40
 Step 3 and 4:
The multiplication proceeds by
finding the partial products:
 Notice that only the magnitude
bits are used in these steps.
 Each successive partial product
is shifted by one bit to the left.
41
bits 6543210
Multiplicand 1010011
Multiplier x0111011
1010011 1st partial product-bit0
+1010011 2nd partial product-bit1
11111001 Sum of the 1st and 2nd
+ 0000000 3rd partial product-bit2
011111001 Sum
+1010011 4th partial product-bit3
1110010001 Sum
+1010011 5th partial product-bit4
100011000001 Sum
+1010011 6th partial product-bit5
1001100100001 Sum
+0000000 7th partial product-bit6
42
1001100100001 Sum
 Step 5:

The sign of the product is 1 as

determined in step 1. We should
find the 2's compliment of the
product

43
Product: 1 0011 0010 0001
2's compliment: 0 1100 1101 1111

We should also attach the sign to

the product:
1 0 1100 1101 1111

44
Confirming that the above product
is equal to (+83) x (-59) = - 4897

1 0 1100 1101 1111 is a negative

number
2's compliment of 1 0 1100 1101 1111:
0 1 0011 0010 0001

45
 Example of positive (signed)
number:
214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
+ 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
0 1 0 0 1 1 0 0 1 0 0 0 0 1

0 1 0011 0010 0001 =

= 4096+ 512+256+32+1= +4897
Therefore the binary number 1 0 1100
1101 1111 represents the decimal
number -4897 46
 We have reviewed, so far, the
basics of binary multiplication
 The following section will
present one algorithm and
hardware that executes
multiplication
 In this section we will
assume that we multiply
only positive numbers 47
 The multiplicand register, the ALU, and the product register are
all 64-bits wide. The multiplier register is 32 bits wide.
 The 64-bit product register is initialized to zero.
 In the right half (32 bits) of the 64-bit multiplicand register we place
the 32-bit multiplicand. The left half is initialized to zero.
 The multiplicand register is shifted to the left by 1 bit, at every step
of the algorithm.

Multiplicand
64 bit Shift left
64 bits

add Multiplier
64-bit ALU 32 bitShift right
32 bits

Product
Control test
64 bit Write
64 bits
48
Figure. First version of multiplication hardware for 32 bit numbers
Shifting occurs in order to align
the multiplicand with the sum
being accumulated in the 64-bit
product register
The control-test-unit has four
outputs, instructing for shift-left,
add, write, shift-right. It has one
input to test the LSB of the
multiplier (if it is 0 or 1). 49
 Figure: The first multiplication algorithm, using the
hardware described before
Sta rt

M ultiplier0 = 1 1 . T e st M ultiplier0 = 0
M ultiplier0

1 a . Add m ultiplica nd to product a nd

pla ce the re sult in Pro du ct re gister

2. S hift the M ultiplica nd re gister le ft 1 bit

3. S hift the M ultiplier re giste r right 1 bit

No: < 3 2 re pe titio ns

3 2nd re petition?

Y e s: 3 2 re petitio ns
50
Do ne
 The algorithm, above, shows the
three basic steps needed for
each bit
 The three basic steps are
repeated 32 times to obtain the
product

51
 The LSB of the multiplier
determines whether the
multiplicand is added to the
product register.
 Let us call the LSB of the
multiplier Multiplier0

52
 Shifting the multiplicand register
to the left (in step 2 of the
algorithm) has the effect of moving
the intermediate operands to the
left, just when multiplying by hand
 Shifting the multiplier register to
the right (in step 3 of the
algorithm), provides the next bit to
be multiplied in the following
iteration. 53
Example using the first version
of algorithm and hardware to
multiply:

Using 4-bit numbers (to save

space), multiply 2x3 (0010 x 0011).

54
1st version: Solution (2 x 3) or (0010 x 0011):

Iteration Step Multiplier Multiplicand Product

1 Initial values 0011 0000 0010 0000 0000
2 LSB=1: Prod=Prod+Mlcnd

Shift left Multiplicand

Shift right Multiplier
3 LSB=1: Prod=Prod+Mlcnd

Shift left Multiplicand

Shift right Multiplier
4 LSB=0 no Addition
Shift left Multiplicand
Shift right Multiplier
5 LSB=0 no Addition
Shift left Multiplicand
55
Shift right Multiplier
1st version: Solution (2x3) or (0010 x 0011):

Iteration Step Multiplier Multiplicand Product

1 Initial values 0011 0000 0010 0000 0000
2 LSB=1: Prod=Prod+Mlcnd >> >> 0000 0010
Shift left Multiplicand >> 0000 0100 >>
Shift right Multiplier 0001 >> >>
3 LSB=1: Prod=Prod+Mlcnd

Shift left Multiplicand

Shift right Multiplier
4 LSB=0 no Addition
Shift left Multiplicand
Shift right Multiplier
5 LSB=0 no Addition
Shift left Multiplicand
56
Shift right Multiplier
1st version: Solution (2x3) or (0010 x 0011):

Iteration Step Multiplier Multiplicand Product

1 Initial values 0011 0000 0010 0000 0000
2 LSB=1: Prod=Prod+Mlcnd >> >> 0000 0010
Shift left Multiplicand >> 0000 0100 >>
Shift right Multiplier 0001 >> >>
3 LSB=1: Prod=Prod+Mlcnd >> >> 0000 0110
Shift left Multiplicand >> 0000 1000 >>
Shift right Multiplier 0000 >> >>
4 LSB=0 no Addition
Shift left Multiplicand
Shift right Multiplier
5 LSB=0 no Addition
Shift left Multiplicand
57
Shift right Multiplier
1st version: Solution (2x3) or (0010 x 0011):

Iteration Step Multiplier Multiplicand Product

1 Initial values 0011 0000 0010 0000 0000
2 LSB=1: Prod=Prod+Mlcnd >> >> 0000 0010
Shift left Multiplicand >> 0000 0100 >>
Shift right Multiplier 0001 >> >>
3 LSB=1: Prod=Prod+Mlcnd >> >> 0000 0110
Shift left Multiplicand >> 0000 1000 >>
Shift right Multiplier 0000 >> >>
4 LSB=0 no Addition >> >> 0000 0110
Shift left Multiplicand >> 0001 0000 >>
Shift right Multiplier 0000 >> >>
5 LSB=0 no Addition
Shift left Multiplicand
58
Shift right Multiplier
1st version: Solution (2x3) or (0010 x 0011):

Iteration Step Multiplier Multiplicand Product

1 Initial values 0011 0000 0010 0000 0000
2 LSB=1: Prod=Prod+Mlcnd >> >> 0000 0010
Shift left Multiplicand >> 0000 0100 >>
Shift right Multiplier 0001 >> >>
3 LSB=1: Prod=Prod+Mlcnd >> >> 0000 0110
Shift left Multiplicand >> 0000 1000 >>
Shift right Multiplier 0000 >> >>
4 LSB=0 no Addition >> >> 0000 0110
Shift left Multiplicand >> 0001 0000 >>
Shift right Multiplier 0000 >> >>
5 LSB=0 no Addition >> >> 0000 0110
Shift left Multiplicand >> 0010 0000 >>
59
Shift right Multiplier 0000 >> >>
Each bit needs 3 steps.
If each step took 1 clock cycle,
how many clock cycles would we
need for multiplying 32 bit
numbers?

Answer: 32x3 +1 =97 cycles

60
 Second version multiplication hardware, being able to
multiply, two, 32-bit numbers
The 32-bit ALU, outputs 32 bits
The result of the ALU, are the left 32 bits, of the product
Multiplicand The 64-bit product register is initialized to zero
32 bits
32-bit multiplicand register

32 bits 32 bits

Multiplier
32 -ALU
32-bit ALU Shift right
32 bits 32-bit multiplier32 bits
register

Shift right
Product Control test
Write
64 bits
32 bits 64-bit product register

Figure. The multiplicand register and the ALU are 32 bits (instead of 64
bits of the first version). The whole product register is shifted to
the right (instead of the multiplicand to the left)
61
Second version multiplication: Minimum hardware required,
for multiplying, two, 4-bit numbers
The 4-bit ALU, outputs 4 bits
The result of the ALU, goes to the left 4 bits, of the 8 bit
Multiplicand product
32
4-bitbits
multiplicand register

4 bits 4 bits

Multiplier
4 bit-ALU
32-bit ALU Shift right
4 bits 4-bit multiplier 32 bits
register

Shift right
Product Control test
Write
64 bits
4 bits 8-bit product register

Figure: Second version multiplication: Minimum hardware

required, for multiplying, two, 4-bit numbers
62
 Second version multiplication: Minimum hardware required, for
multiplying, two, 4-bit numbers 2 x 3 (0010 x 0011)
Initial conditions
Multiplicand
The 4-bit ALU, outputs 4 bits
Multiplicand The result of the ALU, goes to the left 4 bits, of the 8 bit product
0010
32
4-bitbits
multiplicand register

4 bits 4 bits

0011
Multiplier
4 bit-ALU
32-bit ALU Shift right
4 bits 4-bit multiplier 32 bits
register

0000 Product 0000Shift right

Write
Control test

4 bits 64 bits
8-bit product register

Figure: Second version multiplication: Minimum hardware required, for

multiplying, two, 4-bit numbers 2 x 3 (0010 x 0011)
Initial conditions 63
The multiplicand register and the
ALU are now 32 bits wide. Only
the product register is 64-bits
wide. The multiplier register is
still 32 bits wide.

64
Looking at the first version of the
multiplication algorithm, we
recognize that half of the bits of
the multiplicand were always 0.
(Only half of the bits contained
useful values).
A 64-bit ALU thus seemed
wasteful and slow (since half of
the adder bits were adding 0 to
the intermediate sum. 65
Solution: Instead of shifting
the multiplicand to the left, it is
smarter, faster, and more
economical if we shift the
product to the right.

Multiplicand register and ALU

could become 32-bit
66
Each intermediate product is
added to the multiplicand and the
new product is placed in the left
half of the product register.
(Only the left half of the 64-bit
Product register is changed by
the addition)
The 64-bit product register is
initialized to zero 67
 S t a rt

M ultipli e r 0 = 1 1 . T e st M ultipli e r 0 = 0
M ultipli e r 0

1 a . A d d m ulti plic a n d t o t h e l e ft h a lf o f
th e p ro d u ct a n d pl a c e th e r e sult in
th e le ft h a lf of th e P ro d u ct r e gi st e r

Figure. The second

2 . S hift th e P ro d u ct r e giste r rig h t 1 bit
multiplication
algorithm, for 32 bit
numbers. 3 . S hift th e M ulti pli e r r e gi ste r ri g h t 1 bit

The algorithm is
repeated 32 times. N o : < 3 2 r e p e titio n s
3 2 n d r e p e titi o n ?
The algorithm is
repeated as many Y e s: 3 2 r e p e titio n s

times as the bits of

D one
the hardware.
68
Example with the 2nd algorithm : Minimum hardware for 4 bit numbers: multiply
2x3 (0010 x 0011). Initial conditions: 4-bit multiplicand = 0010,
4-bit multiplier = 0011, 8 bit product = 0000 0000
Iteration Step Multiplier Multiplicand Product
1 Initial values 0011 0010 0000 0000
2

69
Example with the 2nd algorithm : Minimum hardware for 4 bit numbers: multiply
2x3 (0010 x 0011). The LSB of the multiplier is 1  (left half of product) =
(multiplicand) + (left half of product)
Iteration Step Multiplier Multiplicand Product
1 Initial values 0011 0010 0000 0000
2 Prod=Prod+Mlcnd >> >> 0010 0000
Shift right Product >> >> 0001 0000
Shift right Multiplier 0001 >> >>
3

70
Example with the 2nd algorithm : Minimum hardware for 4 bit numbers: multiply
2x3 (0010 x 0011). The LSB of the multiplier is again 1 
(left half of product) = (multiplicand) + (left half of product)
Iteration Step Multiplier Multiplicand Product
1 Initial values 0011 0010 0000 0000
2 Prod=Prod+Mlcnd >> >> 0010 0000
Shift right Product >> >> 0001 0000
Shift right Multiplier 0001 >> >>
3 Prod=Prod+Mlcnd >> >> 0011 0000
Shift right Product >> >> 0001 1000
Shift right Multiplier 0000 >> >>
4

71
Example with the 2nd algorithm : Minimum hardware for 4 bit numbers: multiply
2x3 (0010 x 0011). The LSB of the multiplier is 0  No addition occurs and
the Product stays the same
Iteration Step Multiplier Multiplicand Product
1 Initial values 0011 0010 0000 0000
2 Prod=Prod+Mlcnd >> >> 0010 0000
Shift right Product >> >> 0001 0000
Shift right Multiplier 0001 >> >>
3 Prod=Prod+Mlcnd >> >> 0011 0000
Shift right Product >> >> 0001 1000
Shift right Multiplier 0000 >> >>
4 0 no Addition >> >> >>
Shift right Product >> >> 0000 1100
Shift right Multiplier 0000 >> >>
5

72
Example with the 2nd algorithm : Minimum hardware for 4 bit numbers: multiply
2x3 (0010 x 0011). The LSB of the multiplier is 0  No addition occurs and
the Product stays the same
Iteration Step Multiplier Multiplicand Product
1 Initial values 0011 0010 0000 0000
2 Prod=Prod+Mlcnd >> >> 0010 0000
Shift right Product >> >> 0001 0000
Shift right Multiplier 0001 >> >>
3 Prod=Prod+Mlcnd >> >> 0011 0000
Shift right Product >> >> 0001 1000
Shift right Multiplier 0000 >> >>
4 0 no Addition >> >> >>
Shift right Product >> >> 0000 1100
Shift right Multiplier 0000 >> >>
5 0 no Addition >> >> >>
Shift right Product >> >> 0000 0110
73
Shift right Multiplier 0000 >> >>
 Final (3rd) version of the multiplication hardware for 32 bit numbers
The left half of the Product register, is initialized to
Multiplicand zero. The right half, of the Product register, is filled
Multiplicand
register: 32 bits
with the 32 bit multiplier number.
32 bits
32 bits The whole Product register is shifted to the right.
32 bits
The multiplier is also shifted to the right, since it is
placed in the Product register. The test, whether the LSB
of the multiplier, is 1 or 0, is done at the LSB of the Product
register.
ALU: 32 bits
32-bit ALU

32 bits

Shift right Control

Product
Write test

Product register: 64 bits,

64 bits
32 bits (right half: 32 bit
multiplier)

Figure. Final (3rd) version of the multiplication hardware. Compared to the

second version multiplication hardware, the multiplier register is removed and
the Multiplier is placed in the right half of the Product register 74
 Final (3rd) version of multiplication hardware for 32 bit numbers: Initial Conditions

The left half of the Product register, is initialized to

Multiplicand: zero. The right half, of the Product register, is filled
Multiplicand
32 bit number
with the 32 bit multiplier number.
32 bits
32 bits The whole Product register is shifted to the right.
32 bits
The multiplier is also shifted to the right, since it is
placed in the Product register. The test, whether the LSB
of the multiplier, is 1 or 0, is done at the LSB of the Product
register.
ALU: 32 bits
32-bit ALU

32 bits

32 zeros: Shift right

32-bit-number- Control
Product
multiplier is placed
00000 … 00000 Write test

Product register: 64 bits,

64 bits
32 bits (right half: 32 bit
multiplier)

Figure. Final (3rd) version of the multiplication hardware. Compared to the

second version multiplication hardware, the multiplier register is removed and
the Multiplier is placed in the right half of the Product register 75
 Final (3rd) version multiplication: Minimum hardware required,
for multiplying, two, 4-bit numbers
The left half of the Product register, is initialized
Multiplicand: with 4 zeros. The right half, of the Product register,
Multiplicand
4 bit number
is filled with the 4 bit multiplier number.
32 bits
4 bits The whole Product register is shifted to the right.
4 bits
The multiplier is also shifted to the right, since it is
placed in the Product register. The test, whether the LSB
of the multiplier, is 1 or 0, is done at the LSB of the Product
register.
ALU: 4 bits
32-bit ALU

4 bits

Product Register Shift right Control

Product
8 bits Write test

Product
64 bitsregister: 8 bits,
4 bits (right half: 4 bit
multiplier)

Figure. Final (3rd) version multiplication: Minimum hardware required, for

multiplying, two, 4-bit numbers
76
 Final (3rd) version multiplication: Minimum hardware required,
for multiplying, two, 4-bit numbers: 2 x 3 (0010 x 0011
The left half of the Product register, is initialized
Multiplicand:
Multiplicand with 4 zeros. The right half, of the Product register,
0010 is filled with the 4 bit multiplier number.
32 bits
4 bits The whole Product register is shifted to the right.
4 bits
The multiplier is also shifted to the right, since it is
placed in the Product register. The test, whether the LSB
of the multiplier, is 1 or 0, is done at the LSB of the Product
register.
ALU: 4 bits
32-bit ALU
steps

iii y
4 bits

0000
Shift right
Product 0011
Control
add shift
Write test

Product register: 8 bits,

64 bits
4 bits
(right half: 4 bit
multiplier)
Figure. Final (3rd) version multiplication: Minimum hardware required, for
multiplying, two, 4-bit numbers: 2 x 3 (0010 x 0011
77
Improvements to the previous
version of the hardware could be
made
 Before the multiplication starts,
we place the multiplier in the
right half of the product
register. (Only the left half, of
the product register, is used, for
the addition)
78
 As the Product register is shifted
to the right two things happen
 The Product is shifted to the
right, as needed.
 The multiplier is also shifted to
the right. The last bit disappears
and the new bit to be tested is at
location 0.
Product0 takes the place of
Multiplier0. 79
 i
i

The left half of the

Product register is
initialized to zero

80
 Start

Product0 = 1 1. Test Product0 = 0

Product0

1a. Add multiplicand to the left half of

the product and place the re sult in
the left half of the Product register

2. Shift the Product register right 1 bit

No: < 32 repetitions

32nd repetition?

Yes: 32 repetitions

Done

81
Example: using the Final (3rd) version of
algorithm and hardware for multiplication: `
Using 4-bit numbers: 2x3 (0010 x 0011): Initial
values.
Iteration Step Multiplicand Product
1 Initial values 0010 0000 0011
2

82
Example: using the Final (3rd) version of
algorithm and hardware for multiplication: `
Using 4-bit numbers: 2x3 (0010 x 0011): LSB of Product = 1
(new value of left half of product) = multiplicand + (value of left
half of product)
Iteration Step Multiplicand Product
1 Initial values 0010 0000 0011
2 Prod=Prod+Mlcnd >> 0010 0011
Shift right Product >> 0001 0001
3

83
Example: using the Final (3rd) version of
algorithm and hardware for multiplication: `
Using 4-bit numbers: 2x3 (0010 x 0011): LSB of Product = 1
(new value of left half of product) = multiplicand + (value of left
half of product)
Iteration Step Multiplicand Product
1 Initial values 0010 0000 0011
2 Prod=Prod+Mlcnd >> 0010 0011
Shift right Product >> 0001 0001
3 Prod=Prod+Mlcnd >> 0011 0001
Shift right Product >> 0001 1000
4

84
Example: using the Final (3rd) version of
algorithm and hardware for multipliplication: `
Using 4-bit numbers: 2x3 (0010 x 0011): LSB of Product = 0 No
addition  left half of product remains the same

Iteration Step Multiplicand Product

1 Initial values 0010 0000 0011
2 Prod=Prod+Mlcnd >> 0010 0011
Shift right Product >> 0001 0001
3 Prod=Prod+Mlcnd >> 0011 0001
Shift right Product >> 0001 1000
4 0 no Addition >> 0001 1000
Shift right Product >> 0000 1100
5

85
Example: using the Final (3rd) version of
algorithm and hardware for multipliplication: `
Using 4-bit numbers: A x B = 2 x 3 (0010 x 0011)

Iteration Step Multiplicand Product

1 Initial values 0010 0000 0011
2 Prod=Prod+Mlcnd >> 0010 0011
Shift right Product >> 0001 0001
3 Prod=Prod+Mlcnd >> 0011 0001
Shift right Product >> 0001 1000
4 0 no Addition >> >>
Shift right Product >> 0000 1100
5 0  no Addition >> >>
Shift right Product >> 0000 0110
86
 DIVISION

divident
 quotient
divisor
87
 Example (division) in decimal
(using subtraction) 21/7=3, rem 0:
2 1 Divident
- 7 1st subtraction divisor
1 4 1st partial remainder
- 7 2nd subtraction divisor
7 2nd partial remainder
- 7 3rd subtraction of divisor
0 Remainder 88
The sign of the quotient
depends on the sign of the
dividend and the divisor

 If the signs are the same,

the quotient is positive
 If the signs are different,
the quotient is negative
89
When two numbers are divided, both
numbers must be in true
(uncomplemented) form. The basic
steps in a division process are as follows:

Step 1:
Initialize the quotient to zero
Determine what the sign of the
quotient will be (from the signs
of dividend and divisor)
90
 Step 2:
 Subtract the divisor from the
dividend using two's complement
addition, to get the first partial
remainder and add 1 to the quotient.
 If the partial remainder is positive go
to step 3
 If the partial remainder is zero or
negative, the division is complete
(END) 91
 Step 3:
Subtract the divisor from the partial
remainder & add 1 to the quotient
If the result is positive repeat finding
the next partial remainder
If the result is zero or negative, the
division is complete
The quotient is found by counting the
number of times the divisor is
subtracted
92
Example (division) in binary:
Divide the 8 bit signed binary numbers:
0110 0100 (dividend) and 0001 1001 (divisor).
+100/+25

Solution:
0110 0100 (dividend) = 64+32+4 = +100
0001 1001 (divisor) = 16+ 8+1 = + 25
0001 1001 (divisor)  1110 0111
(two's complement of divisor)
93
 Step 1:
•Initialize the quotient to zero.
Quotient = 0000 0000
•The sign of the dividend is 0
and the sign of the divisor is 0
•The sign of the quotient will
be 0 (positive)
94
 Step 2:
• Subtract the divisor from the dividend using
two's complement addition, to get the first partial
remainder
• (remember that final carries are discarded)
bits 7 6 5 4 3 21 0
dividend 01100100
2’s complement of divisor + 11100111
positive 1st partial remainder 1 0 1 0 0 1 0 1 1

Add 1 to the quotient:

0000 0000 + 0000 0001 = 0000 0001 95
 Step 3:
Subtract the divisor from the 1st
partial remainder using two's
complement addition (remember that
final carries are discarded):
bits 7 6 5 4 3 21 0
1st partial remainder 01001011
2’s complement of divisor + 11100111
positive 2ndpartial remainder 1 0 1 0 0 1 0 1 1
Add 1 to the quotient:
0000 0001 + 0000 0001 = 0000 0010 96
 Step 4:
Subtract the divisor from the 2nd partial
remainder using two's complement addition
(remember that final carries are discarded):

bits 7 6 5 4 3 21 0
2ndpartial remainder 00110010
2’s complement of divisor + 11100111
positive 3rdpartial remainder 1 0 0 0 1 1 0 0 1

Add 1 to the quotient:

0000 0010 + 0000 0001 = 0000 0011 97
 Step 5:
Subtract the divisor from the 3rd partial
remainder using two's complement addition
(remember that final carries are discarded):

bits 7 6 5 4 3 21 0
3rd partial remainder 00011001
2’s complement of divisor + 11100111
zero remainder 100000000
Add 1 to the quotient:
0000 0011 + 0000 0001 = 0000 0100 98
The final quotient is 0000 0100, which is +4
 We have reviewed, so far, the basics
of binary division
 The following section will present one
algorithm and hardware that
executes division
 In this section we will assume
that we divide only positive
numbers
99
• Divisor: takes the left (higher) half of Divisor register (Right half is initialized with zero)
• Dividend: takes the right (lower) half of remainder register (Left half is initialized with zero)
• Initialize the quotient to zero.
•Do subtraction: (Remainder register) = (Remainder register) – (Divisor register)
• If the result of subtraction, in the Remainder register, is negative (a) restore previous
remainder (Rem = Rem + Divisor ). Shift Quotient to the left, with a 0
• If the result of subtraction, in the Remainder register, is positive or 0, keep the new result, in
the Remainder register and Shift Quotient to the left, with a 1
• Shift divisor to the right with a 0. Repeat 33 times (as many as the bits of the hardware, + 1)

Divisor register 64 bits

Divisor Shift right

64-bits
64-bits

Quotient
64-bit ALU
Shift left

64-bits Quotient register

32-bits
Remainder register 64 bits Control
Write
Dividend Test

64-bits
100
Figure. 32 bit Division hardware (for two, 32 bit numbers)
• Divisor: takes the left (higher) half of Divisor register. (Right half is initialized with zero)
• Dividend: takes the right (lower) half of remainder register (Left half is initialized with zero)
• Initialize the quotient to zero.
• Do subtraction: (Remainder register) = (Remainder register) – (Divisor register)
• If the result of subtraction, in the Remainder register, is negative (a) restore previous
remainder (Rem = Rem + Divisor ). Shift Quotient to the left, with a 0
• If the result of subtraction, in the Remainder register, is positive or 0, keep the new result, in
the Remainder register and Shift Quotient to the left, with a 1
• Shift divisor to the right with a 0. Repeat 33 times (as many as the bits of the hardware, + 1)
Divisor register 64 bits
Divisor number 32 zeros
32 bits 000000 … right
Shift 000000

64-bits
64-bits

32 zeros
Quotient
64-bit ALU 000000 … 000000
Shift left

Quotient register
64-bits
Remainder register 64 bits 32-bits
Remainder
32 zeros register 64 bits
Dividend number Control
Write
000000 … 000000 Dividend
32 bits Test

64-bits

101
Figure: 32 bit Division hardware (for two, 32 bit numbers), Initial Conditions
• Divisor: takes the left (higher) half of Divisor register. (Right half is initialized with zero)
• Dividend: takes the right (lower) half of remainder register (Left half is initialized with zero)
• Initialize the quotient to zero.
• Do subtraction: (Remainder register) = (Remainder register) – (Divisor register)
• If the result of subtraction, in the Remainder register, is negative (a) restore previous
remainder (Rem = Rem + Divisor ). Shift Quotient to the left, with a 0
• If the result of subtraction, in the Remainder register, is positive or 0, keep the new result, in
the Remainder register and Shift Quotient to the left, with a 1
• Shift divisor to the right with a 0. Repeat 5 times (as many as the bits of the hardware, + 1)
Divisor register 8bits
Divisor number 4 zeros
4 bits 0000right
Shift

8-bits
8-bits

4 zeros
Quotient
8-bit ALU 0000
Shift left

8-bits Quotient register

Remainder register 8bits 4-bits
Remainder
4 zeros register 64 bits
Dividend number Control
Write
0000 Dividend
4 bits Test

8-bits

102
Figure: Minimum Division hardware required for two, 4 bit numbers and Initial Conditions
• Divisor: takes the left (higher) half of Divisor register. (Right half is initialized with zero)
• Dividend: takes the right (lower) half of remainder register (Left half is initialized with zero)
• Initialize the quotient to zero.
• Do subtraction: (Remainder register) = (Remainder register) – (Divisor register)
• If the result of subtraction, in the Remainder register, is negative (a) restore previous
remainder (Rem = Rem + Divisor ). Shift Quotient to the left, with a 0
• If the result of subtraction, in the Remainder register, is positive or 0, keep the new result, in
the Remainder register and Shift Quotient to the left, with a 1
• Shift divisor to the right with a 0. Repeat 5 times (as many as the bits of the hardware, + 1)
Divisor register 8bits
Divisor number 4 zeros
0010 0000
Shift right

8-bits
8-bits

4 zeros
Quotient
8-bit ALU 0000
Shift left

8-bits Quotient register

Remainder register 8bits
4-bits

4 zeros register
Remainder 64 bits
Dividend number Control
0000 0111 Write
Dividend Test

8-bits
103
Figure: Example: Dividend / Divisor, 7/2, 0111 / 0010, Minimum Division hardware required for two, 4
bit numbers and Initial Conditions
 Start

Subtract the Divisor register from

the Remainder register and place
the result in the Remainder register

Test Remainder >= 0 Test Remainder <0

Test Remainder

Restore the original value by adding the

Divisor register to the Remainder
Shift the Quotient register to the left, register and place the sum in the
Remainder register
setting the new rightmost bit to 1
- Also shift the Quotient register to the
left, setting the new least significant bit
to 0

Shift the Divisor register right 1 bit

33rd No: <33 repetitions

repetition

Yes: 33 repetiitons

Done
104
Example: using the first version of
algorithm and hardware for DIVISION:
Assume 4-bit numbers. +7 and +2
Divide the signed binary numbers:
7 = 0111 (is the dividend)
2 = 0010 (is the divisor)
7/2 = 3 (is the quotient) and 1 is the remainder

divident 7
 quotient   3 remainder1
divisor 2
105
 Solution:
0111 (dividend) = +7  Dividend takes the
lower half of the 8-bit remainder register
Remainder register = Dividend=0000 0111

0010 (divisor) = +2  Divisor takes the

higher half of the 8-bit Divisor register
Divisor register = 0010 0000

Initialize the quotient to zero. 0000

106
1. Remainder = Remainder - Divisor 
with SLT (set less than instruction)
2. If Rem is +ve or 0, Shift Quotient
left and set the rightmost bit to 1

3. If Rem is –ve (a) restore previous

remainder (Rem = Rem + Divisor )

Shift Quotient left and set the

rightmost bit to 0 107
4. Shift Divisor right
5. (if not the n repetition
th

go to step 1)
n = (number of quotient
bits)+1

108
 Assume 4-bit numbers and minimum hardware required (therefore do 5
subtractions, 4+1 =5): dividend / divisor, Example: 7/2 = 3 remainder 1, 0111 /
0010 = 0011 remainder 0001,
Solution : Initial values (initial conditions)

Iteration Step Divisor Remainder Quotient

(Dividend)
2 s lamp
0 Initial values 0010 0000 0000 0111 0000
1 11100111

0000111 0000

0001000 1 11
2
11110111

9 00000111 0000

00001000 s
109
Iteration Step Divisor Remainder Quotient
(Dividend)
3 9
11111111
9 000
0000111

soon olee as a
4
a 0000 All a

0000000 a 0001

Poll 110