21EC71 Advanced VLSI

Advanced VLSI
(21EC71)
SEMESTER – VII

Education in itself is an asset, Not an investment.

Module 1
Introduction to ASICs: Full custom, Semi-custom and Programmable ASICs, ASIC
Design flow, ASIC cell libraries. CMOS Logic: Data path Logic Cells: Data Path
Elements, Adders: Carry skip, Carry bypass, Carry save, Carry select, Conditional
sum, Multiplier (Booth encoding), Data path Operators, I/O cells, Cell Compilers.

Textbook 1

Vijaykumar Sajjanar

[email protected],

vjkr.github.io

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21EC71 Advanced VLSI

CONTENTS
Introduction to ASICs ............................................................................................................................................................................ 3
Types of ASICs .......................................................................................................................................................................................... 4
Full-Custom ASICs .............................................................................................................................................................................. 4
SEMI CUSTOM ASICS......................................................................................................................................................................... 5
Standard-Cell Based ASICs ........................................................................................................................................................ 5
GATE ARRAY BASED ASICS ....................................................................................................................................................... 7
programmable asics .......................................................................................................................................................................... 8
Programmable Logic Devices ................................................................................................................................................... 8
Field-Programmable Gate Arrays ............................................................................................................................................... 9
Design Flow............................................................................................................................................................................................. 10
ASIC Cell Libraries........................................................................................................................................................................... 11
CMOS LOGIC CELLS ............................................................................................................................................................................. 13
Datapath Logic Cells ....................................................................................................................................................................... 13
Datapath Elements .......................................................................................................................................................................... 14
adders .............................................................................................................................................................................................. 16
Multipliers ..................................................................................................................................................................................... 19
Other Datapath Operators ........................................................................................................................................................... 20
IO Cells.................................................................................................................................................................................................. 21
Cell Compilers ........................................................................................................................................................................................ 22

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21EC71 Advanced VLSI

INTRODUCTION TO ASICS
An ASIC is an application-specific integrated circuit. Figure 1.0(a) shows an IC
package (this is a pin-grid array, or PGA, shown upside down; the pins will go through holes
in a printed-circuit board). A PGA package is usually made from a ceramic material, but
plastic packages are also common.

FIGURE 1.0 An integrated circuit (IC). (a) A pin-grid array (PGA) package. (b)
The silicon die or chip is under the package lid.

 The earliest ICs used bipolar technology and the majority of logic ICs used either
transistor transistor logic ( TTL ) or emitter-coupled logic (ECL).
 Although invented before the bipolar transistor, the metal-oxide-silicon (MOS) transistor
was initially difficult to manufacture because of problems with the oxide interface.
 By the early 1980s the aluminum gates of the transistors were replaced by polysilicon
gates.
 The introduction of polysilicon as a gate material was a major improvement in CMOS
technology
 The principal advantage of CMOS over NMOS techniology is lower power consumption.
 Another advantage of a polysilicon gate was a simplification of the fabrication process,
allowing devices to be scaled down in size.
 As different types of custom ICs began to evolve for different types of applications, these
new ICs gave rise to a new term:application-specific IC, or ASIC.

Examples of ICs that are ASICs include: Examples of ICs that are not ASICs include
standard parts such as:
1. a chip for a toy bear that talks;
2. a chip for a satellite; 1. memory chips sold as a commodity
3. a chip designed to handle the item ROMs,
interface between memory and a 2. DRAM, and SRAM;
microprocessor for a workstation 3. microprocessors;
CPU; 4. TTL or TTL-equivalent ICs at SSI,
4. a chip containing a microprocessor MSI, and LSI levels.
as a cell together with other logic.

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TYPES OF ASICS
ICs are made on a thin (a few hundred microns thick), circular silicon wafer , with
each wafer holding hundreds of die (sometimes people use dies or dice for the plural of die).

The transistors and wiring are made from many layers (usually between 10 and 15
distinct layers) built on top of one another. Each successive mask layer has a pattern that is
defined using a mask similar to a glass photographic slide. The first half-dozen or so layers
define the transistors. The last half-dozen or so layers define the metal wires between the
transistors (the interconnect).

ASICs

Full Custom Semi Custom Programmable

ASICs ASICs ASICs

Programmable Field
Standard Cell Gate Array Programmable
Logic Devices
based ASICs based ASICs Gate Arrays
(PLDs)
(FPGAs)

Programmable
Channeled
Array Logic
gate arrays
(PALs)

Programmable
Channelless
Logic Array
gate arrays.
(PLAs)

Structured
gate arrays.

Figure 1.1: Types of ASICs

FULL-CUSTOM ASICS
 In a full-custom ASIC an engineer designs some or all of the logic cells, circuits, or
layout specifically for one ASIC.
 This means the designer abandons the approach of using pretested and precharacterized
cells for all or part of that design.
 It makes sense to take this approach only if there are no suitable existing cell libraries
available that can be used for the entire design. This might be because existing cell
libraries are not fast enough, or the logic cells are not small enough or consume too
much power.
 There is one growing member of this family, the mixed analog/digital ASIC.

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21EC71 Advanced VLSI

SEMI CUSTOM ASICS

STANDARD-CELL BASED ASICS
 A cell-based ASIC (cell-based IC, or CBIC a common term in Japan) uses predesigned
logic cells (AND gates, OR gates, multiplexers, and flip-flops, for example) known as
standard cells.
 The standard-cell areas (also called flexible blocks) in a CBIC are built of rows of
standard cells like a wall built of bricks.
 The standard-cell areas may be used in combination with larger predesigned cells,
perhaps microcontrollers or even microprocessors, known as megacells .
 Megacells are also called megafunctions, full-custom blocks, system-level macros
(SLMs), fixed blocks, cores, or Functional Standard Blocks (FSBs).
 The ASIC designer defines only the placement of the standard cells and the interconnect
in a CBIC.
 However, the standard cells can be placed anywhere on the silicon; this means that all
the mask layers of a CBIC are customized and are unique to a particular customer.
 The advantage of CBICs is that designers save time, money, and reduce risk by using a
predesigned, pretested, and precharacterized standard-cell library . In addition each
standard cell can be optimized individually. During the design of the cell library each
and every transistor in every standard cell can be chosen to maximize speed or minimize
area, for example.
 The disadvantages are the time or expense of designing or buying the standard-cell
library and the time needed to fabricate all layers of the ASIC for each new design.

FIGURE 1.2: A cell-based ASIC (CBIC) die with a single standard-cell area (a flexible
block) together with four fixed blocks. The flexible block contains rows of standard
cells.

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FIGURE 1.3 Standard cells are stacked like bricks in a wall; the abutment box (AB)
defines the edges of the brick. The difference between the bounding box (BB) and the
AB is the area of overlap between the bricks. Power supplies (labeled VDD and GND)
run horizontally inside a standard cell on a metal layer that lies above the transistor
layers. This standard cell has center connectors (the three squares, labeled A1, B1, and
Z) that allow the cell to connect to others.

FIGURE 1.4 Routing the CBIC (cell-based IC). The use of regularly shaped standard
cells, from a library allows ASICs like this to be designed automatically. This ASIC
uses two separate layers of metal interconnect (metal1 and metal2) running at right
angles to each other.

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21EC71 Advanced VLSI

GATE ARRAY BASED ASICS

 Both cell-based and gate-array ASICs use predefined cells, but there is a difference we
can change the transistor sizes in a standard cell to optimize speed and performance, but
the device sizes in a gate array are fixed.
 This results in a trade-off in performance and area in a gate array at the silicon level.
 Only the top few layers of metal, which define the interconnect between transistors, are
defined by the designer using custom masks.
 To distinguish this type of gate array from other types of gate array, it is often called a
masked gate array ( MGA ).
 The smallest element that is replicated to make the base array is the base cell (sometimes
called a primitive cell ).
 The logic cells in a gate-array library are often called macros .

There are the following different types of MGA or gate-arraybased ASICs:

● Channeled gate arrays.

● Channelless gate arrays.
● Structured gate arrays.

FIGURE 1.5 A channeled gate- FIGURE 1.6 A channelless gate-array or

array die. The spaces between rows sea-of-gates (SOG) array die. The core
of the base cells are set aside for area of the die is completely filled with an
interconnect. array of base cells (the base array).

FIGURE 1.7 A structured or embedded gate-array die showing an embedded block

in the upper left corner (a static random-access memory, for example). The rest of
the die is filled with an array of base cells.

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21EC71 Advanced VLSI

PROGRAMMABLE ASICS
PROGRAMMABLE LOGIC DEVICES
 Programmable logic devices ( PLDs ) are standard ICs that are available in standard
configurations from a catalog of parts and are sold in very high volume to many
different customers.
 However, PLDs may be configured or programmed to create a part customized to a
specific application, and so they also belong to the family of ASICs.
 No customized mask layers or logic cells • Fast design turnaround

FIGURE 1.8 A programmable logic device (PLD) die. The macrocells typically
consist of programmable array logic followed by a flip-flop or latch.The macrocells
are connected using a large programmable interconnect block.

 The simplest type of programmable IC is a read-only memory ( ROM ). The most common
types of ROM use a metal fuse that can be blown permanently (a programmable ROM or
PROM ).
 An electrically programmable ROM , or EPROM , uses programmable MOS transistors
whose characteristics are altered by applying a high voltage. You can erase an EPROM
either by using another high voltage (an electrically erasable PROM , or EEPROM ) or
by exposing the device to ultraviolet light ( UV-erasable PROM , or UVPROM ).
 There is another type of ROM that can be placed on any ASIC a mask-programmable
ROM (mask-programmed ROM or masked ROM). A masked ROM is a regular array of
transistors permanently programmed using custom mask patterns. An embedded
masked ROM is thus a large, specialized, logic cell.

 a PLA has a programmable AND logic array, or AND plane , followed by a

programmable OR logic array, or OR plane ;
 a PAL has a programmable AND plane and, a fixed OR plane.

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21EC71 Advanced VLSI

FIELD-PROGRAMMABLE GATE ARRAYS

 FPGA is usually just larger and more complex than a PLD.
● None of the mask layers are customized.
● A method for programming the basic logic cells and the interconnect.
● The core is a regular array of programmable basic logic cells that can implement
combinational as well as sequential logic (flip-flops).
● A matrix of programmable interconnect surrounds the basic logic cells.
● Programmable I/O cells surround the core.
● Design turnaround is a few hours.

FIGURE 1.9 A field-programmable gate array (FPGA) die. The exact type, size, and number of the
programmable basic logic cells varies tremendously

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21EC71 Advanced VLSI

DESIGN FLOW
Figure 1.10 shows the sequence of steps to design an ASIC; we call this a design flow.

FIGURE 1.10 ASIC design flow

1. Design entry. Enter the design into an ASIC design system, either using a hardware
description language ( HDL ) or schematic entry .
2. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool to
produce a netlist a description of the logic cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and blocks.
8. Extraction. Determine the resistance and capacitance of the interconnect.
9. Postlayout simulation. Check to see the design still works with the added loads of the
interconnect.

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21EC71 Advanced VLSI

ASIC CELL LIBRARIES

The cell library is the key part of ASIC design. You have three choices: the ASIC vendor (the
company that will build your ASIC) will supply a cell library, or you can buy a cell library
from a third-party library vendor , or you can build your own cell library.

 The first choice, using The second and third choices The third choice is to
an ASIC-vendor library, require you to make a buy-or- develop a cell library in-
requires you to use a set build decision . house.
of design tools approved  If you complete an ASIC  Many large computer and
by the ASIC vendor to design using a cell library electronics companies make
enter and simulate your that you bought, you also this choice.
design. own the masks (the  Most of the cell libraries
 You have to buy the tooling) that are used to designed today are still
tools, and the cost of the manufacture your ASIC. developed in-house
cell library is folded into This is called customer- despite the fact that the
the NRE. owned tooling (COT). process of library
 A library vendor normally development is complex
develops a cell library and very expensive
using information about a
process supplied by an
ASIC foundry .

However created, each cell in an ASIC cell library must contain the following:

A physical
layout
A
A routing
behavioral
model
model

A wire- A
load Verilog/VHDL
model ASIC Cell model
library
A detailed
A cell
timing
icon
model

A circuit A test
schematic strategy

1. The ASIC designer may not actually see the layout if it is hidden inside a phantom, but the
layout will be needed eventually.
2. The ASIC designer needs a high-level, behavioral model for each cell because simulation
at the detailed timing level takes too long for a complete ASIC design.
3. The designer may require Verilog and VHDL models in addition to the models for a
particular logic simulator.

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21EC71 Advanced VLSI

4. ASIC designers also need a detailed timing model for each cell to determine the
performance of the critical pieces of an ASIC. Library engineers simulate the delay of
each cell, a process known as characterization.
5. All ASICs need to be production tested (programmable ASICs may be tested by the
manufacturer before they are customized, but they still need to be tested). Simple cells in
small or medium-size blocks can be tested using automated techniques, but large blocks
such as RAM or multipliers need a planned strategy.
6. The cell schematic (a netlist description) describes each cell so that the cell designer can
perform simulation for complex cells.
7. A cell icon helps in identifying the library cell.
8. In order to estimate the parasitic capacitance of wires before we actually complete any
routing, we need a statistical estimate of the capacitance for a net in a given size circuit
block. This usually takes the form of a look-up table known as a wire-load model .
9. We also need a routing model for each cell. Large cells are too complex for the physical
design or layout tools to handle directly and we need a simpler representation. The
phantom may include information that tells the automated routing tool where it can and
cannot place wires over the cell, as well as the location and types of the connections to
the cell.
LIB files (.lib)

LEF files (.lef)

Netlist file (.v )

GDS file (.gds)

SPICE Netlist (.sp)

Model file (.m)

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21EC71 Advanced VLSI

CMOS LOGIC CELLS

Type of Combinational Sequential Datapath I/O Cells
Cells Logic Cells Logic Cells Logic Cells
Description Perform operations Store data and Optimized for Manage
where the output control timing, arithmetic and communication
depends only on with outputs logical between the internal
logic of the chip and
current inputs, depending on operations, used
the external
without memory. both current in high-speed environment.
and previous datapaths to
states. reduce delay.
Examples AND Gate, D Flip-Flop, Carry Look- Input Buffer Cell,
Multiplexer (MUX), Shift Register, Ahead Adder Output Driver Cell,
Ripple Carry Adder Counter (CLA), Booth Bi-Directional I/O
Cell, ESD Protection
(RCA) Multiplier, Barrel
Cell
Shifter

DATAPATH LOGIC CELLS

Suppose we wish to build an n -bit adder (that adds two n -bit numbers) and to exploit
the regularity of this function in the layout. We can do so using a datapath structure.

FIGURE 2.20 A datapath adder.

(a) A full-adder (FA) cell with inputs (b) A 4-bit adder. (c) The layout, using two-level
metal, with data in m1 and control in m2. (d) The datapath layout.
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21EC71 Advanced VLSI

What is the difference between using a datapath, standard cells, or gate arrays? Cells
are placed together in rows on a CBIC or an MGA, but there is no generally no regularity to
the arrangement of the cells within the rows we let software arrange the cells and complete
the interconnect.

Datapath layout automatically takes care of most of the interconnect between the cells
with the following advantages:

● Regular layout produces predictable and equal delay for each bit.

● Interconnect between cells can be built into each cell.

There are some disadvantages of using a datapath:

● The overhead (buffering and routing the control signals, for example) can make a
narrow (small number of bits) datapath larger and slower than a standard-cell (or even gate-
array) implementation.

● Datapath cells have to be predesigned (otherwise we are using full-custom design) for
use in a wide range of datapath sizes. Datapath cell design can be harder than designing
gate-array macros or standard cells.

● Software to assemble a datapath is more complex and not as widely used as software
for assembling standard cells or gate arrays.

DATAPATH ELEMENTS
Figure 2.21 shows some typical datapath symbols for an adder.

FIGURE 2.21 Symbols for a datapath adder.

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21EC71 Advanced VLSI

TABLE 2.11 Binary arithmetic & representation

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ADDERS

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FIGURE 2.22 The carry-save adder (CSA). (a) A CSA cell. (b) A 4-bit CSA. (c)Symbol fora
CSA. (d) A four-input CSA. (e) The datapath for a four-input, 4-bit adder using CSAs with a
ripple-carry adder (RCA) as the final stage. (f) A pipelined adder. (g) The datapath for the
pipelined version showing the pipeline registers as well as the clock control lines that use m2

FIGURE 2.24 The conditional-sum adder. (a) A 1-bit conditional adder that calculates the sum
and carry out assuming the carry in is either '1' or '0'. (b) The multiplexer that selects between
sums and carries. (c) A 4-bit conditional-sum adder with carry input, C[0].

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21EC71 Advanced VLSI

FIGURE 2.23 The Brent Kung carry-lookahead adder (CLA). (a) Carry generation in
4-bit CLA. (b) A cell to generate the lookahead terms, C[0] C[3]. (c) Cells L1, L2, an
L3 are rearranged into a tree that has less delay. Cell L4 is added to calculate C[2] that
is lost in the translation. (d) and (e) Simplified representations of parts a and c. (f) The
lookahead logic for an 8-bit adder. The inputs, 0:7, are the propagate and carry terms
formed from the inputs to the adder. (g) An 8-bit Brent Kung CLA. The outputs
of the lookahead logic are the carry bits that (together with the inputs) form the sum.
One advantage of this adder is that delays from the inputs to the outputs are more
nearly equal than in other adders. This tends to reduce the number of unwanted and
unnecessary switching events and thus reduces power dissipation.

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21EC71 Advanced VLSI

MULTIPLIERS
There are two items we can attack to improve the performance of a multiplier: the
number of partial products and the addition of the partial products. Booth encoding reduces
the number o partial products by a factor of two and thus considerably reduces the area as
well as increasing the speed of our multiplier

Booth Encoding

The above multiplier architecture can be divided into two stages. In the first stage the Partial
Products are formed by the Booth encoder and Partial Product Generator(PPG). In the second
stage the partial products obtained in the above are merged to form the results.

 Andrew Donald Booth proposed Booth's multiplication algorithm which can perform the
multiplication operation of Two Signed Binary numbers in their respective 2's complement
form.
RADIX-2 BOOTH RECODING

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Table 2: Example of Booth’s Radix-2 multiplication

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OTHER DATAPATH OPERATORS

The combinational datapath cells, NAND, NOR, and so on, and sequential datapath
cells (flip-flops and latches) have standard-cell equivalents and function identically.

FIGURE 2.31 Symbols for datapath elements. (a) An array or vector of flip-flops (a
register). (b) A two-input NAND cell with databus inputs. (c) A two-input NAND cell with a
control input. (d) A buswide MUX. (e) An incrementer/decrementer. (f) An all-zeros
detector. (g) An all-ones detector. (h) An adder/subtracter.

 We can build a ripple-borrow subtracter (a type of borrow-propagate subtracter), a

borrow-save subtracter, and a borrow-select subtracter in the same way we built
these adder architectures.
 A barrel shifter rotates or shifts an input bus by a specified amount. For example if
we have an eight-input barrel shifter with input '1111 0000' and we specify a shift of
'0001 0000' (3, coded by bit position) the right-shifted 8-bit output is '0001 1110'. A
barrel shifter may rotate left or right (or switch between the two under a separate
control).
 A leading-one detector is used with a normalizing (left-shift) barrel shifter to align
mantissas in floating-point numbers.
 The output of a priority encoder is the binary-encoded position of the leading one in
an input.
 An accumulator is an adder/subtracter and a register. Sometimes these are combined
with a multiplier to form a multiplier accumulator ( MAC ). An incrementer adds 1 to
the input bus, Z = A + 1, so we can use this function, together with a register, to
negate a two s complement number for example.

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IO CELLS

FIGURE 2.32 A three-state bidirectional output buffer. When the output enable,
OE, is '1' the output section is enabled and drives the I/O pad. When OE is '0' the output
buffer is placed in a high-impedance state.

 Figure 2.33 shows a three-state bidirectional output buffer (Tri-State ® is a

registered trademark of National Semiconductor).When the output enable (OE) signal
is high, the circuit functions as a noninverting buffer driving the value of DATAin
onto the I/O pad. When OE is low, the output transistors or drivers , M1 and M2, are
disconnected. This allows multiple drivers to be connected on a bus. It is up to the
designer to make sure that a bus never has two drivers a problem known as
contention .In order to prevent the problem opposite to contention a bus floating to an
intermediate voltage when there are no bus drivers we can use a bus keeper or bus-
hold cell (TI calls this Bus-Friendly logic).
 Large currents and voltages at I/O pads because of inductances and capacitances
cause power-supply bounce. To avoid this, we can limit the number of simultaneously
switching outputs (SSOs), we can limit the number of I/O drivers that can be attached
to any one VDD and GND pad, and we can design the output buffer to limit the slew
rate of the output (we call these slew-rate limited I/O pads). Quiet-I/O cells also use
two separate power supplies and two sets of I/O drivers: an AC supply (clean or quiet
supply) with small AC drivers for the I/O circuits that start and stop the output
slewing at the beginning and end of a output transition, and a DC supply (noisy or
dirty supply) for the transistors that handle large currents as they slew the output.
 To protect the I/O cells from electrostatic discharge ESD, the input pads are
normally tied to device structures that clamp the input voltage to below the gate
breakdown voltage. Some I/O cells use transistors with a special ESD implant that
increases breakdown voltage and provides protection.

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CELL COMPILERS
The process of hand crafting circuits and layout for a full-custom IC is a tedious,
time-consuming, and error-prone task.

There are two types of automated layout assembly tools, often known as a silicon
compilers.

1. The first type produces a specific kind of circuit, a RAM compiler or multiplier
compiler , for example.
2. The second type of compiler is more flexible, usually providing a
programming language that assembles or tiles layout from an input command
file, but this is full-custom IC design.

In addition to producing layout we also need a model compiler so that we can verify the
circuit at the behavioral level, and we need a netlist from a netlist compiler so that we can
simulate the circuit and verify that it works correctly at the structural level. Silicon compilers
are thus complex pieces of software.

End of Module 1 Notes

Best of Luck

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