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Veriloh HDL Sa-2

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5 views

Veriloh HDL Sa-2

Uploaded by

roghithjaya
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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NAME: NAVEEN A

REGISTER NO: 212223060183


SUBJECT NAME: VERILOG HDL
SUBJECT SLOT: 4L4-2
ASSIGNMENT: SKILL ASSESSMENT-2
TOPIC: N-BIT MULTIPLIER USING VERILOG CODE

ABSRTACT:
An n-bit multiplier is a digital circuit designed to
multiply two binary numbers, each consisting of n bits.
It takes two inputs, A and B, each of size n-bits, and
produces an output that is a product of the two numbers,
typically 2n-bits in length. The primary operation
involves a series of bitwise AND operations, followed
by shifts and additions to accumulate the partial
products. Common methods for constructing an n-bit
multiplier include the array multiplier, booth multiplier,
and wallace tree multiplier, each offering trade-offs in
terms of speed, area, and power consumption. The
multiplier is an essential component in various digital
systems, such as microprocessors, digital signal
processors (DSPs), and cryptographic systems, where
efficient and accurate multiplication is crucial. This
paper explores the design, optimization techniques, and
performance evaluation of n-bit multipliers, addressing
their implementation challenges and offering insights
into their use in high-performance computing
applications.
CODE:
module multiplier(
out, a_in, b_in, clk, start, reset, finish, bcd);
parameter N = 8;
output[(((N*2)/3)+1)*4-1:0] bcd;
output[(N*2)-1:0] out;
output finish;
input start;
input clk;
input reset;
input [N-1:0] a_in;
input [N-1:0] b_in;
reg[(((N*2)/3)+1)*4-1:0] bcd_reg = 0;
reg[(N*2)-1:0] out_reg;
reg finish_reg = 0;
reg [(N*2)-1:0] a_in_reg;
reg [(N*2)-1:0] b_in_reg;
reg [8:0] bits;
assign bcd = bcd_reg;
assign out = out_reg;
assign finish = finish_reg;
integer i, j;
always @(negedge reset)
begin
out_reg = 0;
a_in_reg = 0;
b_in_reg = 0;
end
always @(posedge clk)
begin
if(!reset)
begin
case(start)
1'b0: begin
a_in_reg = a_in;
b_in_reg = b_in;
bits = N;
finish_reg = 0;
out_reg = 0;
bcd_reg = 0;
$display("Values loaded into the input register!");
end
1'b1: begin
if(b_in_reg[0]==1)
begin
out_reg = out_reg + a_in_reg;
end
bits = bits - 1;
a_in_reg = a_in_reg<<1;
b_in_reg = b_in_reg>>1;
end
endcase
if(bits==0)
begin
$display("Multiplication completed!");
finish_reg = 1'b1;
for(i=0;i<(N*2);i=i+1)
begin
if (3 <= (((N*2)/3)+1)*4-1 &&
bcd_reg[3:0] >= 5) bcd_reg[3:0] = bcd_reg[3:0] + 3;

if (7 <= (((N*2)/3)+1)*4-1 &&


bcd_reg[7:4] >= 5) bcd_reg[7:4] = bcd_reg[7:4] + 3;
if (11 <= (((N*2)/3)+1)*4-1 &&
bcd_reg[11:8] >= 5) bcd_reg[11:8] = bcd_reg[11:8] +
3;
if (15 <= (((N*2)/3)+1)*4-1 &&
bcd_reg[15:12] >= 5) bcd_reg[15:12] = bcd_reg[15:12]
+ 3;
if (19 <= (((N*2)/3)+1)*4-1 &&
bcd_reg[19:16] >= 5) bcd_reg[19:13] = bcd_reg[19:13]
+ 3;
bcd_reg = {bcd_reg[(((N*2)/3)+1)*4-
2:0],out_reg[(N*2)-1-i]};
end
$display("Conversion of binary to BCD completed!");
end
end
end
endmodule
TESTBENCH CODE:
module multiplier_tb;
parameter n_bits = 5;
reg [n_bits-1:0] a_in;
reg [n_bits-1:0] b_in;
reg clk;
reg start;
reg reset;
wire [(n_bits*2)-1:0] out;
wire finish;
wire [(((n_bits*2)/3)+1)*4-1:0] bcd;
multiplier uut (
.out(out),
.a_in(a_in),
.b_in(b_in),
.clk(clk),
.start(start),
.reset(reset),
.finish(finish),
.bcd(bcd)
);
defparam uut.N = n_bits;
initial
begin
forever
#50 clk= ~clk;
end
initial begin
a_in = 0;
b_in = 0;
clk = 0;
start = 0;
reset = 1;
reset = 0;
a_in = 'd26;
b_in = 'd30;
start = 0;
#200
start = 1;
#(100*n_bits)
a_in = 'd13;
b_in = 'd13;
start = 0;
#200
start = 1;
#(100*n_bits)
$finish;
end
endmodule
FLOW CHAT:
OUTPUT:

TESTBENCH OUTPUT:

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