Design of a Software Defined, FPGA-Based

Reconfigurable RF Measuring Receiver

Matthew T. Hunter Achilleas G. Kourtellis Wasfy B. Mikhael
DME Corporation DME Corporation University of Central Florida
12889 Ingenuity Drive 12889 Ingenuity Drive 4000 Central Florida Blvd.
Orlando, Florida 32826 Orlando, Florida 32826 Orlando, Florida 32816
Email: [email protected] Email: [email protected] Email: [email protected]

Abstract—Digital Signal Processing (DSP) plays a central role

in the implementation of software-defined, Synthetic Instruments
(SI) [1]–[5]. Moving as many signal processing tasks as possible
from the analog to the digital domain makes for a more flexible,
future-proof system. Advances in DSP can also be exploited to
reduce the complexity of, or remove completely, the analog com-
ponents. In this work, the design of a high performance FPGA-
Based Radio Frequency (RF) Measuring Receiver is described. It
is shown how advanced DSP can be used to synthesize multiple
measurements from a single source on a compact, software
defined platform.

I. I NTRODUCTION
As the role of DSP in instrumentation continues to increase, Fig. 1. Synthetic Instrument Concept
the meaning of certain terminology can be expanded. For ex-
ample, when one familiar with the field of RF instrumentation
thinks of an “RF Measuring Receiver”, the Hewlett-Packard newer software implementations, e.g. [8], may take minutes
(HP) 8902 [6] immediately comes to mind, thus defining depending on the settings. An alternative approach is to insert
the term “RF Measuring Receiver”. The HP8902 represented a real-time processing element in the signal path such as a
a monumental achievement for its time, providing multiple Field Programmable Gate Array (FPGA). In this manner, the
RF measurements on a single hardware-defined platform. computational load may be partitioned to maximize the speed
Today’s RF Measuring Receiver can provide the function of and memory efficiency of a particular measurement.
the HP8902 in addition to many more measurements on a
smaller, software-defined platform as shown in Fig. 1. In this paper it is shown how DSP can be used to mimic
analog signal processing without the associated drawbacks.
One approach to the design of an RF Software Defined
The design and implementation of a flexible DSP system for
Instrument (SDI) is given in [7]. In this approach, RF in-
a high performance RF Measuring Receiver is described. At
put signals are first conditioned and shifted to a suitable
the heart of the system is the flexible Digital Down Con-
Intermediate Frequency (IF) for digitization. The digitized
verter (DDC) which provides virtually any analysis bandwidth
IF samples are then stored in memory before being trans-
desired from 100 Hz to 8 MHz. Practical implementation
ferred to a General Purpose Processor (GPP) or computer
issues are highlighted including the role of FPGAs in real-
for offline processing. This approach greatly increases the
time systems. The details of a real implementation of an FPGA
flexibility of the instrumentation since the actual measurement
based DDC are given along with measured results. Finally, the
functions are implemented as software algorithms. In addition
overall proposed RF Measuring Receiver is described showing
to this, multiple measurement functions may be performed
how multiple measurements can be derived from a single
on a single data set. This eliminates the need for multiple
source on a compact FPGA-based platform.
discrete hardware functions to perform each measurement.
The drawback to this approach is the speed of measurement This paper is organized as follows. Section II provides
penalty incurred in offline processing. This decrease in speed a high level overview of Software Defined Instrumentation
can be quite dramatic. For example, the HP8902 performs (SDI). The software defined receiver is the subject of Section
modulation measurements in fractions of a second, however, III. Section IV discusses the reconfigurable DDC. An FPGA
implementation of the reconfigurable DDC is presented in
This work was supported by DME Corporation’s funding of the Univer- Section V followed by measured results in Section VI. The
sity of Central Florida Research project entitled Advanced Digital Signal
Processing for Synthetic Instrumentation. DME Corporation is an Astronics overall measuring receiver is described in Section VII. Finally,
Company. Section VIII concludes the paper.

978-1-4244-4981-1/09/$25.00 ©2009 IEEE

 II. S OFTWARE D EFINED I NSTRUMENTATION (SDI)
Software Defined, or Synthetic Instrumentation (SI) [1], [2],
[4], [5], [9]–[12] and Software Defined Radio (SDR) [13]–[16]
have many common goals. One of the main goals of SDR is to
replace as many of the analog and hard-wired digital circuits Fig. 3. Software Defined Receiver
as possible with programmable devices. This makes a radio
(any wireless communication device, e.g. cell phone, walkie-
talkie) more flexible in the sense that it can be reconfigured signal processing with DSP are minimization or elimination
to handle a different type of communication waveform simply of calibration, flexibility/reconfigurability, future proofing, and
by changing its programming. This concept is illustrated in increased accuracy and repeatability.
Fig. 2 where the single SDR on the right can handle all of the
III. S OFTWARE D EFINED R ECEIVER
waveforms produced by the multiple hardware defined radios
on the left. As illustrated in Fig. 3, the first step in the analysis of RF
input signals is analog signal conditioning. The main task of
this signal conditioning is to translate the RF input spectrum
to a suitable Intermediate Frequency (IF) and power level for
Analog to Digital Conversion (ADC). This is shown in Fig. 4.

Fig. 2. Software Defined Radio Concept

Fig. 4. Analog Signal Processing
The SI movement takes the same approach in that it seeks to
use flexible DSP based architectures to provide many functions Next, the IF input Spectrum is translated to Base Band (BB)
on a single platform. Multiple measurement functions can be and channel/analysis bandwidth selection is performed. This
synthesized from a limited set of “generic” SI components operation provides a filtered, alias-free signal bandwidth ready
as opposed to discrete instrument types such as a spectrum for further analysis. Figure 5 demonstrates the selection of a
analyzer [17]. This concept is shown in Fig. 1, where the particular bandwidth for anlysis.
SI platform on the right performs the same functions as the
discrete instruments on the left. In the figure, the example SI
platform consists of a monitor for display on top of a card
cage housing the generic SI components. Examples of generic
SI components include the frequency downconverter, digitizer,
and ARBitrary waveform generator (ARB).
The differences between SDR and SI are quite small in the
area of RF and communications instrumentation, such as the
Vector Signal Analyzer (VSA) and Vector Signal Generator
(VSG). In fact, a SI receiver can be thought of as a gold
standard SDR receiver [1]. Hence, advances in SDR can be Fig. 5. Tune and Zoom
taken advantage of in the development of new SI’s and vice-
versa. In both areas, DSP plays a prominent role. The tune and zoom function in Fig. 5 is performed by the
A generic software defined receiver which could be found digital down converter as described in the next section.
in either a SDR or SDI is given in Fig. 3. The primary
concern of the SDR is to recover information from the RF IV. R ECONFIGURABLE D IGITAL D OWN C ONVERTER
input signal. On the other hand, the primary concern of the New communications waveforms are constantly in develop-
SDI is to analyze the RF input signal which includes the ment leading to an endless supply of ever changing channel
recovery of information. The next section further details the bandwidths, symbol rates, and signals to analyze in general.
software defined receiver. In both cases the role of DSP is This creates the need for reconfigurable analysis and measure-
maximized. Some of the main benefits of replacing analog ment systems. In particular, how can a DDC be designed to
support a virtually infinite supply of analysis bandwidths and
symbol rates? A pictorial representation of the spectra for this
requirement is given in Fig. 6.

Fig. 9. Flexible Digital Down Converter

analysis of a similar structure may be found in [4]. This

Fig. 6. Spectral Interpretation of DDC approach sounds good in theory, but is it practical? If so, what
type of implementation platform is best? Answering these
In Fig. 6, R(f ) is the input to the DDC, Z(f ) is the complex questions is the subject of the next section.
envelope of R(f ), and S(f ) is the desired analysis bandwidth
of B Hz. Many approaches can be taken to achieve the desired V. FPGA D ESIGN AND I MPLEMENTATION
operation. The brute force approach is depicted in Fig. 7. While a computer may provide the most flexible and easily
reconfigurable signal processing platform, it is not suited for
real-time, high bandwidth (MHz) applications. As commu-
nication data rates and bandwidths continue to increase, the
need for reconfigurable, real-time signal processing becomes
apparent. The FPGA provides the ideal platform for this need.
Today’s FPGAs are capable of high speed (100s of MHz) real-
time parallel processing that may be reconfigured on the fly.
Fig. 7. Brute Force Analog Approach
High performance DSP specific cores are being produced by
manufacturers reducing design time. Several abstraction tools
This method uses an adjustable ADC sample clock along for DSP system designers are also available further speeding
with selectable bandwidth filters to meet the requirement. and easing development. These tools not only allow design
Unfortunately, as the number of analysis bandwidths to support and simulation in a MATLAB environment, but are capable
grows this approach becomes impractical. Another approach of producing efficient, portable, deployable firmware.
retains the adjustable sample clock, but employs multi-rate We now proceed with the design details of the DDC. From
filtering to provide the selectable analysis bandwidths. This Fig. 9, the complex exponential is readily implemented in an
type of system is depicted in Fig. 8. FPGA via Direct Digital Synthesis (DDS). DDS can provide
µHz tuning resolution from DC to Nyquist with Spurious Free
Dynamic Range (SFDR) in excess of 100 dB. The arbitrary
bandwidth filter of Fig. 9 has a bandwidth proportional to
its output sample rate. Thus, to provide continuously variable
bandwidth, the sample rate must also be continuously variable.
This can be achieved by operating on the input signal with
samples computed from a continuous time filter without any
Fig. 8. Combined Multirate Approach explicit digital-to-analog or analog-to-digital conversion [18].
For SDR and SI applications, the continuous time filter
The multi-rate filter is shown as the block with the down should allow for fast, on-line computation of impulse response
arrow and label M . M is the integer decimation factor such samples, frequency domain design, and computational effi-
that the output sample rate of the filter is the input sample ciency. Polynomial-Based Filters (PBF) provide these charac-
rate divided by M . This provides a bandwidth proportional to teristics and are readily implemented in FPGAs. In addition,
the input sample rate divided by an integer. The fine tuning of PBFs provide resampling by arbitrary factors, linear phase, and
the bandwidth and sample rate is accomplished by adjusting support virtually any bandwidth with arbitrary resolution. An
the ADC sample clock. The drawback to this approach is example DDC design employing a DDS and PBF with ADC
the requirement of an adjustable sample clock which requires sample rate of 122.88 MHz is given in Fig. 10. Particularly
more hardware and cost than a fixed frequency oscillator. suited for the DDC is the Transposed Modified Farrow Struc-
Maximizing the use of DSP leads to the flexible DDC given in ture (TMFS), a PBF implementation structure designed for
Fig. 9. This structure supports any analysis/channel bandwidth sample rate reduction [4], [19], [20]. This structure is shown
to the system maximum, while requiring the minimum amount in Fig. 11.
of analog hardware. The complex output of the DDS is mixed with the input
In particular, no tunable/selectable sample clock or bank of signal, translating it to baseband. The filter following the mixer
selectable analog filters are required. More detailed theoretical provides a fixed decimation by 6 reducing the computational
 Fig. 10. DDC Example Design

specific FPGA implementation is given. A fractional interval

generator is necessary to perform the resampling operation
with the TMFS, the details may be found in [4]. The design
of this was done in Xilinx System Generator, and is shown in
Fig. 13, which highlights the level of abstraction now available
to DSP system designers.

Fig. 11. Transposed Modified Farrow Structure

complexity required by the PBF, Ha (f ). This design supports

virtually any alias-free analysis bandwidth, B, from 100 Hz
to 8 MHz. The PBF frequency response is shown in Fig. 12,
where it can clearly be seen that the attenuation requirement
given in Fig. 10 is met.

Fig. 13. FPGA Example Design

VI. DDC M EASURED R ESULTS

In this section, measured results from a real implementation
of the system in Fig. 10 are given. The test setup for the
measurements is depicted in Fig. 14.

Fig. 12. PBF Frequency Response

Before concluding this section a small example of the Fig. 14. Measurement Test Setup
 operating in parallel are given in Fig. 17. The figure shows
the Graphical User Interface (GUI) of one of DME’s Next
Generation Synthetic Instrumentation Architectures (NGSIA).
Shown on the display are an RF receiver control panel, a
spectrum analyzer, Received Signal Strength Indicator (RSSI),
frequency counter/error meter, constellation diagram, and error
vector magnitude meter. While it is outside the scope of
this paper to describe in detail how each instrument was
constructed, the main purpose is to show how multiple virtual
instruments can be simultaneously synthesized via DSP.

VIII. C ONCLUSION
In this paper the main concepts and similarities of SDR and
(a) 1 MHz Bandwidth SDI were covered. It was shown how DSP can be employed
to construct a flexible software defined measuring receiver.
In particular, the design of a reconfigurable Digital Down
Converter (DDC) was presented along with an FPGA imple-
mentation. Finally, measured results were given demonstrating
the performance of the design.

R EFERENCES
[1] R. W. Lowdermilk and F. J. Harris, “Vector signal analyzer implemented
as a synthetic instrument,” in Proceedings of the IEEE Systems Readiness
Technology Conference, 2007. AUTOTESTCON 2007., Baltimore, MD,
Sep. 2007, pp. 157–166.
[2] ——, “Signal conditioning and data collection in synthetic instruments,”
in Proceedings of the IEEE Systems Readiness Technology Conference,
2003. AUTOTESTCON 2003., Anaheim, CA, Sep. 2003, pp. 426–431.
[3] H. Howard and F. Cruger, “Re-configurable hardware for synthetic
wideband instruments,” in AUTOTESTCON Proceedings, 2001. IEEE
Systems Readiness Technology Conference, Valley Forge, PA, Aug. 2001,
pp. 632 – 647.
(b) 233 kHz Bandwidth [4] M. T. Hunter, W. B. Mikhael, and A. G. Kourtellis, “Wideband digital
downconverters for synthetic instrumentation,” IEEE Transactions on
Fig. 15. Measured Results Instrumentation and Measurement, vol. 58, no. 2, pp. 263–269, Feb.
2009.
[5] M. T. Hunter, W. B. Mikhael, and T. Tocco, “Arbitrary waveform
generators for synthetic instrumentation,” in Proceedings of the IEEE
The DDC implementation was deployed on one of DME Systems Readiness Technology Conference, 2008. AUTOTESTCON ’08.,
Corporation’s next generation synthetic instruments. A spec- Salt Lake City, UT, Sep. 2008, pp. 138–143.
trum analyzer Virtual Instrument was used to collect data and [6] “Hp8902a specifications,” Agilent. [Online]. Available:
http://www.home.agilent.com/upload/cmc upload/All/EPSG085826.pdf
perform a max hold measurement while the external signal [7] J. Murrill, “Rf synthetic instrumentation used to support ew test capa-
generator swept the frequency spectrum. Thus the filter shape bility,” in AUTOTESTCON, 2008 IEEE, Sept. 2008, pp. 144–147.
could be traced. Two example bandwidths are shown in Fig. [8] “Agilent n5531s,” Agilent, May 2009. [Online]. Available:
http://cp.literature.agilent.com/litweb/pdf/5989-9217EN.pdf
15, where it is clear that the real implementation achieves the [9] M. T. Hunter, W. B. Mikhael, and A. G. Kourtellis, “Direct if synthesis of
designed performance. vector modulated signals using real-time signal processing,” in Proceed-
ings of the 2008 IEEE International Instrumentation and Measurement
VII. FPGA-BASED RF M EASURING R ECEIVER Technology Conference, 2008. I2MTC 2008., Victoria, Vancouver Island,
Canada, May 2008, pp. 1853–1858.
The overall block diagram of the proposed software defined, [10] ——, “Flexible, high performance, fixed sample clock signal synthesis,”
IEEE Transactions on Instrumentation and Measurement, 2009, submit-
FPGA-based reconfigurable RF measuring receiver is shown ted for publication.
in Fig. 16. At the heart of the system is the flexible DDC [11] M. Hunter, “Efficient fft-based spectral analysis using polynomial-based
providing µHz tuning resolution and continuously variable filters for next generation test systems,” in Proceedings of the IEEE
Systems Readiness Technology Conference, 2007. AUTOTESTCON ’07.,
analysis bandwidths from 100 Hz to 8 MHz. As can be Baltimore, MD, Sep. 2007, pp. 677–686.
seen from the figure, multiple software reconfigurable instru- [12] M. Hunter and W. Mikhael, “Fixed sample clock fpga-based arbitrary
ments/measurements are available from a single source. These waveform generator,” U.S. patent application, 2008.
[13] M. Sadiku and C. Akujuobi, “Software-defined radio: a brief overview,”
measurements include some found in the HP 8902 in addition IEEE Potentials, vol. 23, pp. 14–15, oct-nov 2004.
to many other instruments/measurements found in spectrum [14] P. Burns, Software Defined Radio for 3G, ser. Mobile Communications.
and vector signal analyzers. Artech House, 2003.
[15] J. Mitola, Software Radio Architecture. Wiley-Interscience, 2000.
This architecture was implemented and tested as in Fig. [16] P. B. Kenington, RF and Baseband Techniques for Software Defined
14. Measured results of multiple measurements/instruments Radio, ser. Mobile Communications. Artech House, 2005.
 Fig. 16. Software Defined, FPGA-Based Reconfigurable RF Measuring Receiver

Fig. 17. Multiple Virtual Instruments in Parallel

[17] P. Pragrastis, I. Sihra, and M. N. Granieri, “Synthetic instrumentation: [19] D. Babic, T. Saramki, and M. Renfors, “Prolonged transposed polyno-
Contemporary architectures and applications (part ii),” RF DESIGN, pp. mial based filters for decimation,” in Int. Symp. Circuits and Systems,
12–19, Nov. 2004. vol. 4, May 2003, pp. 317–320.
[18] F. M. Gardner, “Interpolation in digital modems - part i: Fundamentals,” [20] D. Babic, J. Vesma, T. Saramki, and M. Renfors, “Implementation of the
IEEE Transactions on Communications, vol. 41, pp. 501–507, Mar. transposed farrow structure,” in Int. Symp. Circuits and Systems, vol. 4,
1993. May 2002, pp. 5–8.