SR Flip – Flop:

module srff (
input clk, rst, s, r,
output reg qn, qnbar,
output q
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
qn <= 1'b0; qnbar <= 1'b1; end
else
case ({s, r})
2'b00: begin qn <= q; qnbar <= ~q; end
2'b01: begin qn <=1'b0; qnbar <= 1'b1; end
2'b10: begin qn <= 1'b1; qnbar <= 1'b0; end
2'b11: begin qn <= 1'b x; qnbar <= 1'b x; end
endcase
end
endmodule
SR Flip – Flop (Asynchronous):
module srff (
input clk, pre, clr, s, r,
output reg qn, qnbar,
output q
);
always @ (posedge clk, pre, clr)
begin
if (pre == 1'b0 && clr == 1'b0)
begin qn <= q; qnbar <= ~q; end
else if (pre == 1'b0 && clr == 1'b1)
begin qn <=1'b1; qnbar <= 1'b0; end
else if (pre == 1'b1 && clr == 1'b0)
 begin qn <=1'b0; qnbar <= 1'b1; end
else if (pre == 1'b1 && clr == 1'b1)
case ({s, r})
2'b00: begin qn <= q; qnbar <= ~q; end
2'b01: begin qn <=1'b0; qnbar <= 1'b1; end
2'b10: begin qn <= 1'b1; qnbar <= 1'b0; end
2'b11: begin qn <= 1'b x; qnbar <= 1'b x; end
endcase
end
endmodule

JK Flip – Flop:
module jkff (
input clk, rst, j, k,
output reg qn, qnbar,
output q
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
qn <= 1'b0; qnbar <= 1'b1; end
else
case ({j, k})
2'b00: begin qn <= q; qnbar <= ~q; end
2'b01: begin qn <=1'b0; qnbar <= 1'b1; end
2'b10: begin qn <= 1'b1; qnbar <= 1'b0; end
2'b11: begin qn <= 1'b x; qnbar <= 1'b x; end
endcase
end
endmodule
JK Flip – Flop (Asynchronous):
module jkff (
input clk, pre, clr, k, j,
output reg qn, qnbar,
output q
);
always @ (posedge clk, pre, clr)
begin
if (pre == 1'b0 && clr == 1'b0)
begin qn <= q; qnbar <= ~q; end
else if (pre == 1'b0 && clr == 1'b1)
begin qn <=1'b1; qnbar <= 1'b0; end
else if (pre == 1'b1 && clr == 1'b0)
begin qn <=1'b0; qnbar <= 1'b1; end
else if (pre == 1'b1 && clr == 1'b1)
case ({j, k})
2'b00: begin qn <= q; qnbar <= ~q; end
2'b01: begin qn <=1'b0; qnbar <= 1'b1; end
2'b10: begin qn <= 1'b1; qnbar <= 1'b0; end
2'b11: begin qn <= 1'b x; qnbar <= 1'b x; end
endcase
end
endmodule

D Flip – Flop:
module dff (
input clk, rst, d,
output reg qn, qnbar,
output q
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
 begin
qn <= 1'b0; qnbar <= 1'b1; end
else
case (d)
1'b0: begin qn <= q; qnbar <= ~q; end
1'b1: begin qn <=d; qnbar <= ~d; end
endcase
end
endmodule
D Flip – Flop (Asynchronous):
module dff (
input clk, pre, clr, d,
output reg qn, qnbar,
output q
);
always @ (posedge clk, pre, clr)
begin
if (pre == 1'b0 && clr == 1'b0)
begin qn <= q; qnbar <= ~q; end
else if (pre == 1'b0 && clr == 1'b1)
begin qn <=1'b1; qnbar <= 1'b0; end
else if (pre == 1'b1 && clr == 1'b0)
begin qn <=1'b0; qnbar <= 1'b1; end
else if (pre == 1'b1 && clr == 1'b1)
case (d)
1'b0: begin qn <= q; qnbar <= ~q; end
1'b1: begin qn <=d; qnbar <= ~d; end
endcase
end
endmodule
T Flip – Flop:
module tff (
input clk, rst, t,
output reg qn, qnbar,
output q
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
qn <= 1'b0; qnbar <= 1'b1; end
else
case (t)
1'b0: begin qn <= q; qnbar <= ~q; end
1'b0: begin qn <= ~q; qnbar <= q; end
endcase
end
endmodule
T Flip – Flop (Asynchronous):
module tff (
input clk, pre, clr, t,
output reg qn, qnbar,
output q
);
always @ (posedge clk, pre, clr)
begin
if (pre == 1'b0 && clr == 1'b0)
begin qn <= q; qnbar <= ~q; end
else if (pre == 1'b0 && clr == 1'b1)
begin qn <=1'b1; qnbar <= 1'b0; end
else if (pre == 1'b1 && clr == 1'b0)
begin qn <=1'b0; qnbar <= 1'b1; end
else if (pre == 1'b1 && clr == 1'b1)
 case (t)
1'b0: begin qn <= q; qnbar <= ~q; end
1'b0: begin qn <= ~q; qnbar <= q; end
endcase
end
endmodule
Counters:
UP Counter:
2- bit counter:
module counter2bit (
input rst, clk,
output reg [1:0] count
);
always @ (posedge clk or posedge rst)
begin
if (rst) count <= 2'b00;
else
count <= count + 1'b1;
end
endmodule
3- bit counter:
module counter3bit (
input rst, clk,
output reg [2:0] count
);
always @ (posedge clk or posedge rst)
begin
if (rst) count <= 3'b000;
else
count <= count + 1'b1;
end
endmodule
4- bit counter:
module counter4bit (
input rst, clk,
output reg [3:0] count
);
always @ (posedge clk or posedge rst)
begin
if (rst) count <= 4'b0000;
else
count <= count + 1'b1;
end
endmodule
DOWN Counter:
2- bit counter:
module counter2bit (
input rst, clk,
output reg [1:0] count
);
always @ (posedge clk or posedge rst)
begin
if (rst) count <= 2'b11;
else
count <= count - 1'b1;
end
endmodule
3- bit counter:
module counter3bit (
input rst, clk,
output reg [2:0] count
);
always @ (posedge clk or posedge rst)
begin
 if (rst) count <= 3'b111;
else
count <= count - 1'b1;
end
endmodule
4- bit counter:
module counter4bit (
input rst, clk,
output reg [3:0] count
);
always @ (posedge clk or posedge rst)
begin
if (rst) count <= 4'b1111;
else
count <= count - 1'b1;
end
endmodule
Decade counter:
module decade_counter (
input rst, clk,
output reg [3:0] count
);
always @ (posedge clk or posedge rst)
begin
if (rst) count <= 4'b0000;
else
if (count == 9) count <= 4'b0000;
else
count <= count + 1'b1;
end
endmodule
Mod- 12 counter:
module counter2bit (
input rst, clk,
output reg [3:0] count
);
always @(posedge clk or posedge rst)
begin

if (rst) count <= 4'b0000;

else
if (count == 11) count <= 4'b0000;
else
count <= count + 1'b1;
end
endmodule
Mod- 6 counter:
module mod6counter(
input rst,clk,
output reg [2:0] count
);
always @(posedge clk or posedge rst)
begin
if (rst) count <= 3'b000
else
if(count == 5) count <= 3'b000;
else
count <= count + 1'b1;
end
endmodule
Ring counter:
module ringcounter (
input rst, clk,
output reg [3:0] q
);
always @(posedge clk or posedge rst)
begin
if(rst == 1'b1) q <= 4'b0001;
else q <= {q[0], q[3:1]};
end
endmodule
Johnson counter:
module johnsoncounter (
input rst, clk,
output reg [3:0] q
);
always @(posedge clk or posedge rst)
begin
if(rst == 1'b1) q <= 4'b0000;
else q <= {(~q[0]), q[3:1]};
end
endmodule

Shift Registers:
SISO:
Left Shift:
module siso (
input rst, clk, sin,
output reg [3:0] q,
output reg sout);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1) q <= 4'b0000;
else q <= {q[2:0],sin};// left shift
sout <= q[3];
end
endmodule
Right Shift:
module siso (
input rst, clk, sin,
output reg [3:0] q,
output reg sout);
always @ (posedge clk or posedge rst)

begin
if (rst == 1'b1) q <= 4'b0000;
else q <= {sin, q[3:1]};// right shift
sout <= q[0];
end
endmodule

SIPO:
module sipo (
input rst, clk, sin,
output reg [3:0] q,
output reg [3:0] pout
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
q <= 4'b0000;
pout <= 4'b0000;
end
else
q <= {sin, q [3:1] };
pout <= q;
end
endmodule
PISO:
module piso (
input rst, clk, load,
input [3:0] pin,
output reg [3:0] q,
output reg sout
);
always @ (posedge clk or posedge rst)

begin
if (rst == 1'b1) q <= 4'b0000;
else
if (load)
q <= pin;
else
q <= {1'b0, q [3:1]};
sout <= q [0];
end
endmodule
PIPO:
module pipo (
input rst, clk,
input [3:0] pin,
output reg [3:0] pout
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
pout <= 4'b0000;
else
pout <= pin;
end
endmodule
Bi – Directional Shift Register:
// shift_ctrl = 1 right shift
// shift_ctrl = 0 left shift
module bidirectional_shift_reg (
input rst, clk, sin, shift_ctrl,
output reg [3:0] q,
output reg sout);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1) q <= 4'b0000;
else
if(shift_ctrl)
begin q <= {sin, q [3:1] };// right shift
sout <= q [0];
end
else
begin
q <= {q [2:0], sin};// right shift
sout <= q [3];
end
end
endmodule

Universal Shift Register:

// shift_ctrl = 00 HOLD
// shift_ctrl = 01 LEFT SHIFT
// shift_ctrl = 10 right shift
// shift_ctrl = 11 PIPO
module usr (
 input rst, clk, sin,
input [1:0] shift_ctrl,
input [3:0] pin,
output reg [3:0] q,
//output reg [3:0] dout,
output reg sout);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
q <= 4'b0000;
else
case (shift_ctrl)
2'b00: q <= q;
2'b01: begin q <= {q[2:0], sin}; sout <= q[3]; end
2'b10: begin q <= {sin, q [3:1]}; sout <= q [0]; end
2'b11: q <= pin;
endcase
end
endmodule