ISOUSB211

SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

ISOUSB211 High/Full/Low Speed Isolated USB Repeater

1 Features 3 Description
• Compliant to USB 2.0 ISOUSB211 is a galvanically-isolated USB 2.0
• Supports low speed (1.5 Mbps), full speed (12 compliant repeater supporting low speed (1.5
Mbps) and high speed (480 Mbps) signaling Mbps), full speed (12 Mbps) and high speed
• Does not need external crystal or clock input (480 Mbps) signaling rates. The device supports
• Automatic speed and connection detection automatic connect and speed detection, reflection
• Supports L1 (sleep) and L2 (suspend) low-power of pull-ups/pull-downs, and link power management
states allowing drop-in USB hub, host, peripheral and
• Programmable equalization to compensate board cable isolation. The device also supports automatic
trace loss in high speed mode role reversal - if after disconnect, a new connect
• CDP advertising on downstream side is detected on the Upstream facing port, then
• Supply OK indication on opposite side the Upstream and Downstream port definitions
• Supports automatic role reversal for USB On-The- are reversed. This feature enables the device to
Go (OTG) and Type-C® Dual Role Port (DRP) support USB On-The-Go (OTG) and Type-C Dual
designs Role Port (DRP) implementations. The ISOUSB211
• High CMTI: 100 kV/µs has inbuilt programmable equalization to cancel
• ±8 kV IEC 61000-4-2 contact discharge protection signal loss caused by board traces, which helps in
across isolation barrier meeting USB2.0 high-speed TX and RX eye-diagram
• VBUS voltage range: 4.25 V to 5.5 V templates. This device uses a silicon dioxide (SiO2)
– 3.3 V and 1.8 V internal LDOs insulation barrier with a withstand voltage of up to
• Meets CISPR32 class B emissions limits 5000 VRMS and a working voltage of 1500 VRMS. Used
• Ambient temperature range: –40°C to +125°C in conjunction with isolated power supplies, the device
• Small footprint 28-SSOP package protects against high voltage, and prevents noise
• Safety-related certifications: currents from the bus from entering the local ground.
– 7071-VPK VIOTM and 2121-VPK VIORM The ISOUSB211 device is available for reinforced
(Reinforced) per DIN EN IEC 60747-17 (VDE isolation. It supports a wide ambient temperature
0884-17) range of –40°C to +125°C. The device is available in
– 5000-VRMS isolation for 1 minute per UL 1577 the small foot-print SSOP-28 (28-DP) package.
– IEC 62368-1, IEC 60601-1 and IEC 61010-1 Device Information
certifications PART NUMBER(1) PACKAGE BODY SIZE (NOM)
– CQC, TUV and CSA certifications
ISOUSB211 SSOP (28) DP 10.30 mm × 7.50 mm
2 Applications
(1) For all available packages, see the orderable addendum at
• USB Hub, Host, Peripheral and Cable Isolation the end of the data sheet.
• Medical
• Factory automation Upstream
ISOUSB211
3.3 V (local supply)
Port
• Motor drives Connector
V3P3V2
• Grid infrastructure VBUS1 VBUS2 VCC
• Power delivery UD+ DD+ Peripheral
DP
• USB Audio USB
HOST DD- DM
MCU
UD-

Reinforced Isolation Option GND1 GND2 GND

FEATURE ISOUSB211
Galvanic
PERIPHERAL
Protection Level Reinforced Isolation Barrier

Surge Isolation Voltage 12800 VPK

Application Diagram
Isolation Rating 5000 VRMS
1500 VRMS /
Isolation Working Voltage
2121 VPK

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

Table of Contents
1 Features............................................................................1 8.1 Overview................................................................... 22
2 Applications..................................................................... 1 8.2 Functional Block Diagram......................................... 22
3 Description.......................................................................1 8.3 Feature Description...................................................23
4 Revision History.............................................................. 2 8.4 Device Functional Modes..........................................26
5 Pin Configuration and Functions...................................3 9 Power Supply Recommendations................................27
6 Specifications.................................................................. 5 10 Application and Implementation................................ 28
6.1 Absolute Maximum Ratings........................................ 5 10.1 Typical Application.................................................. 28
6.2 ESD Ratings............................................................... 5 10.2 Meeting USB2.0 HS Eye-Diagram Specifications...32
6.3 Recommended Operating Conditions.........................5 10.3 Thermal Considerations..........................................33
6.4 Thermal Information....................................................6 11 Layout........................................................................... 37
6.5 Power Ratings.............................................................6 11.1 Layout Guidelines................................................... 37
6.6 Insulation Specifications............................................. 7 12 Device and Documentation Support..........................39
6.7 Safety-Related Certifications...................................... 8 12.1 Documentation Support.......................................... 39
6.8 Safety Limiting Values.................................................8 12.2 Receiving Notification of Documentation Updates..39
6.9 Electrical Characteristics.............................................9 12.3 Support Resources................................................. 39
6.10 Switching Characteristics........................................14 12.4 Trademarks............................................................. 39
6.11 Insulation Characteristics Curves............................18 12.5 Electrostatic Discharge Caution..............................39
6.12 Typical Characteristics............................................ 19 12.6 Glossary..................................................................39
7 Parameter Measurement Information.......................... 20 13 Mechanical, Packaging, and Orderable
7.1 Test Circuits.............................................................. 20 Information.................................................................... 39
8 Detailed Description......................................................22 13.1 Tape and Reel Information......................................43

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (September 2022) to Revision C (January 2023) Page

• Removed "Basic" option from data sheet........................................................................................................... 1

Changes from Revision A (March 2022) to Revision B (September 2022) Page

• Updated device status to Production Data......................................................................................................... 1

Changes from Revision * (November 2021) to Revision A (March 2022) Page

• TA Max value updated to 125°C......................................................................................................................... 5
• Updated Thermal Considerations section.........................................................................................................33

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

5 Pin Configuration and Functions

V 1 28 V
BUS1 BUS2

V 2 27 V
3P3V1 3P3V2

GND1 3 26 GND2

V 4 25 V
1P8V1 1P8V2

V 5 24 V
CC1 CC2

V2OK 6 23 V1OK

ISOLATION
UD- 7 22 DD-

UD+ 8 21 DD+

EQ10 9 20 EQ20

EQ11 10 19 EQ21

V 11 18 V
1P8V1 1P8V2

GND1 12 17 GND2

CDPENZ1 13 16 CDPENZ2

NC 14 15 NC

Not to scale

Figure 5-1. DP Package 28-Pin SSOP Top View

Table 5-1. Pin Functions—28 Pins

PIN
I/O DESCRIPTION
NO. NAME
Input Power Supply for Side 1. If a 4.25 V to 5.5 V (example USB power bus) supply is available
1 VBUS1 — connect it to VBUS1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and V3P3V1 to
an external 3.3 V power supply.
Power Supply for Side 1. If a 4.25 V to 5.5 V supply is connected to VBUS1 connect a bypass capacitor
2 V3P3V1 — between V3P3V1 and GND1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and
V3P3V1 to an external 3.3 V power supply.
3 GND1 — Ground 1. Ground reference for Isolator Side 1.
Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC1 connect a bypass capacitor
4 V1P8V1 — between V1P8V1 and GND1. In this case an internal LDO generates V1P8V1. Else, connect VCC1 and
V1P8V1 to an external 1.8 V power supply.
Input Power Supply for Side 1. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived
5 VCC1 — from USB power bus) supply is available connect it to VCC1. In this case an internal LDO generates
V1P8V1. Else, connect VCC1 and V1P8V1 to an external 1.8 V power supply.
6 V2OK O High level on this pin indicates that side 2 is powered up.
7 UD- I/O Upstream facing port D-.
8 UD+ I/O Upstream facing port D+.
9 EQ10 I Equalization setting for Side 1, LSB. Logic Input.
10 EQ11 I Equalization setting for Side 1, MSB. Logic Input.
11 V1P8V1 — Connect pin 11 to pin 4, with local bypass capacitors near pin 11.
12 GND1 — Ground 1. Ground reference for Isolator Side 1.
13 CDPENZ1 I Active low singal. Enables CDP advertising on UD+/UD- pins.
14 NC — Leave floating or connect to V3P3V1.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

Table 5-1. Pin Functions—28 Pins (continued)

PIN
I/O DESCRIPTION
NO. NAME
15 NC — Leave floating or connect to V3P3V2.
16 CDPENZ2 I Active low singal. Enables CDP advertising on DD+/DD- pins.
17 GND2 — Ground 2. Ground reference for Isolator Side 2.
18 V1P8V2 — Connect pin 18 to pin 25, with local bypass capacitors near pin 18.
19 EQ21 I Equalization setting for Side 2, MSB. Logic Input.
20 EQ20 I Equalization setting for Side 2, LSB. Logic Input.
21 DD+ I/O Downstream facing port D+.
22 DD- I/O Downstream facing port D-.
23 V1OK O High level on this pin indicates that side 1 is powered up.
Input Power Supply for Side 2. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived
24 VCC2 — from USB power bus) supply is available connect it to VCC2. In this case an internal LDO generates
V1P8V2. Else, connect VCC2 and V1P8V2 to an external 1.8 V power supply.
Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC2 connect a bypass capacitor
25 V1P8V2 — between V1P8V2 and GND2. In this case an internal LDO generates V1P8V2. Else, connect VCC2 and
V1P8V2 to an external 1.8 V power supply.
26 GND2 — Ground 2. Ground reference for Isolator Side 2.
Power Supply for Side 2. If a 4.25 V to 5.5 V supply is connected to VBUS2 connect a bypass capacitor
27 V3P3V2 — between V3P3V2 and GND1. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and
V3P3V2 to an external 3.3 V power supply.
Input Power Supply for Side 2. If a 4.25 V to 5.5 V (example USB power bus) supply is available
28 VBUS2 — connect it to VBUS2. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and V3P3V2 to
an external 3.3 V power supply.

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VBUS1, VBUS2 VBUS supply voltage -0.3 6 V
VCC1, VCC2 VCC supply voltage -0.3 6 V
V3P3V1, V3P3V2 3.3-V input supply voltage –0.3 4.25 V
V1P8V1, V1P8V2 1.8-V input supply voltage –0.3 2.1 V
Voltage on bus pins (UD+, UD-, DD+, DD-) 1000 total number of
VDPDM –0.3 6 V
short events and cummulative duration of 1000 hrs.
VIO IO voltage range (V*OK, EQ*, CDPENZ*) –0.3 V3P3Vx+0.3(3) V
IO Output current on output pins (V*OK) -10 10 mA
TJ Junction temperature 150 °C
TSTG Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 4.25 V

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
V(ESD) Electrostatic discharge ±1500 V
JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC
V(ESD) Electrostatic discharge ±500 V
specification JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VBUSx VBUS input voltage (inclusive of any ripple) 4.25 5 5.5 V
V3P3Vx 3.3-V input supply voltage (inclusive of any ripple) 3.0 3.3 3.6 V
VCCx Input voltage to internal 1.8V LDO (inclusive of any ripple) 2.4 3 5.5 V
V1P8Vx 1.8-V input supply voltage (inclusive of any ripple) 1.71 1.8 1.94 V
TA Operating free-air temperature –40 125 °C
TJ Junction temperature –55 150 °C

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

6.4 Thermal Information

ISOUSB211
THERMAL METRIC(1) DP (SSOP) UNIT
28 PINS
RΘJA Junction-to-ambient thermal resistance 44.2 °C/W
RΘJC(top) Junction-to-case (top) thermal resistance 13.9 °C/W
RΘJB Junction-to-board thermal resistance 19.0 °C/W
ψJT Junction-to-top characterization parameter 3.3 °C/W
ψJB Junction-to-board characterization parameter 18.4 °C/W
RΘJC(bot) Junction-to-case (bottom) thermal resistance - °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISOUSB211
VBUS1 = VBUS2 = VCC1 = VCC2 = 5.5 V,
TJ = 150°C, RL = 50 Ω each on DD-
PD Maximum power dissipation (both sides) and DD+ to GNDx, input a 240-MHz 50% 1232 mW
duty cycle adifferential 0 to 400mV swing
signal on UD- and UD+
VBUS1 = VBUS2 = VCC1 = VCC2 = 5.5 V,
TJ = 150°C, RL = 50 Ω each on DD-
PD1 Maximum power dissipation (side-1) and DD+ to GNDx, input a 240-MHz 50% 616 mW
duty cycle adifferential 0 to 400mV swing
signal on UD- and UD+
VBUS1 = VBUS2 = VCC1 = VCC2 = 5.5 V,
TJ = 150°C, RL = 50 Ω each on DD-
PD2 Maximum power dissipation (side-2) and DD+ to GNDx, input a 240-MHz 50% 616 mW
duty cycle adifferential 0 to 400mV swing
signal on UD- and UD+

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

6.6 Insulation Specifications

SPECIFIC
PARAMETER TEST CONDITIONS ATIONS UNIT
DP-28
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air >8 mm
CPG External Creepage(1) Side 1 to side 2 distance across package surface >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 V
Material Group According to IEC 60664-1 I
Rated mains voltage ≤ 600 VRMS I-IV
Overvoltage category
Rated mains voltage ≤ 1000 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
AC voltage (sine wave); time-dependent dielectric
1500 VRMS
VIOWM Maximum isolation working voltage breakdown (TDDB) test;
DC voltage 2121 VDC
VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t
VIOTM Maximum transient isolation voltage 8000 VPK
= 1 s (100% production)
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-us waveform per IEC 62368-1 8000 VPK
Tested in oil (qualification test), 1.2/50-μs waveform per IEC
VIOSM Maximum surge isolation voltage(3) 12800 VPK
62368-1
Method a, After Input/Output safety test subgroup 2/3,Vini =
≤5
VIOTM, tini = 60 s;Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,Vini =
≤5
VIOTM, tini = 60 s;Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd Apparent charge(4) Method b: At routine test (100% production) and pC
preconditioning (type test);
Vini = 1.2 x VIOTM, tini = 1 s;
≤5
Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)

CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 pft), f = 1 MHz 1.2 pF
VIO = 500 V, TA = 25°C > 1012
RIO Insulation resistance, input to output(5) VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011 W
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t
VISO Withstand isolation voltage 5700 VRMS
= 1 s (100% production)

(1) Care must be taken during board design so that the mounting pads of the isolator on the printed-circuit board (PCB) do not reduce
creepage and clearance. Inserting grooves, ribs or both can help increase creepage distance on the PCB.
(2) ISOUSB211 is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

6.7 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to DIN Certified according to IEC Recognized under
Certified according to GB Certified according to EN
EN IEC 60747-17 (VDE 61010-1, IEC 62368-1 and UL 1577 Component
4943.1 61010-1 and EN 62368-1
0884-17) IEC 60601-1 Recognition Program
Reinforced insulation per
Reinforced Insulation; CSA 62368-1 and IEC
Maximum transient 62368-1 5000 VRMS Reinforced
isolation voltage, ISOUSB211: 800 VRMS insulation per EN 61010-1
ISOUSB211: 8000 VPK Maximum working voltage up to working voltage
Reinforced insulation,
Maximum repetitive peak (pollution degree 2, of 600 VRMS
Single protection, Altitude ≤ 5000 m, Tropical
isolation voltage, 2121 material group I); ----------------
ISOUSB211: 5700 VRMS Climate,
VPK; ISOUSB211: 2 MOPP 5000 VRMS Reinforced
700 VRMS maximum
Maximum surge isolation ---------------- insulation per EN 62368-1
working voltage
voltage, (Means of Patient up to working voltage of
ISOUSB211: 12800 VPK Protection) per CSA 800 VRMS
(Reinforced) 60601-1 and IEC 60601-1,
250 VRMS maximum
working voltage
Certificate number:
Certificate:
40040142 Master contract: 220991 File number: E181974 Client ID: 77311
CQC15001121716

6.8 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DP-28 PACKAGE
RθJA = 44.2°C/W, VI = 5.5 V, TJ = 150°C,
514 mA
TA = 25°C
RθJA = 44.2°C/W, VI = 3.6 V, TJ = 150°C,
IS Safety input, output, or supply current 785 mA
TA = 25°C
RθJA = 44.2°C/W, VI = 1.94 V, TJ = 150°C,
1457 mA
TA = 25°C
PS Safety input, output, or total power RθJA = 44.2°C/W, TJ = 150°C, TA = 25°C 2828 mW
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

6.9 Electrical Characteristics

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CHARACTERISTICS
Receive side HS Active (240 MHz
signal rate), EQxx = 00, RL = 45 Ω to 10.5 13.5 mA
ground on D+ and D-
VBUS or V3P3V current consumption - Transmit side HS Active (240 MHz
IVBUSx or IV3P3Vx
High Speed (HS) mode signal rate), EQxx = 00, RL= 45 Ω to 10.5 13.5 mA
ground on D+ and D-
HS Idle State, EQxx = 00, RL = 45 Ω to
10.5 13.5 mA
ground on D+ and D-
Receive side FS Active (6 MHz signal
12 15.3 mA
rate), Figure 7-9, CL = 50 pF
Transmit side FS Active (6 MHz signal
9.5 13 mA
rate), Figure 7-9, CL = 50 pF
VBUS or V3P3V current consumption -
IVBUSx or IV3P3Vx Full Speed (FS) and Low Speed (LS) Receive side LS Active (750 kHz signal
11 13.5 mA
modes rate), Figure 7-10, CL = 450 pF
Transmit side LS Active (750 kHz signal
9.5 13 mA
rate), Figure 7-10, CL = 450 pF
FS/LS Idle State (US side or DS side) 7.4 11 mA

VBUS or V3P3V current consumption - L1 Upstream Facing side 7.5 9.8 mA

IVBUSx or IV3P3Vx
Sleep mode Downstream Facing side 7.3 9.5 mA

VBUS or V3P3V current consumption - L2 Upstream Facing side 1.07 1.55 mA

IVBUSx or IV3P3Vx
Suspend mode Downstream Facing side 5.6 7.5 mA

VBUS or V3P3V current consumption - Upstream Facing side 6.2 8.5 mA

IVBUSx or IV3P3Vx
Not attached Downstream Facing side 6.2 8.9 mA
Receive side HS Active (240 MHz
signal rate), EQxx = 00, RL = 45 Ω to 80 96 mA
ground on D+ and D-
IVCCx or IV1P8Vx current consumption - Transmit side HS Active (240 MHz
IVCCx or IV1P8Vx
High Speed (HS) mode signal rate), EQxx = 00, RL = 45 Ω to 85 96 mA
ground on D+ and D-
HS Idle State, EQxx = 00, RL = 45 Ω to
77 90 mA
ground on D+ and D-.
Receive side FS Active (6 MHz signal
0.4 0.55 mA
rate), Figure 7-9, CL = 50 pF
Transmit side FS Active (6 MHz signal
0.4 0.55 mA
rate), Figure 7-9, CL = 50 pF
IVCCx or IV1P8Vx current consumption -
IVCCx or IV1P8Vx Full Speed (FS) and Low Speed (LS) Receive side LS Active (750 kHz signal
0.4 0.55 mA
modes rate), Figure 7-10, CL = 450 pF
Transmit side LS Active (750 kHz signal
0.4 0.55 mA
rate), Figure 7-10, CL = 450 pF
FS/LS Idle State 0.4 0.55 mA

IVCCx or IV1P8Vx current consumption - Upstream Facing side 0.4 0.55 mA

IVCCx or IV1P8Vx
L1 Sleep mode Downstream Facing side 0.4 0.55 mA

IVCCx or IV1P8Vx current consumption - Upstream Facing side 0.4 0.55 mA

IVCCx or IV1P8Vx
L2 Suspend mode Downstream Facing side 0.4 0.55 mA

IVCCx or IV1P8Vx current consumption - Upstream Facing side 0.4 0.55 mA

IVCCx or IV1P8Vx
Not attached Downstream Facing side 0.4 0.55 mA

(1) Under voltage threshold when supply

UV+(VBUSx) 4.0 V
voltage is rising, VBUS

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) Under voltage threshold when supply

UV-(VBUSx) 3.6 V
voltage is falling, VBUS
UVHYS(VBUSx) Under voltage threshold hysteresis,
(1) 0.08 V
VBUS
Under voltage threshold when supply
UV+(V3P3Vx) 2.95 V
voltage is rising, V3P3V
Under voltage threshold when supply
UV-(V3P3Vx) 1.95 V
voltage is falling, V3P3V
Under voltage threshold hysteresis,
UVHYS(V3P3Vx) 0.11 V
V3P3V
Under voltage threshold when supply
UV+(VCCx) (2) 2.35 V
voltage is rising, VCC

(2) Under voltage threshold when supply

UV-(VCCx) 2 V
voltage is falling, VCC
UVHYS(VCCx) (2) Under voltage threshold hysteresis, VCC 0.05 V
Under voltage threshold when supply
UV+(V1P8Vx) 1.66 V
voltage is rising, V1P8V
Under voltage threshold when supply
UV-(V1P8Vx) 1.25 V
voltage is falling, V1P8V
Under voltage threshold hysteresis,
UVHYS(V1P8Vx) 0.05 V
V1P8V
DIGITAL INPUTS
0.7 x
VIH High-level input voltage V
V3PV3x
0.3 x
VIL Low-level input voltage V
V3PV3x
VIHYS Input transition threshold hysteresis 0.3 V
IIH High-level input current 1 µA
IIL Low-level input current 10 µA
DIGITAL OUTPUTS (V1OK, V2OK)
V3P3Vx -
VOH High-level output voltage IO = -3 mA for 3.0 V ≤ V3P3Vx ≤ 3.6 V V
0.2
VOL Low-level output voltage IO = 3 mA for 3.0 V ≤ V3P3Vx ≤ 3.6 V 0.2 V
UDx, DDx, INPUT CAPACITANCE AND TERMINATION
Vin=3.6 V, V3P3Vx=3.0 V, TJ < 125 ℃,
ZINP_xDx Impedance to GND, no pull up/down 300 kΩ
USB 2.0 Spec Section 7.1.6
Measured with VNA at 240MHz, Driver
CIO_xDx Capacitance to GND 10 pF
Hi-Z
Bus Pull up Resistor on Upstream
RPUI USB 2.0 Spec Section 7.1.5 0.9 1.1 1.575 kΩ
Facing Port (idle)
Bus Pull up Resistor on Upstream
RPUR USB 2.0 Spec Section 7.1.5 1.5 2.2 3 kΩ
Facing Port (receiving)
Bus Pull-down Resistor on Downstream
RPD USB 2.0 Spec Section 7.1.5 14.25 19 24.8 kΩ
Facing Port
USB 2.0 Spec Section 7.1.5, measured
Termination voltage for Upstream facing on D+ or D- with pull up enabled
VTERM 3 3.6 V
port pullup (RPU) on upstream port with external load
disconnected.
USB 2.0 Spec Section 7.1.6.2, The
VHSTERM Termination voltage in high speed output voltage in the high-speed idle –10 10 mV
state

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver Output Resistance (which also (VOH= 0 to 600mV) USB 2.0 Spec
ZHSTERM 40.5 45 49.5 Ω
serves as high-speed termination) Section 7.1.1.1 and Figure 7-5.
UDx, DDx, INPUT LEVELS LS/FS
USB 2.0 Spec Section 7.1.4 (measured
VIH High (driven) 2 V
at connector)
USB 2.0 Spec Section 7.1.4 (Host
downstream port pull down resistor
VIHZ High (floating) 2.7 3.6 V
enabled and Device pulled up to 3.0 V -
3.6 V).
VIL Low USB 2.0 Spec Section 7.1.4 0.8 V
|(xD+)-(xD-)|; USB 2.0 Spec Figure
VDI Differential Input Sensitivity 0.2 V
7-19; (measured at connector)
Includes VDI range; USB 2.0 Spec
VCM Common Mode Range 0.8 2.5 V
Figure 7-19; (measured at connector)
UDx, DDx, OUTPUT LEVELS LS/FS
USB 2.0 Spec Section 7.1.1, (measured
VOL Low at connector with RL of 0.9 kΩ to 3.6 0 0.3 V
V. )
USB 2.0 Spec Section 7.1.1 (measured
VOH High (Driven) at connector with RL of 14.25 kΩ to 2.8 3.6 V
GND. )
VOSE1 SE1 USB 2.0 Spec Section 7.1.1 0.8 V
USB 2.0 Spec Section 7.1.1 and Figure
ZFSTERM Driver Series Output Resistance 28 44 Ω
7-4, Measured during VOL or VOH
Measured as in USB 2.0 Spec Section
7.1.1 Figures 7-8, 7-9 and 7-10;
VCRS Output Signal Crossover Voltage 1.3 2 V
Excluding the first transition from the
Idle state
UDx, DDx, INPUT LEVELS HS
USB 2.0 Spec Section 7.1.7.2
(specification refers to peak differential
High-speed squelch/no-squelch
VHSSQ signal amplitude), measured at 240MHz 100 116 150 mV
detection threshold
with increasing amplitude, VCM=-50mV
to 500mV
USB 2.0 Spec Section 7.1.7.2
High-speed disconnect detection
VHSDSC (specification refers to differential signal 525 575 625 mV
threshold HSDC typical values
amplitude). VCM = -50 mV to 500 mV
Chirp detection threshold (measured
VCHIRP_TH Chirp detection threshold as peak differential signal amplitude). 70 215 365 mV
VCM = -50 mV to 500 mV
High-speed differential input signaling
VHSRX Peak-to-peak at 240 MHz 100 mV
levels data sensitivity
High-speed data signaling common USB 2.0 Spec Section 7.1.4.2, receiver
VHSCM mode voltage range (guideline for should be able to receive with this –50 200 500 mV
receiver) common mode range
UDx, DDx, OUTPUT LEVELS HS
USB 2.0 Spec Section 7.1.7.2,
measured single ended peak voltage
VHSOH High-speed data signaling high per USB 2.0 test measurement spec, 360 400 440 mV
EQxx = 00, Test load is an ideal 45 Ω to
GND on D+ and D-

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
USB 2.0 Spec Section 7.1.7.2,
measured single ended peak voltage
VHSOL High-speed data signaling low per USB 2.0 test measurement spec, –10 10 mV
EQxx = 00, Test load is an ideal 45 Ω to
GND on D+ and D-.
High-speed data signaling idle, driver is USB 2.0 Spec Section 7.1.7.2, PE
VHSOI off termination is on (measured single disabled,Test load is an ideal 45 Ω to –10 10 mV
ended) GND on D+ and D-.
USB 2.0 Spec Section 7.1.7.2, EQxx =
00, Test load is an ideal 45 Ω to GND
VCHIRPJ Chirp J level (differential voltage) 700 850 1100 mV
on D+ and D-, with 2.2 kΩ pull-up to 3.3
V on D+.
USB 2.0 Spec Section 7.1.7.2, EQxx =
00, Test load is an ideal 45 Ω to GND
VCHIRPK Chirp K level (differential voltage) –900 –750 –500 mV
on D+ and D-, with 2.2 kΩ pull-up to 3.3
V on D+.
Test load is an ideal 45 Ω to GND on D+
U2_TXCM High-speed TX DC Common Mode –50 200 500 mV
and D-.
EQUALIZATION AND PRE-EMPHASIS
EQHS High-speed RX Equalization EQ1=low, EQ0=low, 240MHz -0.24 0.46 0.75 dB
EQHS High-speed RX Equalization EQ1=low, EQ0=float, 240MHz 0.27 0.98 1.5 dB
EQHS High-speed RX Equalization EQ1=low, EQ0=high, 240MHz 0.70 1.50 2.2 dB
EQHS High-speed RX Equalization EQ1=float, EQ0=low, 240MHz 1.04 2.00 2.81 dB
EQHS High-speed RX Equalization EQ1=float, EQ0=float, 240MHz 1.45 2.68 3.8 dB
EQHS High-speed RX Equalization EQ1=float, EQ0=high, 240MHz 1.73 3.09 4.4 dB
EQHS High-speed RX Equalization EQ1=high, EQ0=low, 240MHz 2.00 3.46 4.7 dB
EQHS High-speed RX Equalization EQ1=high, EQ0=float, 240MHz 2.25 3.80 5.1 dB
EQHS High-speed RX Equalization EQ1=high, EQ0=high, 240MHz 2.25 3.80 5.1 dB
PEHS High-speed TX Pre-emphasis EQ1=low, EQ0=low, 240MHz 0.25 0.48 0.75 dB
PEHS High-speed TX Pre-emphasis EQ1=low, EQ0=float, 240MHz 0.62 0.9 1.2 dB
PEHS High-speed TX Pre-emphasis EQ1=low, EQ0=high, 240MHz 0.89 1.36 1.5 dB
PEHS High-speed TX Pre-emphasis EQ1=float, EQ0=low, 240MHz 1.4 1.7 2.0 dB
PEHS High-speed TX Pre-emphasis EQ1=float, EQ0=float, 240MHz 1.7 2.1 2.5 dB
PEHS High-speed TX Pre-emphasis EQ1=float, EQ0=high, 240MHz 2.1 2.5 2.9 dB
PEHS High-speed TX Pre-emphasis EQ1=high, EQ0=low, 240MHz 2.7 3.2 3.7 dB
PEHS High-speed TX Pre-emphasis EQ1=high, EQ0=float, 240MHz 3.4 4.0 4.6 dB
PEHS High-speed TX Pre-emphasis EQ1=high, EQ0=high, 240MHz 3.4 4.0 4.6 dB
CDP
Load Current in the range of 0 to 250
VDM_SRC VDM_SRC Voltage 0.5 0.7 V
uA
IDP_SINK IDP_SINK (D+) D+ Voltage = 0 V to 0.7 V 25 175 μA
VDAT_REF+ VDAT_REF comparator rising threshold 300 400 mV
VDAT_REF- VDAT_REF comparator falling threshold 275 385 mV
VDAT_REF_HYS VDAT_REF comparator hysteresis 15 20 25 mV
THERMAL SHUTDOWN
TSD+ Thermal shutdown turn-on temperature 160 170 180 °C
TSD- Thermal shutdown turn-off temperature 150 160 170 °C

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSDHYS Thermal shutdown hysteresis 10 °C

(1) If VBUSx pins are externally connected to the corresponding V3P3Vx pins, then UVLO thresholds on VBUSx are governed
by UV+(V3P3Vx) , UV-(V3P3Vx) and UVHYS(V3P3Vx)
(2) If VCCx pins are externally connected to the corresponding V1P8Vx pins, then UVLO thresholds on VCCx are governed by UV+(V1P8Vx) ,
UV-(V1P8Vx) and UVHYS(V1P8Vx)

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

6.10 Switching Characteristics

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER-UP TIMING
Allowed power supply ramp-up times on
TSUPRAMP VBUSx , V3P3Vx ,VCCx and V1P8Vx external 0.005 100 ms
power supplies
Time taken for the device to power up, and
recognize USB signaling, after valid power All external power supplies are ramped up
TPWRUP 3.6 8 ms
supply is provided on both side 1 and side together with 5 µs power up time.
2.
UDx, DDx, HS Driver Switching Characteristics
USB 2.0 Spec Section 7.1.2, ideal 45 Ω to GND
THSR Rise Time (10% - 90%) 310 370 510 ps
loads on D+ and D-, EQxx = 00
USB 2.0 Spec Section 7.1.2, ideal 45 Ω to GND
THSF Fall Time (10% - 90%) 310 370 510 ps
loads on D+ and D-, EQxx = 00
UDx, DDx, FS Driver Switching Characteristics
USB 2.0 Spec Figure 7-8, Figure 7-9, CL = 50
TFR Rise Time (10% - 90%) 4 20 ns
pF
USB 2.0 Spec Figure 7-8, Figure 7-9, CL = 50
TFF Fall Time (10% - 90%) 4 20 ns
pF
USB 2.0 Spec 7.1.2, Excluding the first
Differential Rise and Fall Time Matching
TFRFM transition from the Idle state, Figure 7-9, CL = 90 111.1 %
(TFR/TFM)
50 pF
UDx, DDx, LS Driver Switching Characteristics
USB 2.0 Spec Figures 7-8 and 7-10, with
TLR Rise Time (10% - 90%) 75 300 ns
CL range 50 pF to 600 pF.
USB 2.0 Spec Figures 7-8 and 7-10, with
TLF Fall Time (10% - 90%) 75 300 ns
CL range 50 pF to 600 pF.
Rise and Fall Time Matching (TLR/TFM), USB 2.0 Spec Figures 7-8 and 7-10, with
TLRFM 80 125 %
Excluding first transition from idle state. CL range 50 pF to 600 pF.
REPEATER TIMING - CONNECT, DISCONNECT, RESET, L1, L2
Debounce filter on FS or LS Connect
TFILTCONN 45 70 80 µs
Detection
Time to detect disconnect at the DS facing
TDDIS 2 7 µs
port in LS/FS L0 mode.
Time taken to detect reset on US port in
TDETRST 0 7 µs
LS/FS L0 mode
Time taken by the US side to detect
suspend mode (L2) and draw less than 2.5
T2SUSP 3 10 ms
mA current when bus is continuously in idle
state.
Maximum time to detect resume on the US
tDRESUMEL1 and reflect/drive resume on the DS port 1 µs
from sleep/L1 state.
Maximum time to detect resume on the US
tDRESUMEL2 and reflect/drive resume on the DS port 130 µs
from suspend/L2 state.
Maximum time to detect and propagate
tDWAKEL1 5 µs
remote wake when in sleep/L1 state.
Maximum pulse width of remote wake
tDWAKEL2 that is guranteed to be detected when in 900 µs
suspend/L2 state.
Minimum duration of resume driven
tDRSMPROP upstream and downstream after detecting 1 ms
remote wake when in suspend/L2 state.

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PK-PK common mode noise, VCMPKPK = 1200
CMTI Common mode transient immunity 50 100 kV/µs
V during USB data transmission, see Figure 7-3

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REPEATER TIMING - LS, FS
Low-speed Differential Data Propagation
TLSDD USB 2.0 spec section 7.1.14. Figure 7-52(C). 358 ns
Delay
TLSOP LS Data bit-width distortion after SOP USB 2.0 spec section 7.1.14. Figure 7-52(C). -40 25 ns
TLSJP LS repeater additive jitter - paired transition USB 2.0 spec section 7.1.14. Figure 7-52(C). –5 5 ns
TLSJN LS repeater additive jitter - next transition USB 2.0 spec section 7.1.14. Figure 7-52(C). –7.0 7.0 ns
Minimum width of SE0 interval during LS
TLST differential transition - filtered out by the USB 2.0 spec section 7.1.4. 210 ns
repeater
TLEOPD Repeater EOP delay relative to TLSDD USB 2.0 spec section 7.1.14. Figure 7-53(C). 0 200 ns
SE0 skew caused by the repeater during LS
TLESK USB 2.0 spec section 7.1.14. Figure 7-53(C). -100 100 ns
EOP
Full-Speed Differential Data Propagation
TFSDD USB 2.0 spec section 7.1.14. Figure 7-52(C). 70 ns
Delay
TFSOP FS Data bit-width distortion after SOP USB 2.0 spec section 7.1.14. Figure 7-52(C). -10 10 ns
TFSJP FS repeater additive jitter - paired transition USB 2.0 spec section 7.1.14. Figure 7-52(C). –2 2 ns
TFSJN FS repeater additive jitter - next transition USB 2.0 spec section 7.1.14. Figure 7-52(C). –6.0 6.0 ns
Minimum width of SE0 interval during FS
TFST differential transition - filtered out by the USB 2.0 spec section 7.1.4. 14 ns
repeater
TFEOPD Repeater EOP delay relative to TFSDD USB 2.0 spec section 7.1.14. Figure 7-53(C). 0 17 ns
SE0 skew caused by the repeater during FS
TFESK USB 2.0 spec section 7.1.14. Figure 7-53(C). -15 15 ns
EOP
REPEATER TIMING - HS
THSSOPT High-speed Start of Packet Truncation USB 2.0 spec, section 7.1.10. 6 8 UI
THSEOPD High-speed End of Packet Dribble USB 2.0 spec, section 7.1.13. 7 8 UI
THSPD High-speed Propagation Delay USB 2.0 spec, section 7.1.14. 2 3 4 ns
High-speed total additive jitter (output jitter
- input jitter) of repeater (includes all
THSTJ 120 ps
complete SOP bits), RX EQ disabled, TX
PE disabled.
High-speed additive random jitter (output
jitter - input jitter) of repeater (includes all
THSRJ 35 ps
complete SOP bits), RX EQ disabled, TX
PE disabled.
High-speed additive deterministic jitter
(output jitter - input jitter) of repeater
THSDJ 82 ps
(includes all complete SOP bits), RX EQ
disabled, TX PE disabled.
Time window of contiuous no transition
THSDIS during which the HS Disconnect Detector 36 82 ns
output must be sampled
Time for which a Chirp J or Chirp K must
TFILT be continuously detected (filtered) by hub or USB 2.0 spec, section 7.1.7.5. 2.5 µs
device during Reset handshake
CDP TIMING
TVDMSRC_E Time taken to enable VDMSRC on D- after
0.1 ms
N detecting VDPSRC connection on D+
TVDMSRC_DI Time taken to disable VDMSRC on D- after
0.1 ms
S detecting VDPSRC disconnection on D+

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

Over recommended operating conditions (unless otherwise noted). All typical values are at TA = 25°C, VBUSx = 5 V, V3P3Vx =
3.3 V, V1P8Vx = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TCON_IDPSIN Time taken to disable IDP_SINK on D+ after
0.1 ms
K_DIS detecting connect

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

6.11 Insulation Characteristics Curves

1600 3000
VI = 1.94 V Power
1400 VI = 3.6 V
VI = 5.5 V 2500
Safety Limiting Current (mA)

Safety Limiting Power (mW)

1200
2000
1000

800 1500

600
1000
400
500
200

0 0
0 50 100 150 200 0 50 100 150 200
Ambient Temperature (C) Ambient Temperature (C)

Figure 6-1. Thermal Derating Curve for Limiting Figure 6-2. Thermal Derating Curve for Limiting
Current per VDE for DP-28 Package Power per VDE for DP-28 Package

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

6.12 Typical Characteristics

Figure 6-3. Typical High-Speed (480 Mbps) Eye-

Diagram through ISOUSB211 Figure 6-4. Typical Full-Speed (12 Mbps) Eye-
Diagram through ISOUSB211

Figure 6-5. Typical Low-Speed (1.5 Mbps) Eye-Diagram through ISOUSB211

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

7 Parameter Measurement Information

7.1 Test Circuits

143
15.8

UD+ DD+ 50- Coax

USB 2.0 ISOUSB211 Oscilloscope

Golden Host / Peripheral 15.8
UD– DD– 50- Coax

143 Test Fixture

Per USB 2.0 standard

Figure 7-1. Upstream and Downstream Packet Parameter and Eye-Diagram Measurements for HS

Oscilloscope

UD+ DD+

USB 2.0 ISOUSB211 USB 2.0

Host Peripheral
UD– DD–

Figure 7-2. Upstream and Downstream Packet Parameter and Eye-Diagram Measurements for LS, FS

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

ISOUSB211

UD+ DD+

DC bias / UD- Oscilloscope /

DD-
Oscilloscope DC bias

GND1 GND2

Pass / Fail Criterion:

VCM Output remains stable

VCMPKPK/2

VCM

–VCMPKPK/2

Figure 7-3. Common-Mode Transient Immunity Test Circuit

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

8 Detailed Description
8.1 Overview
ISOUSB211 is a galvanically-isolated USB2.0 compliant repeater supporting Low Speed (1.5 Mbps), Full
Speed (12 Mbps) and High Speed (480 Mbps) signaling rates. The device supports automatic speed and
connection detection, reflection of pull-ups/pull-downs, and link power management allowing drop-in USB hub,
host, peripheral and cable isolation. Most microcontrollers integrate the USB PHY, and so offer only D+ and
D- bus lines as external pins. ISOUSB211 can isolate these pins from the USB bus without needing any other
intervention from the microcontroller. The device also supports automatic role reversal - if after disconnect, if a
new connect is detected on the Upstream facing port, then the Upstream and Downstream port definitions are
reversed. The ISOUSB211 has inbuilt programmable equalization to cancel signal loss caused by board traces,
which helps in meeting USB2.0 high-speed TX and RX eye-diagram templates. High Speed (HS) Test Mode
entry is also automatically detected, as required by the USB2.0 standard, to enable HS compliance tests.
ISOUSB211 is available in reinforced isolation option with isolation withstand voltage of 5000 VRMS respectively,
and with surge test voltage of 12.8 kVPK respectively. The device can operate completely off a 4.25 V to 5.5 V
supply (USB VBUS power) or from local 3.3-V and 1.8- supplies, if available, on both side 1 and side 2. This
flexibility in supply voltages allows optimization for thermal performance based on power rails available in the
system.
8.2 Functional Block Diagram
A simplified functional block diagram of ISOUSB211 is shown in Figure 8-1. The device comprises the following:
1. Transmit and receive circuits and pull-up and pull-down resistors according to the USB standard.
2. Digital logic to handle bi-directional communication, and various state-transitions.
3. Internal LDOs to generate V3P3Vx and V1P8Vxsupplies from the VBUSx and VCCxsupplies respectively.
4. Galvanic isolation.

22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

VBUS1 VBUS2
LDO LDO
V3P3V1 V3P3V2

VCC1 VCC2
LDO LDO
V1P8V1 V1P8V2

HSRX HSRX

HSTX HSTX

GALVANIC ISOLATION
SERXD- SERXD-
FSM FSM

SERXD+ SERXD+

FSM
LSFSRX LSFSRX

UD+ LSFSTX LSFSTX DD+

UD- DD-

PU/PD PU/PD

Figure 8-1. ISOUSB211 Simplified Functional Block Diagram

8.3 Feature Description

8.3.1 Power Supply Options
The ISOUSB211 can be powered by connecting a 4.25 V to 5.5 V supply on VBUSx pins, in which case an
internal LDO generates V3P3Vx voltage. This option is suitable for the side facing the USB connector, where a
5-V VBUS supply is available. Alternatively, VBUSx and V3P3Vx pins can be shorted together and an external 3.3-
V power supply can be connected to both. This second option is suitable for the side facing the microcontroller,
where a 5-V supply may not be available.
The ISOUSB211 also needs a 1.8-V supply for operation. A 2.4 V to 5.5 V supply can be connected on VCCx
pins, in which case internal LDOs generate the V1P8Vx supplies. In the simplest implementation, VCCx can be
connected to the USB VBUS on the side facing the connector, and to the 3.3-V local supply on the side facing
the microcontroller. In this implementation, there is power dissipation on the internal LDOs of ISOUSB, which
limits the maximum ambient temperature supported by ISOUSB211.
To reduce power dissipation inside the ISOUSB211, an external 1.8-V supply can be connected to both VCCx
and V1P8Vx pins shorted together, in which case the internal 1.8-V LDOs of ISOUSB211 are bypassed. In this
implementation, some of the power dissipation is transferred to the external 1.8-V supply, and overall higher
ambient temperature operation is achieved for the ISOUSB211. If the external 1.8-V supply is an LDO, the effect
is to reduce power dissipation inside ISOUSB211, but overall no reduction in system current or power dissipation
is achieved. Alternatively, if the external 1.8-V supply is a DC-DC (buck) converter, both system power and
ISOUSB211 power dissipation can be reduced.
A third option is to include external resistors between VCCx pins and VBUS and 3.3-V local supplies. These
resistors can be accomodated since VCCx pins operate down to 2.4 V. The resistors drop voltage and dissipate

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

power and serve a similar purpose as external 1.8-V LDOs, that is, reduce power dissipation inside ISOUSB211
and allow higher ambient temperature operation.
Refer to the Thermal Considerations section for further details on how to optimize ISOUSB211 internal power
dissipation according to the maximum ambient temperature required in the system, and for recommendations on
external resistors, LDOs and buck converters.
8.3.2 Power Up
Until all power supplies on both sides of ISOUSB211 are above their respective UVLO thresholds, the device
ignores any activity on the bus lines on both upstream and downstream side. Once the power supplies are
above their UVLO thresholds, the device is ready to respond to activity on the bus lines. When the power
supplies on side 1 are up, this is indicated on side 2 by V1OK = High. Similarly, V2OK = High indicates that Side
2 is fully powered up.
8.3.3 Symmetric Operation, Dual-Role Port and Role-Reversal
ISOUSB211 supports symmetric operation. Normally, UD+ and UD- are upstream facing ports and connect to a
host or hub. DD+ and DD- are downstream facing ports and connect to a peripheral. However, it is also possible
to connect UD+ and UD- to a peripheral and DD+ and DD- to a host or hub. Whichever side sees a connect
first (D+ or D- pulled up to 3.3 V) becomes the downstream facing side. This feature enables implementation of
dual-role port (for eg. Type-C dual-role port) and role-reversal (for eg. OTG Host Negotiation Protocol - HNP).
Refer to How to Implement an Isolated USB 2.0 High-Speed, Type-C® DRP application note for details. In the
rest of this document, DD+/DD- are treated as downstream facing ports, and UD+/UD- as upstream facing ports,
but the various operations and features described are equally applicable if this assignment is swapped.
8.3.4 Connect and Speed Detection
When there is no peripheral device connected to the downstream side of ISOUSB211, internal 15 kΩ pull-down
resistors on DD+ and DD- pins pull the bus lines to zero, creating an SE0 state. When either the DD+ or DD-
lines is pulled up higher than the VIH threshold, for a time period higher than TFILTCONN, the ISOUSB211 device
treats this as a connect. The ISOUSB211 device configures internal pull-up on the upstream side to match the
pull-up detected on the downstream side. After connect is detected, the ISOUSB211 device waits for a reset to
be asserted by the host/hub on the upstream side. Depending on whether DD+ or DD- is pulled up at the start
of reset, the speed of the ISOUSB211 repeater is set. Once set, the speed of the repeater can only be changed
after a power down or disconnect event.
A high-speed (HS) capable device is attached to the ISOUSB211 device would proceed to perform high-speed
handshake using chirp signaling as specified in the USB2.0 standard. This would be followed by chirp signals
from the host. The ISOUSB211 device reflects these chirp signals across the barrier, including HS idle (SE0)
states from downstream to upstream and vice versa. Upon successful completing of the HS handshake
ISOUSB211 speed is set to High speed. Once set to high-speed, the speed of the repeater can only be changed
after power down, HS disconnect event, or if the peripheral or host/hub do not perform HS handshake after a
reset.
8.3.5 Disconnect Detection
When in Full-speed (FS) and Low-speed (LS) modes, disconnection of a peripheral is indicated when the
host/hub is not driving any signal on the upstream side, and when the downstream bus is in the SE0 state ( Both
DD+ and DD- are below the VILthreshold) for a time period higher than TDDIS. Upon disconnect detection in FS
and LS modes, the ISOUSB211 device removes the pull-up resistor from the upstream side, thus allowing the
upstream UD+ and UD- lines to discharge to zero. The ISOUSB211 then waits for the next connect event to
occur.
When in High Speed (HS) mode, if the ISOUSB211 detects a continuous period of no transitions lasting
THSDIS, the devices samples the DD+ and DD- lines using the HS Disconnect detector. If the input differential
voltage crosses VHSDSC during THSDIS, the repeater removes the HS termination from both the downstream and
upstream terminals and transitions to a disconnect state. The ISOUSB211 then waits for the next connect event
to occur.

24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

8.3.6 Reset
The ISOUSB211 device detects Reset assertion (prolonged SE0 state) on its upstream facing side, and
transmits the same to the downstream facing side. In HS state, an extended HS idle state can be the beginning
of reset, or an entry into L2 Power Management state. ISOUSB211 is able to make the distinction between the
two, and accordingly either continue to drive HS idle (same as reset) on the downstream side or transition to the
L2 suspend state.
8.3.7 LS/FS Message Traffic
The ISOUSB211 device monitors the state of the bus on both upstream and downstream sides. The direction of
communication is set by which side transitions from the LS/FS idle state first (J to K transition). After that, data
is transferred digitally across the barrier, and reconstructed on the other side. Data transmission continues till
either an End-of-Packet (EOP) or a long idle is seen. At this point, the ISOUSB211 device tri-states its LS/FS
transmitters, and waits for the next transition from the LS/FS idle state.
8.3.8 HS Message Traffic
The ISOUSB211 device monitors the state of the bus on both upstream and downstream sides. The direction of
communication is set by which side transitions from the HS idle state first. Transition from HS idle state to valid
HS data is detected by the HS Squelch Detector. After that, data is transferred digitally across the barrier, and
reconstructed on the other side. Data transmission continues till the bus returns to HS idle state, also indicated
by the HS Squelch Detector. At this point, the ISOUSB211 device tri-states it's HS transmitters, and waits for the
next transition from the HS idle state.
8.3.9 Equalization and Pre-emphasis
The ISOUSB211 has inbuilt programmable receive equalization and transmit pre-emphasis to cancel signal loss
caused by board traces, which helps in meeting USB2.0 high-speed TX and RX eye-diagram templates. These
settings are controlled by EQ11 and EQ10 on side 1 and EQ21 and EQ20 on side 2. The EQxx pins can be
connected to ground, connected to 3.3-V supply or left floating, together creating 9 different equalization levels.
EQ11 and EQ10 can be chosen based on the length of D+/D- board trace and corresponding channel loss
estimated on side 1, and similarly EQ21 and EQ20 for side 2. Typical 45-Ohm trace in FR4 has about 0.15
dB/inch for 480 Mbps signaling. Further adjustments to the EQ settings can be made by observing the transmit
eye-diagram at the connector. If the trace lengths are very small, no equalization may be needed, and the EQxx
pins can be connected to ground.
ISOUSB211 samples EQxx pins only at power up, so it is not recommended to change the EQxx settings on the
fly after power up.

8.3.10 L2 Power Management State (Suspend) and Resume

The ISOUSB211 device supports Suspend low power state, also called L2 state in the USB 2.0 Link Power
Management engineering change notice (ECN). Suspend mode is detected if the bus stays in the LS/FS/HS
idle state for more than 3 ms. When Suspend is detected from LS and FS idle state, the ISOUSB211 continues
in the LS or FS idle state, at the same time reducing internal power consumption. If Suspend is detected from
HS idle state, the ISOSUB211 detects the DS port transition to FS idle state (FS J), and reflects this upstream,
while disabling all high-speed circuits to reduce power consumption. The transition to the L2 low-power mode is
completed within 10 ms.
Exit from L2 occurs through either Resume signaling from the host, on the upstream facing side of ISOUSB211,
or Remote Wake signaling from the peripheral on the downstream facing side of ISOUSB211 followed by
Resume signaling from the host/hub on the upstream facing side. Start of Resume or Wake are signaled by a ‘K’
state by the host or the device respectively. The end of resume is signalled by the host by driving two low-speed
bit times of SE0 followed by a 'J' state. If the port was operating in high speed before entering the low power
state, end of resume is signaled by the host by transitioning to the high speed idle state. ISOUSB211 is able
to replicate the resume and wake signaling appropriately both upstream and downstream. After Resume/Wake
signaling the device returns to LS, FS or HS idle state depending on the state it was in before entering the L2
state.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

8.3.11 L1 Power Management State (Sleep) and Resume

The ISOUSB211 device supports the additional L1 or Sleep low power state defined in the USB 2.0 Link Power
Management ECN. When L1 entry is detected from the LS and FS idle state, the ISOUSB211 continues in the
LS or FS idle state, at the same time reducing internal power consumption. If L1 entry is detected from HS idle
state, the ISOSUB211 disables all high-speed circuits to reduce power consumption. The transition to the L1
low-power mode is completed within 50 µs.
Exit from L1 occurs through either Resume signaling from the host, on the upstream facing side of ISOUSB211,
or Remote Wake signaling from the peripheral on the downstream facing side of ISOUSB211 followed by
Resume signaling from the host/hub on the upstream facing side. Start of Resume or Wake are signaled by a ‘K’
state by the host or the device respectively. The end of resume is signalled by the host by driving two low-speed
bit times of SE0 followed by a 'J' state. If the port was operating in high speed before entering the low power
state, end of resume is signaled by the host by transitioning to the high speed idle state. ISOUSB211 is able to
replicate the K signaling appropriately both upstream and downstream. After Resume/Wake signaling the device
returns to LS, FS or HS idle state depending on the state it was in before entering the L1 state.
8.3.12 HS Test Mode Support
USB2.0 standards needs test mode support, where the host/hub or peripheral is expected to enter High Speed
test-modes based on commands received. ISOUSB211 is able to automatically detect test mode entry to enable
HS compliance tests.
8.3.13 CDP Advertising

The ISOUSB211 device supports CDP advertising on both downstream and upstream facing side according to
Battery Charger standard BC 1.2. CDP advertizing is useful when isolating a host or hub, to indicate to the
connected peripheral that the port is capable of supplying 1.5 A of current on VBUS. CDP advertising can be
enabled by connecting the dowsnstream side CDPENZx pin to ground (active low).
8.4 Device Functional Modes
Function Table lists the functional modes for the ISOUSB211 device.
Table 8-1. Function Table
SIDE 1 SIDE 2
SUPPLY BUS1 SUPPLY BUS2
COMMENTS
VBUS1, V3P3V1 (UD+, UD-) VBUS2, V3P3V2 (DD+, DD-)
VCC1, V1P8V1 (1) VCC2, V1P8V2
When both sides are powered, the state-of the bus is reflected
Powered Active Powered Active
correctly from upstream to downstream and vice-versa.
Powered 15-kΩ PD Powered 15-kΩ PD Disconnected state is presented on both upstream and downstream
Powered 15-kΩ PD Unpowered Z
If a side is not powered, the bus lines on that side are in high-
Unpowered Z Powered 15-kΩ PD
impedance state.
Unpowered Z Unpowered Undetermined

(1) Powered =( (VBUSx ≥ UV+(VBUSx)) || (VBUSx = V3P3Vx ≥ UV+(V3P3Vx)) ) & ( (VCCx ≥ UV+(VCCx)) || (VCCx = V1P8Vx ≥ UV+(V1P8Vx)) ) ;
Unpowered = ( (VBUSx < UV-(VBUSx)) & (V3P3Vx < UV-(V3P3Vx)) ) || ( (VCCx < UV-(VCCx)) & (V1P8Vx < UV-(V1P8Vx)) ); X = Irrelevant; H = High
level; L = Low level; Z = High impedance

26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

9 Power Supply Recommendations

0.1 µF capacitors are recommended to be placed very close to V3P3Vx pins to GNDx. 1-µF capacitors are
recommended to be placed placed very close to VBUSx pins to GNDx. 2-µF, 0.1-µF, and 10-nF capacitors
are recommended to be placed between V1P8Vx and GNDx, between pins 4 and 3, between pins 25 and 26,
between pins 11 and 12, and between pins 25 and 26 respectively, as close to the device as possible. Place
the lower value capacitors closer to the IC. If VCCx pins are connected through resistors as shown in Example
Configuration 3 1-µF capacitors are recommended to be placed between VCCx (pins 5, 24) and GNDx (pins 3,
26), as close to the device as possible, with higher priority being accorded to the capacitors on V1P8Vx pins.
These decoupling capacitor recommendations are irrespective of whether the 3.3 V and 1.8 V supplies are
provided externally or generated using internal LDOs.
Refer to the Section 11.1.1 section for recommended placement of the decoupling capacitors. Small footprint
capacitors (0402/0201) are recommended so that these may be placed very close to the supply pins and
corresponding ground pins on the top layer without the use of vias. The capacitors on V1P8Vx supplies are higher
in priority when considering placement close to the IC.
While isolating a host/hub or bus-powered peripherals, isolated power is needed and can be generated with
the help of a transformer driver such as TI's SN6505B. For such applications, detailed power supply design,
and transformer selection recommendations are available in the SN6505 Low-Noise 1-A Transformer Drivers for
Isolated Power Supplies data sheet. If CDP functionality is enabled while isolation host/hub, the isolated power
supply must be capable of delivering 1.5 A on VBUS.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

10.1 Typical Application

10.1.1 Isolated Host or Hub
Figure 10-1 shows an application for isolating a host or a hub using ISOUSB211. In this example, on the
microntroller side, V3P3V1 and VBUS1 are together connected to an external 3.3-V supply. The V1P8V1 supply is
generated using the internal 1.8-V LDO by providing 3.3-V supply to VCC1. On the connector side, the VBUS
from the USB connector is connected to VBUS2 and the V3P3V2 supply is generated using the internal 3.3-V
LDO. VCC2 and V1P8V2 are together connected to an external 1.8-V supply derived from VBUS. Please refer to
Thermal Considerations for options on optimizing power dissipation inside ISOUSB211 as required.
Decoupling capacitors are placed next to ISOUSB211 according to the recommendations provided in the Power
Supply Recommendations section. An isolated DC-DC converter (such as the SN6505) is to provide power
to the VBUS using the 3.3-V local supply. Note that, for a host or hub, the USB standard requires a 120-μF
capacitor to be placed on the VBUS so as to be able provide in-rush current when a downstream peripheral is
attached. In addition, a 100-nF capacitor is recommended close to the VBUS pin to handle tranisent currents.
ESD diodes with low capacitance and low dynamic resistance, such as PESD5V0C1USF, may be placed on D+
and D- lines. A ferrite bead, with dc resistance less than 100 mΩ, may be optionally placed between VBUS pin of
the connector and the VBUS pin of ISOUSB211, as shown in the figure, to suppress transients such as ESD.
If the isolated power supply used is capable of providing >1.5 A current on the VBUS, the port can be configured
as a CDP port according to Battery Charger specification BC 1.2. To do this, the CDPENZ2 pin of ISOUSB211
must be connected to ground as shown. Under this condition ISOUSB211 responds to BC 1.2 signaling from a
connected peripheral indicating to the peripheral that the port is capable of supply 1.5-A current on VBUS.

28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

GND D2 IN OUT

3.3 VLV LDO

EN ISO VCC 3.3 µF
DC-DC 1 µF
GND
D1
CLK

3.3 VLV (local supply) 1 µF 28 VBUS (5.0 V)

1 VBUS2
VBUS1
V3P3V2 27 3.3 V 1 µF Ferrite
2 V
VCC 0.1 µF
3P3V1 LDO/ Bead
3 0.1 µF DC-DC
GND1 26 100 nF
10 nF GND2
2 µF 1.8 V 120 µF VBUS
ISOUSB211 10 nF 0.1 µF
4 V V1P8V2 25
0.1 µF
1P8V1 2 µF
5 D-
3.3 VLV VCC1 24
VCC2
Host/Hub 23
6 D+
MCU V2OK V1OK
7 22 GND
DM UD- DD-
8 21
DP UD+ DD+ Downstream
3.3VLV 9 20 Port
EQ10 EQ20
DGND Connector
0V 10 19
EQ11 EQ21
ISO
2 µF 0.1 µF 10 nF 11 18 10 nF 0.1 µF 2 µF
V1P8V1 V1P8V2 Ground
Digital
Ground 12 17
GND1 GND2
3.3 VLV 13 16
CDPENZ1 CDPENZ2
14 15
NC NC

Galvanic
Isolation Barrier

Figure 10-1. Isolated Host or Hub with ISOUSB211

10.1.2 Isolated Peripheral - Self-Powered

Figure 10-2 shows an application for isolating a self-powered peripheral using ISOUSB211. In this example, on
the microntroller side, V3P3V2 and VBUS2 are together connected to an external 3.3-V supply. The V1P8V2 supply
is generated using the internal 1.8-V LDO by providing 3.3-V supply to VCC1. On the connector side, the VBUS
from the USB connector is connected to VBUS1 and the V3P3V1 supply is generated using the internal 3.3-V
LDO. VCC1 and V1P8V1 are together connected to an external 1.8-V supply derived from VBUS. Please refer to
Thermal Considerations for options on optimizing power dissipation inside ISOUSB211 as required.
Decoupling capacitors are placed next to ISOUSB211 according to the recommendations provided in the Power
Supply Recommendations section. Note that the USB standard requires that, for a peripheral, the total capacitor
value on VBUS must be less than 10-μF. However, a total of at least 5-µF capacitance is recommended on
VBUS. A 100-nF capacitor is recommended close to the VBUS pin to handle tranisent currents.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

ESD diodes with low capacitance and low dynamic resistance, such as PESD5V0C1USF, may be placed on D+
and D- lines. A ferrite bead, with dc resistance less than 100 mΩ, may be optionally placed between VBUS pin of
the connector and the VBUS pin of ISOUSB211, as shown in the figure, to suppress transients such as ESD.
VBUS (5.0 V) 3.3 VLV (local supply)
1
VBUS1 VBUS2 28
Ferrite 5 µF 3.3 V 2 27 1 µF
V3P3V2 0.1 µF
Bead V3P3V1 VCC
LDO/
DC-DC 0.1 µF 3
GND1 GND2 26
VBUS
100 nF ISOUSB211
1.8 V 2 µF 0.1 µF 10 nF 4
V1P8V1 V1P8V2 25 1.8 VLV
D- 10 nF 0.1 µF 2 µF Peripheral
5 24
VCC1 VCC2 MCU
3.3 VLV
D+ 6 23
V2OK V1OK
GND 7 22
UD- DD- DM
8 21
UD+ DD+ DP
Upstream
Port 9 3.3 VLV
EQ10 EQ20 20
Connector DGND
10 19
EQ11 EQ21 0V
ISO
2 µF 0.1 µF 10 nF 11 V 18 10 nF 0.1 µF 2 µF
Ground 1P8V1 V1P8V2
Digital
12 17 Ground
GND1 GND2
13 16 3.3 VLV
3.3 V CDPENZ1 CDPENZ2
14 15
NC NC

Galvanic
Isolation Barrier

Figure 10-2. Isolated Self-Powered Peripheral with ISOUSB211

10.1.3 Isolated Peripheral - Bus-Powered

Figure 10-3 shows an application for isolating a self-powered peripheral using ISOUSB211. In this example, an
isolated DC-DC converter (for example: SN6505) is used to create a 3.3-V local supply while deriving power
from the USB VBUS. On the microntroller side, V3P3V2 and VBUS2 are together connected to an external 3.3-V
supply. The V1P8V2 supply is generated using the internal 1.8-V LDO by connecting the 3.3-V local supply to
VCC1. On the connector side, the VBUS from the USB connector is connected to VBUS1 and the V3P3V1 supply is
generated using the internal 3.3-V LDO. VCC1 and V1P8V1 are connected together connected to an external 1.8-V
supply derived from VBUS. Please refer to Thermal Considerations for options on optimizing power dissipation
inside ISOUSB211 as required.
Decoupling capacitors are placed next to ISOUSB211 according to the recommendations provided in the Power
Supply Recommendations section. Note that the USB standard requires that, for a peripheral, the total capacitor
value on VBUS, including any decoupling capacitors reflected from the secondary side through the isolated
DC-DC converter, must be less than 10-μF. However, a total of at least 5-µF capacitance is recommended on
VBUS. A 100-nF capacitor is recommended close to the VBUS connector to handle tranisent currents.

30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

ESD diodes with low capacitance and low dynamic resistance, such as PESD5V0C1USF, may be placed on D+
and D- lines. A ferrite bead, with dc resistance less than 100 mΩ, may be optionally placed between VBUS pin of
the connector and the VBUS pin of ISOUSB211, as shown in the figure, to suppress transients such as ESD.

GND D2 IN OUT
3.3 µF TPS76350
EN
EN SN6505 VCC
1 µF
GND NC
D1
CLK

1 28 3.3 VLV
VBUS1 VBUS2
VBUS (5.0 V) 5 µF 1 µF
3.3 V 2 27
Ferrite V3P3V1 V3P3V2
Bead 0.1 µF VCC
LDO/
DC-DC 0.1 µF 3
GND1 GND2 26
VBUS ISOUSB211
100 nF 1.8 V 2 µF 0.1 µF 10 nF 4
V1P8V1 V1P8V2 25
D- 5 24 10 nF 0.1 µF 2 µF
VCC1 VCC2
3.3 VLV Peripheral
D+ 6 23
V2OK V1OK MCU
GND 7 22
UD- DD- DM
8
UD+ DD+ 21 DP
Upstream
Port 9 20 3.3 VLV
EQ10 EQ20
Connector DGND
10 19 0V
EQ11 EQ21
ISO
2 µF 0.1 µF 10 nF 11 10 nF 0.1 µF 2 µF
Ground V1P8V1 V1P8V2 18 Digital GND
12 17 Ground
GND1 GND2
3.3 V 13 16 3.3 VLV
CDPENZ1 CDPENZ2
14 15
NC NC

Galvanic
Isolation Barrier

Figure 10-3. Isolated Bus-Powered Peripheral using ISOUSB211

10.1.4 Application Curve

10.1.4.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 10-4 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 50% for
lifetime which translates into minimum required insulation lifetime of 30 years at a working voltage that's 20%
higher than the specified value.
Figure 10-5 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 169 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DP-28 package is specified upto 1500 VRMS. At the lower working voltages,
the corresponding insulation lifetime is much longer than 169 years.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

A
Vcc 1 Vcc 2

Time Counter

DUT > 1 mA

GND 1 GND 2
VS

Oven at 150 °C

Figure 10-4. Test Setup for Insulation Lifetime Measurement

Figure 10-5. Insulation Lifetime Projection Data

10.2 Meeting USB2.0 HS Eye-Diagram Specifications

The USB2.0 standadards specifies TX and RX eye-diagram templates that must be met at the connector. The
horizontal eye-opening achieved at the connector is a combination of the performance at the microcontroller,
the additive jitter of the ISOUSB211, and the inter-symbol interference resulting from the insertion loss of D+/D-
board traces. For best performance, it is recommended to minimize the length of D+/D- board traces from the
MCU to ISOUSB211, and from ISOUSB211 to the connector. Vias and stubs on D+/D- lines must be avoided.
The ISOUSB211 has inbuilt programmable receive equalization and transmit pre-emphasis to cancel signal loss
caused by board traces, which helps in meeting USB2.0 high-speed TX and RX eye-diagrams. EQ11 and EQ10
can be chosen based on the length of D+/D- board traces and corresponding channel loss estimated on side 1,
and similarly EQ21 and EQ20 for side 2. The EQxx pins can be connected to ground, connected to 3.3-V supply
or left floating, together creating 9 different equalization levels.
Typical 45-Ohm traces in FR4 have an insertion loss of about 0.15 dB/inch for 480 Mbps signaling. This number
can be used to arrive at an estimate for the amount of Equalization/Pre-emphasis needed and the corresponding
EQ settings. Further adjustments to the EQxx settings can be made by observing the transmit eye-diagram at

32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

the connector, and chossing the setting that gives the best eye-opening. Chosing the right setting for the transmit
path will also result in an optimum performance for the receive path. Refer to Compensate for Channel Loss with
Equalizer Settings on High-Speed USB Isolators application note for details. If the trace lengths are very small,
no equalization may be needed, and the EQxx pins can be connected to ground.
10.3 Thermal Considerations
ISOUSB211 offers different power supply input options, including internal LDOs, that can be used to optimize
thermal performance in HS mode. If the 3.3-V and 1.8-V supplies are supplied using external regulators,
the power dissipated inside the ISOUSB chip is lower. The internal power dissipated, when taken with the
junction-to-air thermal resistance defined in the Thermal Information table can be used to determine the junction
temperature for a given ambient temperature. The junction temperature must not exceed 150°C. This section
describes different power supply configurations for ISOUSB211 and explains how the power dissipated inside
ISOUSB211 and the internal temperature rise can be calculated in each case.
For optimal thermal performance, connect small ground planes to the GNDx pins, and connect these planes to
the ground layer with multiple vias as shown in Layout Example.
10.3.1 VBUS / V3P3V Power
If VBUS is connected to external 5.0-V supply, with V3P3V generated through an internal LDO, the power
dissipated is VBUSx × IVBUSx.

If VBUSx and V3P3Vx are shorted together and connected to an external 3.3 V supply, the power dissipated due
to this supply is V3P3Vx × I3P3Vx.
10.3.2 VCCx / V1P8Vx Power
If VCCx is connected to external 2.4 to 5.0-V supply, with V1P8Vx generated through the internal 1.8-V LDO, the
power dissipated is VCCx × IVCCx.

If VCCx and V1P8Vx are are shorted together and connected to an external 1.8-V supply, the power dissipated due
to this supply is V1P8Vx × I1P8Vx.
10.3.3 Example Configuration 1
In the application example shown in Figure 10-6, ISOUSB211 is powered using USB VBUS on the connector
side, and a local 3.3-V digital supply on the microcontroller side. No other external regulators or power supplies
are used.
In this scenario, the total power consumption inside ISOUSB211 from both sides taken together is:
VBUS1 × IVBUS1 + VBUS1 × IVCC1 + V3P3V2 × I3P3V2 + V3P3V2 × IVCC2
Assuming 5.25 V as the maximum value of VBUS1, and 3.5 V as the maximum value of the 3.3-V local supply,
the internal power dissipation is calculated as:
5.25 V×13.5 mA + 5.25 V×96 mA + 3.5 V×13.5 mA+3.5 V×96 mA = 960 mW.
Since the junction-to-air thermal resistance is 44.2°C/W, this power dissipation results in a 42.5°C internal
temperature rise. Ambient temperature up to 107°C can be supported for this configuration.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

This configuration offers the simplest implementation, but the ambient temperature supported is lower than other
configurations.
VBUS (5.0 V) 3.3 VLV (local supply)
1
VBUS1 VBUS2 28
Ferrite 5 µF 3.3 V 2 27
V3P3V2 0.1 µF 1 µF
Bead V3P3V1 VCC
0.1 µF 3
GND1 GND2 26
VBUS ISOUSB211
100 nF 1.8 V 2 µF 0.1 µF 10 nF 4
V1P8V1 V1P8V2 25
D- 10 nF 0.1 µF 2 µF
5 24
VCC1 VCC2 3.3 VLV
23 Peripheral
D+ 6
V2OK V1OK MCU
GND 7
UD- DD- 22 DM
8 21
Upstream UD+ DD+ DP
Port 9 20 3.3 VLV
EQ10 EQ20
Connector DGND
10
EQ11 EQ21 19 0V
ISO 2 µF 0.1 µF 10 nF 11 18 10 nF 0.1 µF 2 µF
Ground V1P8V1 V1P8V2 Digital
12 17 Ground
GND1 GND2
13 16
3.3 V CDPENZ1 CDPENZ2 3.3 VLV
14 15
NC NC

Galvanic
Isolation Barrier

Figure 10-6. Using ISOUSB211 without External 1.8-V Regulators

10.3.4 Example Configuration 2

In the application example shown in Figure 10-7, ISOUSB211 is powered using USB VBUS on the connector
side, and a local 3.3-V digital supply on the microcontroller side to generate V3P3Vx. An external LDO or DC-DC
buck converter is used to generate V1P8Vx on both sides.
In this scenario, the total power consumption from both sides taken together is:
VBUS1 × IVBUS1 + V1P8V1 × I1P8V1 + V3P3V2 × I3P3V2 + V1P8V2 × I1P8V2
Assuming 5.25 V as the maximum value of VBUS, and 1.89 V as the maximum value of the external 1.8-V
power supply, the internal power dissipation is calculated as
5.25 V×13.5 mA + 1.89 V×96 mA + 3.5 V×13.5 mA+1.89 V×96 mA = 481 mW.
Since the junction-to-air thermal resistance is 44.2°C/W, this power dissipation results in a 22°C internal
temperature rise. Ambient temperature up to 128°C can be supported for this configuration.
TLV741P and TLV62568 are examples of low-cost LDO and buck converter respectively that may be used in this
application. Both options reduce the power dissipation in ISOUSB211. However, the buck converter additionally
reduces power dissipation at the system level, and also the current drawn from VBUS and local 3.3-V supplies.

34 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

This configuation offers the lowest power dissipation and the highest ambient temperature operation using
external regulators.
VBUS (5.0 V) 28 3.3 VLV (local supply)
1
VBUS1 VBUS2
Ferrite 5 µF 3.3 V 2 1 µF
V3P3V1 V3P3V2 27
Bead 0.1 µF VCC
LDO/ LDO/
DC-DC 0.1 µF 3 26 DC-DC
GND1 GND2
VBUS
100 nF ISOUSB211 25 10 nF 0.1 µF 2 µF
1.8 V 2 µF 0.1 µF 10 nF 4
V1P8V1 V1P8V2
D- 1.8 VLV Peripheral
5 24
VCC1 VCC2 MCU
D+ 6 23
V2OK V1OK
GND 7 22
UD- DD- DM
8 21
UD+ DD+ DP
Upstream
Port 9 20 3.3 VLV
EQ10 EQ20
Connector DGND
10 19 0V
EQ11 EQ21
ISO
2 µF 0.1 µF 10 nF 11 V 18 10 nF 0.1 µF 2 µF
Ground 1P8V1 V1P8V2 Digital
12 17 Ground
GND1 GND2
3.3 V 13 16
CDPENZ1 CDPENZ2 3.3 VLV
14 15
NC NC

Galvanic
Isolation Barrier

Figure 10-7. Using ISOUSB211 with 1.8-V supplied with External Regulators

10.3.5 Example Configuration 3

In the application example shown in Figure 10-8, ISOUSB211 is powered using USB VBUS on the connector
side, and a local 3.3-V digital supply on the microcontroller side to generate V3P3Vx. The internal LDOs are used
to generate V1P8Vx on both sides like in Example Configuration 1. However, the VCC1 and VCC2 are connected to
VBUS and 3.3 VLV, not directly like in Example Configuration 1, but through resistors R1 (20 Ω, 250 mW) and
R2 (5 Ω, 50 mW) respectively.
The external resistors drop voltage, and dissipate power, helping reduce the power dissipation within
ISOUSB211, and the corresponding temperature rise. The resistor values are decided keeping in mind that
the VCCx voltage can be as low as 2.4 V. Additional 1-μF capacitors are needed on VCCx pins.
In this scenario, the total power consumption inside the IC from both sides taken together is:
VBUS1 × IVBUS1 + VBUS1 × IVCC1 - 20 Ω × IVCC1× IVCC1+ V3P3V2 × I3P3V2 + V3P3V2 × IVCC2- 5 Ω × IVCC2× IVCC2
Assuming 5.25 V as the maximum value of VBUS, and 3.5 V as the maximum value of the 3.3-V local supply,
the internal power dissipation is calculated as
5.25 V×13.5 mA + 5.25 V×96 mA - 20 Ω×96 mA×96 mA + 3.5 V×13.5 mA+3.5 V×96 mA - 5 Ω×96 mA×96 mA =
728 mW.
Since the junction-to-air thermal resistance is 44.2°C/W, this power dissipation results in a 33°C internal
temperature rise. Ambient temperature up to 117°C can be supported for this configuration.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

This configuration offers a middle path between Example Configuration 1 and Example Configuration 2,
achieving lower temperature rise, and higher ambient temperature operation, with the addition of only two
resistors and two capacitors.
VBUS (5.0 V) 3.3 VLV (local supply)
1
VBUS1 VBUS2 28
5 µF 3.3 V 2 27 0.1 µF
V3P3V2 1 µF
V3P3V1 VCC
0.1 µF 3
GND1 GND2 26
VBUS ISOUSB211 1 µF
100 nF 2 µF 0.1 µF 10 nF 4
1.8 V V1P8V1 V1P8V2 25 R2=5

D- R1=20 10 nF 0.1 µF 2 µF
5 24
VCC1 VCC2
250 mW 23
50 mW Peripheral
D+ 6
1 µF V2OK V1OK MCU
3.3 VLV
GND 7
UD- DD- 22 DM
8 21
Upstream UD+ DD+ DP
Port 9 20 3.3 VLV
EQ10 EQ20
Connector DGND
10
EQ11 EQ21 19 0V
ISO 2 µF 0.1 µF 10 nF 11 18 10 nF 0.1 µF 2 µF Digital
Ground V1P8V1 V1P8V2
Ground
12 17
GND1 GND2
13 16
3.3 V CDPENZ1 CDPENZ2 3.3 VLV
14 15
NC NC

Galvanic
Isolation Barrier

Figure 10-8. Using ISOUSB211 with Resistors in series with VCCx pins

36 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

11 Layout
11.1 Layout Guidelines
Three layers are sufficient to accomplish a low EMI PCB design. Layer stacking should be in the following order
(top-to-bottom): high-speed signal layer, ground plane, optional power layer, and low-frequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• For best performance, it is recommended to minimize the length of D+/D- board traces from the MCU to
ISOUSB211, and from ISOUSB211 to the connector. Vias and stubs on D+/D- lines must be avoided. This is
especially important for High Speed Operation.
• Placing a solid ground plane just below the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
D+ and D- traces must be designed for 90-Ω differential impedance and as close to 45-Ω single ended
impedance as possible.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Decoupling capacitors must be placed on the top layer, and the routing between the capacitors and the
corresponding to supply and ground pins must be completed in the top layer itself. There should not be any
vias in the routing path between the decoupling capacitors and the corresponding supply and ground pins.
• ESD structures must be placed on the top layer, close to the connector, and right on the D+/D- traces without
vias. Ground routing for the ESD structures must be made in the top layer if possible, else must have a
strong connection to the ground plane with multiple vias.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Connect a small plane (for example, 2 mm x 2 mm) to the GND pins on the top layer to improve thermal
performance. Connect this to the ground player in the second layer with multiple vias. See Layout Example
for details.
11.1.1 Layout Example
The layout example in this section shows the recommended placement for de-coupling capacitors and ESD
protection diodes. A continuous ground plane is recommended below the D+/D- signal traces. Small footprint
capacitors (0402/0201) are recommended so that these may be placed very close to the supply pins and
corresponding ground pins and connected using the top layer. There should not be any vias in the routing path
between the decoupling capacitors and the corresponding supply and ground pins. The capacitors on V1P8Vx
supplies are higher in priority when considering placement close to the IC. The ESD protection diodes should be
placed close to the connector with a strong connection to the ground plane. Pins 4 and 11 for V1P8V1 and pins
18 and 25 for V1P8V2 are connected together, but this connection is after the de-coupling capacitors. If more than
2 layers are available in the PCB, this connection should be made in an inner or bottom layer (ex. Layer 3 or
4) so as to not interrupt the ground plane under the D+/D- traces. The example shown is for an isolated host or
hub, but similar considerations apply for isolated peripherals also. The 120-μF capacitor on VBUS only applies
to host or hub and should not be used for peripherals. A ferrite bead, with dc resistance less than 100 mΩ, may
be optionally placed on the VBUS route, after the 100-nF (and 120-μF) capacitors to prevent transients such as
ESD from affecting the rest of the circuits.
For best performance, it is recommended to minimize the length of D+/D- board traces from the MCU to
ISOUSB211, and from ISOUSB211 to the connector. Vias and stubs on D+/D- lines must be avoided. This is
especially important for High Speed Operation.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

Connect a small plane (for example, 2 mm x 2 mm) to the GND pins on the top layer to improve thermal
performance. Connect this to the ground player in the second layer with multiple vias.

Ferrite
1 µF Bead
1 µF
VBUS1 VBUS2
0.1 µ
0.1 µ F
F V3P3V2
V3P3V1
10 nF 10 nF
2 µF GND1 GND2 120 µF

V1P8V1 V1P8V2
2 µF 0.1 µF 0.1 µF 2 µF
VCC1 VCC2
x x

1 nF
V2OK V1OK VBUS
ESD D
x x
UD- DD- D-
MCU
UD+ D+
DD+
x x
ESD D GND
EQ10 EQ20

x EQ11 EQ21 x

2 µF 10 nF 10 nF 2 µF
V1P8V1 V1P8V2
x x

GND1 GND2
0.1 µF 0.1 µF
CDPENZ1 CDPENZ2

NC NC

GND1 Plane GND2 Plane

Figure 11-1. Layout Example for ISOUSB211

11.1.2 PCB Material

For digital circuit boards operating at less than 500 Mbps, (or rise and fall times greater than 1 ns), and
trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over
lower-cost alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater
strength and stiffness, and the self-extinguishing flammability-characteristics.

38 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

PACKAGE OUTLINE
DP0028A-C01 SCALE 1.500
SSOP - 2.65 mm max height
SMALL OUTLINE PACKAGE

10.63 SEATING PLANE

9.97
A PIN 1 ID
AREA 0.1 C

1 28

26x 0.65

10.5
10.1 2 x 8.45
NOTE3

14
15
7.6
B 7.4
NOTE4 28x0.35
0.29
2.65 max

0.25 C A B

0.304 TYP
0.204

0.25
GAGE PLANE
SEE DETAIL A

0.3
0 -8 0.1
1.27
0.4 DETAIL A
(1.4) TYPICAL

4225976/B 09/2020

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com

40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

EXAMPLE BOARD LAYOUT

DP0028A-C01 SSOP - 2.65 mm max height
SSOP

SYMM
SYMM 28x(1.65)
28x(2)
1 28 1 28

28x(0.45) 28x(0.45)

SYMM SYMM

26x(0.65) 26x(0.65)

14
15 15
R0.075 TYP R0.075 TYP 14

(9.3) (9.75)

IPC-7351 STANDARD HV / ISOLATION OPTION

7.3mm CLEARANCE/CREEPAGE 8.1mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4225976/B 09/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

EXAMPLE STENCIL DESIGN

DP0028A-C01 SSOP - 2.65 mm max height
SSOP

SYMM
SYMM 28x(1.65)
28x(2)
1 28 1 28

28x(0.45) 28x(0.45)

SYMM SYMM

26x(0.65) 26x(0.65)

14
15 15
R0.075 TYP 14

(9.3) (9.75)

IPC-7351 STANDARD HV / ISOLATION OPTION

7.3mm CLEARANCE/CREEPAGE 8.1mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125mm THICK STENCIL
SCALE:4X

4225976/B 09/2020

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

42 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 ISOUSB211
www.ti.com SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023

13.1 Tape and Reel Information

REEL DIMENSIONS TAPE DIMENSIONS
K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants
Reel Reel
Package Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter Width W1
Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) (mm)
ISOUSB211DPR SSOP DP 28 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43

Product Folder Links: ISOUSB211

ISOUSB211
SLLSFC5C – NOVEMBER 2021 – REVISED JANUARY 2023 www.ti.com

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

L
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISOUSB211DPR SSOP DP 28 2000 350.0 350.0 43.0

44 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOUSB211

 PACKAGE OPTION ADDENDUM

www.ti.com 8-Dec-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISOUSB211DPR ACTIVE SSOP DP 28 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOUSB211 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated