Ex.

No: 1

Date:
Adders and Subtractors
Aim: To simulate Adders and Subtractors in behavioural, structural, and dataflow model of Verilog HDL.

Software used: Xilinx Vivado.

HARDWARE USED: Basys 3 FPGA board

HALF ADDER:

Half adder in the behavioural model:

module half_adder(s,c,a,b);

output reg s,c;

input a,b;

always@(a or b)

begin

if(a==0 && b==0)

begin s=0;c=0; end

if(a==1 && b==0)

begin s=1;c=0; end

if(a==0 && b==1)

begin s=1;c=0; end

if(a==1 && b==1)

begin s=0;c=1; end

end

endmodule

Half adder in structural model:

module half_adder_s(S, C, A, B);

input A, B;
output S, C;
wire xor_out, and_out;
xor (xor_out, A, B);
assign S = xor_out;
and (and_out, A, B);
assign C = and_out;
 endmodule
Half adder in dataflow model:

module half_adder_ds(S, C, A, B);

input A, B;

output S, C;

assign S = A ^ B;

assign C = A & B;

endmodule

Testbench for Half adder:

module half_adder_tb_st();

reg a,b;

wire sum,carry;

half_adder ut(a,b,sum,carry);

initial begin

a=0;b=0;

#100

a=0;b=1;

#100

a=1;b=1;

#100

a=1;b=0;

#100;

$stop;

end

initial begin

$monitor("a=%d,b=%b,sum=%d,carry=%b",a,b,sum,carry);

end

endmodule

FULL ADDER:

DATA FLOW:

module FA_df(Sum, Cout, A, B, Cin);

input A, B, Cin;
 output Sum, Cout;

// Continuous assignments for sum and carry-out

assign Sum = A ^ B ^ Cin; // Sum is A XOR B XOR Cin

assign Cout = (A & B) | (Cin & (A ^ B)); // Carry-out calculation

endmodule

STRUCTURAL:

module FA_s(s,cy,a,b,c);

input a,b,c;

output s,cy;

wire s1,c1,c2;

xor g1(s1,a,b);

xor g2(s,s1,c);

and g3(c1,a,b);

and g4(c2,c,s1);

or g5(cy,c1,c2);

endmodule

BEHAVIOURAL:

module FA_b(s,cy,a,b,c);

input a,b,c;

output reg s,cy;

always @(a or b or c)

begin

if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

 if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

if(a==0 && b==0 && c==0)

begin s=0;cy=0; end

end

endmodule

TEST BENCH FOR FULL ADDER:

module full_adder_tb_bh();

reg a,b,c;

wire sum,carry;

FA_b utt(a,b,c,sum,carry);

initial begin

a=0;b=0;c=0;

#50

a=0;b=1;c=0;

#50a=0;b=1;c=1;

#50a=1;b=1;c=1;

#50a=1;b=1;c=0;

#50a=1;b=0;c=0;

#50a=1;b=0;c=1;

#50a=0;b=0;c=1;

#50;

$stop;

end

initial begin

$monitor("a=%d,b=%d,c=%d,sum=%d,carry=%d",a,b,c,sum,carry);

end

endmodule
RIPPLE CARRY ADDER:

module full_adder(

input a, b, cin,

output sum, cout

);

assign sum = a ^ b ^ cin;

assign cout = (a & b) | (b & cin) | (cin & a);

endmodule

module RCA_4bit(

input [3:0] a, b,

input cin,

output [3:0] sum,

output cout

);

wire [2:0] c;

full_adder fa0(a[0], b[0], cin, sum[0], c[0]);

full_adder fa1(a[1], b[1], c[0], sum[1], c[1]);

full_adder fa2(a[2], b[2], c[1], sum[2], c[2]);

full_adder fa3(a[3], b[3], c[2], sum[3], cout);

endmodule

TEST BENCH FOR RCA:

module rca_tb();

reg [3:0]a;

reg [3:0]b;

reg c;

wire [3:0]s;

wire carry;

rca h(a,b,c,s,carry);

initial begin

a=4'b0000;b=4'b0000; c=1;

#100 a=4'b1000;b=4'b1000; c=0;

#100 a=4'b1000;b=4'b1000; c=1;

#100 a=4'b1100;b=4'b1100; c=0;

#100 a=4'b1100;b=4'b1100; c=1;

 #100 a=4'b1110;b=4'b1111; c=0;

#100 a=4'b1110;b=4'b1111; c=1;

#100;

$stop;

end

initial begin

$monitor("a=%d,b=%d,c=%d,sum=%d,carry=%d",a,b,c,s,carry);

end

endmodule

HALF SUBSTRACTOR:

BEHAVIOURAL

module HS_b(d,bo,a,b);

input a,b;

output reg d,bo;

always@(a or b)

begin

if(a==0 && b==0)

begin d=0;bo=0; end

if(a==1 && b==0)

begin d=1;bo=0; end

if(a==0 && b==1)

begin d=1;bo=1; end

if(a==1 && b==1)

begin d=0;bo=0; end

end

endmodule

DATA FLOW

module HS_ds(d,bo,a,b);

input a,b;

output d,bo;

assign d= a^b;

assign bo= a & b;

endmodule
STRUCTURAL

module HS_s(d,bo,a,b);

input a,b;

output d,bo;

wire mid;

xor G1(d,a,b);

not G2(mid,a);

and G3(bo,mid,b);

endmodule

TEST BENCH FOR HALF SUBTRACTOR:

module half_sub_tb_dt();

reg a,b;

wire diff,bor;

HS_s w(a,b,diff,bor);

initial begin

a=0;b=0;

#100

a=0;b=1;

#100

a=1;b=1;

#100

a=1;b=0;

#100;

$stop;

end

initial begin

$monitor("a=%d,b=%d,diff=%d,bor=%b",a,b,diff,bor);

end

endmodule

FULL SUBTRACTOR:

DATA FLOW:

module FS_df (A,B,C,D,Bout);

 input A,B,C;

output D,Bout;

assign D = A ^ B ^ C;

assign Bout = (~A & (B | C)) | (B & C);

endmodule

STRUCTURAL:

module FS_s(a,b,c,d,bo);

input a,b,c;

output d,bo;

wire m1,m2,m3,m4,m5;

xor G1(m1,a,b);

not G2(m2,a);

and G3(m3,m2,b);

not G4(m4,m1);

xor G6(d,m1,c);

and G5(m5,c,m4);

or G7(bo,m3,m5);

endmodule

BEHAVIOURAL:

module FS_b(a,b,c,d,bo);

input a,b,c;

output reg d,bo;

always@(a or b or c)

begin

if( a==0 && b==0 && c==0)

begin d=0;bo=0; end

if( a==0 && b==0 && c==1)

begin d=1;bo=1; end

if( a==0 && b==1 && c==0)

begin d=1;bo=1; end

if( a==0 && b==1 && c==1)

begin d=0;bo=1; end

if( a==1 && b==0 && c==0)

begin d=1;bo=0; end

if( a==1 && b==0 && c==1)

begin d=0;bo=0; end

if( a==1 && b==1 && c==0)

begin d=0;bo=0; end

if( a==1 && b==1 && c==1)

begin d=1;bo=1; end

end

endmodule

TEST BENCH FOR FULL SUBTRACTOR:

module full_sub_tb_bh();

reg a,b,c;

wire diff,bor;

FS_b u(a,b,c,diff,bor);

initial begin

a=0;b=0;c=0;

#50

a=0;b=1;c=0;

#50a=0;b=1;c=1;

#50a=1;b=1;c=1;

#50a=1;b=1;c=0;

#50a=1;b=0;c=0;

#50a=1;b=0;c=1;

#50a=0;b=0;c=1;

#50;

$stop;

end

initial begin

$monitor("a=%d,b=%d,c=%d,diff=%d,bor=%d",a,b,c,diff,bor);

end

endmodule

4 – BIT PARALLEL SUBSTRACTOR:

module subtractor(a,b,c,d,bor);

input [3:0]a;
 input [3:0]b;

input c;

output [3:0]d;

output bor;

wire c1,c2,c3;

full_sub_st f(a[0],b[0],c,d[0],c1);

full_sub_st f1(a[1],b[2],c1,d[1],c2);

full_sub_st f2(a[2],b[2],c2,d[2],c3);

full_sub_st f3(a[3],b[3],c3,d[3],bor);

endmodule

TEST BENCH FOR 4 -BIT PARALLEL SUBSTRACTOR:

module subtractor_tb();

reg [3:0]a;

reg [3:0]b;

reg c;

wire [3:0]d;

wire bor;

subtractor h(a,b,c,d,bor);

initial begin

a=4'b0000;b=4'b0000; c=1;

#100 a=4'b1000;b=4'b1000; c=0;

#100 a=4'b1000;b=4'b1000; c=1;

#100 a=4'b1100;b=4'b1100; c=0;

#100 a=4'b1100;b=4'b1100; c=1;

#100 a=4'b1110;b=4'b1111; c=0;

#100 a=4'b1110;b=4'b1111; c=1;

#100;

$stop;

end

initial begin

$monitor("a=%d,b=%d,c=%d,d=%d,bor=%d",a,b,c,d,bor);

end

endmodule
Circuit diagram:

Half Adder

Full Adder

4-bit Parallel Adder:

TRUTH TABLES:
Half adder:
Simulation Waveform:

Hardware Output:

(a=1,b=0,sum=1,carry=0)
Full Adder: Simulation waveform:

Hardware Output:

RIPPLE CARRY Adder: Simulation waveform:

Hardware Output:

(a=0000,b=1111,c=1,sum=1110,carry=1

CIRCUITS:

HALF SUBTRACTOR:

FULL SUBTRACTOR:
4 BIT PARALLEL SUBTRACTOR:

TRUTH TABLE:

Half subtractor: Simulation waveform:

Hardware Output:

(a=0,b=1,diff=1,bor=1)

Full subtractor: Simulation waveform:

Hardware Output:

(a=1,b=1,c=1,diff=1,bor=1)

4-bit subtractor: Simulation waveform:

Hardware Output:

(a=1111,b=1111,c=1,diff=1111,bor=1)

Result:

Hence the logic circuits for the adders and subtractors are designed in Verilog HDL and the output combinations
are verified in VIVADO SOFTWARE using Basys 3 FPGA Board .