FM24C16A

16Kb FRAM Serial Memory

Features
Low Power Operation
16K bit Ferroelectric Nonvolatile RAM • 5V operation
• Organized as 2,048 x 8 bits • 150 µA Active Current (100 kHz)
• High Endurance (1012) Read/Write Cycles • 10 µA Standby Current
• 10 year Data Retention
• NoDelay™ Writes Industry Standard Configuration
• Advanced High-Reliability Ferroelectric Process • Industrial Temperature -40° C to +85° C
• 8-pin SOIC
Fast Two-wire Serial Interface
• Up to 1MHz maximum bus frequency
• Direct hardware replacement for EEPROM

Description Pin Configuration

The FM24C16A is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
NC 1 8 VDD
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a NC 2 7 WP
RAM. It provides reliable data retention for over 10
years while eliminating the complexities, overhead, NC 3 6 SCL
and system level reliability problems caused by SDA
VSS 4 5
EEPROM and other nonvolatile memories.

Unlike serial EEPROMs, the FM24C16A performs

write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The Pin Names Function
FM24C16A is capable of supporting 1012 read/write
SDA Serial Data/Address
cycles, or a million times more write cycles than
SCL Serial Clock
EEPROM.
WP Write Protect
These capabilities make the FM24C16A ideal for VDD Supply Voltage 5V
nonvolatile memory applications requiring frequent VSS Ground
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The Ordering Information
combination of features allows the system to write FM24C16A-S 8-pin SOIC
data more frequently, with less system overhead.

The FM24C16A provides substantial benefits to users

of serial EEPROM, and these benefits are available as
a hardware drop-in replacement. The FM24C16A is
available in an industry standard 8-pin SOIC and uses
a two-wire protocol. The specifications are
guaranteed over the industrial temperature range from
-40°C to +85°C.

This product conforms to specifications per the terms of the Ramtron Ramtron International Corporation
standard warranty. Production processing does not necessarily in- 1850 Ramtron Drive, Colorado Springs, CO 80921
clude testing of all parameters. (800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
Rev. 2.0 www.ramtron.com
July 2003 Page 1 of 13
 FM24C16A

Address 256 x 64
Counter
Latch FRAM Array

SDA ` Serial to Parallel

Data Latch
Converter

SCL
WP Control Logic

Figure 1. Block Diagram

Pin Description
Pin Name Type Pin Description
SDA I/O Serial Data Address: This is a bi-directional data pin for the two-wire interface. It
employs an open-drain output and is intended to be wire-OR’d with other devices on the
two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the
output driver includes slope control for falling edges. A pull-up resistor is required.
SCL Input Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on
the falling edge and clocked-in on the rising edge.
WP Input Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
VDD Supply Supply Voltage (5V)
VSS Supply Ground
NC - No connect

Rev 2.0
July 2003 Page 2 of 13
 FM24C16A

Overview Two-wire Interface

The FM24C16A is a serial FRAM memory. The The FM24C16A employs a bi-directional two-wire
memory array is logically organized as a 2,048 x 8 bus protocol using few pins and little board space.
memory array and is accessed using an industry Figure 2 illustrates a typical system configuration
standard two-wire interface. Functional operation of using the FM24C16A in a microcontroller-based
the FRAM is similar to serial EEPROMs. The major system. The industry standard two-wire bus is
difference between the FM24C16A and a serial familiar to many users but is described in this section.
EEPROM with the same pinout relates to its superior
write performance. By convention, any device that is sending data onto
the bus is the transmitter while the target device for
Memory Architecture this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
When accessing the FM24C16A, the user addresses
generating the clock signal for all operations. Any
2,048 locations each with 8 data bits. These data bits
device on the bus that is being controlled is a slave.
are shifted serially. The 2,048 addresses are accessed
The FM24C16A is always a slave device.
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
The bus protocol is controlled by transition states in
devices), a row address, and a segment address. The
the SDA and SCL signals. There are four conditions
row address consists of 8-bits that specify one of 256
including Start, Stop, Data bit, and Acknowledge.
rows. The 3-bit segment address specifies one of 8
Figure 3 illustrates the signal conditions that define
segments within each row. The complete 11-bit
the four states. Detailed timing diagrams are in the
address specifies each byte uniquely.
electrical specifications.
Most functions of the FM24C16A either are
controlled by the two-wire interface or handled
VDD
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Rmin = 1.8 KΩ
Unlike an EEPROM, it is not necessary to poll the Rmax = tR/Cbus
Microcontroller
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation is complete.
This is explained in more detail in the interface
SDA SCL SDA SCL
section below.
FM24C16A Other Slave
Device
Note that the FM24C16A contains no power
management circuits other than a simple internal Figure 2. Typical System Configuration
power-on reset. It is the user’s responsibility to ensure
that VDD is within data sheet tolerances to prevent
incorrect operation.

Rev 2.0
July 2003 Page 3 of 13
 FM24C16A

SCL

SDA 7 6 0

Stop Start Data bits Data bit Acknowledge

(Master) (Master) (Transmitter) (Transmitter) (Receiver)

Figure 3. Data Transfer Protocol

The receiver would fail to acknowledge for two

Stop Condition
distinct reasons. First is that a byte transfer fails. In
A stop condition is indicated when the bus master this case, the No-Acknowledge ends the current
drives SDA from low to high while the SCL signal is operation so that the part can be addressed again.
high. All operations using the FM24C16A must end This allows the last byte to be recovered in the event
with a Stop condition. If an operation is pending of a communication error.
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory Second and most common, the receiver does not
read) in order to assert a Stop condition. acknowledge to deliberately end an operation. For
Start Condition example, during a read operation, the FM24C16A
will continue to place data onto the bus as long as
A Start condition is indicated when the bus master
the receiver sends Acknowledges (and clocks).
drives SDA from high to low while the SCL signal is
When a read operation is complete and no more data
high. All read and write transactions begin with a
is needed, the receiver must not acknowledge the
Start condition. An operation in progress can be
last byte. If the receiver acknowledges the last byte,
aborted by asserting a Start condition at any time.
this will cause the FM24C16A to attempt to drive
Aborting an operation using the Start condition will
the bus on the next clock while the master is sending
prepare the FM24C16A for a new operation.
a new command such as a Stop.
If during operation the power supply drops below the Slave Address
specified VDD minimum, the system should issue a The first byte that the FM24C16A expects after a
Start condition prior to performing another operation. Start condition is the slave address. As shown in
Data/Address Transfer Figure 4, the slave address contains the device type,
the page of memory to be accessed, and a bit that
All data transfers (including addresses) take place
specifies if the transaction is a read or a write.
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
Bits 7-4 are the device type and should be set to
not change while SCL is high. For system design
1010b for the FM24C16A. The device type allows
considerations, keeping SCL in a low state while idle
other types of functions to reside on the 2-wire bus
improves robustness.
within an identical address range. Bits 3-1 are the
Acknowledge page select. They specify the 256-byte block of
The Acknowledge takes place after the 8th data bit has memory that is targeted for the current operation. Bit
been transferred in any transaction. During this state, 0 is the read/write bit. A 0 indicates a write
the transmitter should release the SDA bus to allow operation.
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.

Rev 2.0
July 2003 Page 4 of 13
 FM24C16A

Page
Slave ID Select
Memory Operation
The FM24C16A is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
1 0 1 0 A2 A1 A0 R/W higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C16A and a similar
Figure 4. Slave Address
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Word Address
After the FM24C16A (as receiver) acknowledges the Write Operation
slave ID, the master will place the word address on All writes begin with a slave ID then a word address
the bus for a write operation. The word address is the as previously mentioned. The bus master indicates a
lower 8-bits of the address to be combined with the 3- write operation by setting the LSB of the Slave
bits of the page select to specify the exact byte to be Address to a 0. After addressing, the bus master
written. The complete 11-bit address is latched sends each byte of data to the memory and the
internally. memory generates an acknowledge condition. Any
number of sequential bytes may be written. If the
No word address occurs for a read operation, though end of the address range is reached internally, the
the 3-bit page select is latched internally. Reads address counter will wrap from 7FFh to 000h.
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the Unlike other nonvolatile memory technologies, there
address following the previous access. A random read is no write delay with FRAM. The entire memory
address can be loaded by doing a write operation as cycle occurs in less time than a single bus clock.
explained below. Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
After transmission of each data byte, just prior to the polling, a technique used with EEPROMs to
acknowledge, the FM24C16A increments the internal determine if a write is complete is unnecessary and
address latch. This allows the next sequential byte to will always return a ‘ready’ condition.
be accessed with no additional addressing. After the
last address (7FFh) is reached, the address latch will An actual memory array write occurs after the 8th
roll over to 000h. There is no limit on the number of data bit is transferred. It will be complete before the
bytes that can be accessed with a single read or write acknowledge is sent. Therefore, if the user desires to
operation. abort a write without altering the memory contents,
this should be done using start or stop condition
Data Transfer
prior to the 8th data bit. The FM24C16A needs no
After all address information has been transmitted, page buffering.
data transfer between the bus master and the
FM24C16A can begin. For a read operation the The memory array can be write protected using the
device will place 8 data bits on the bus then wait for WP pin. Setting the WP pin to a high condition
an acknowledge. If the acknowledge occurs, the next (VDD) will write-protect all addresses. The
sequential byte will be transferred. If the FM24C16A will not acknowledge data bytes that are
acknowledge is not sent, the read operation is written to protected addresses. In addition, the
concluded. For a write operation, the FM24C16A will address counter will not increment if writes are
accept 8 data bits from the master then send an attempted to these addresses. Setting WP to a low
acknowledge. All data transfer occurs MSB (most state (VSS) will deactivate this feature.
significant bit) first.
Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.

Rev 2.0
July 2003 Page 5 of 13
 FM24C16A

By Master Start Address & Data Stop

S Slave Address 0 A Word Address A Data Byte A P

By FM24C16
Acknowledge

Figure 5. Single Byte Write

By Master Start Address & Data Stop

S Slave Address 0 A Word Address A Data Byte A Data Byte A P

By FM24C16
Acknowledge

Figure 6. Multiple Byte Write

There are four ways to properly terminate a read

Read Operation
operation. Failing to properly terminate the read will
There are two types of read operations. They are most likely create a bus contention as the FM24C16A
current address read and selective address read. In a attempts to read out additional data onto the bus. The
current address read, the FM24C16A uses the internal four valid methods are as follows.
address latch to supply the lower 8 address bits. In a
selective read, the user performs a procedure to set 1. The bus master issues a no-acknowledge in the
these lower address bits to a specific value. 9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
Current Address & Sequential Read the preferred method.
As mentioned above the FM24C16A uses an internal 2. The bus master issues a no-acknowledge in the
latch to supply the lower 8 address bits for a read 9th clock cycle and a start in the 10th.
operation. A current address read uses the existing 3. The bus master issues a stop in the 9th clock
value in the address latch as a starting place for the cycle. Bus contention may result.
read operation. This is the address immediately 4. The bus master issues a start in the 9th clock
following that of the last operation. cycle. Bus contention may result.

To perform a current address read, the bus master If the internal address reaches 7FFh it will wrap
supplies a slave address with the LSB set to 1. This around to 000h on the next read cycle. Figures 7 and
indicates that a read operation is requested. The 3 8 show the proper operation for current address reads.
page select bits in the slave ID specify the block of
memory that is used for the read operation. On the Selective (Random) Read
next clock, the FM24C16A will begin shifting out A simple technique allows a user to select a random
data from the current address. The current address is address location as the starting point for a read
the 3 bits from the slave ID combined with the 8 bits operation. It uses the first two bytes of a write
that were in the internal address latch. operation to set the internal address byte followed by
subsequent read operations.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read To perform a selective read, the bus master sends out
is simply a current address read with multiple byte the slave address with the LSB set to 0. This specifies
transfers. After each byte, the internal address counter a write operation. According to the write protocol, the
will be incremented. Each time the bus master bus master then sends the word address byte that is
acknowledges a byte this indicates that the loaded into the internal address latch. After the
FM24C16A should read out the next sequential byte. FM24C16A acknowledges the word address, the bus
master issues a start condition. This simultaneously
aborts the write operation and allows the read
Rev 2.0
July 2003 Page 6 of 13
 FM24C16A

command to be issued with the slave address set to 1. operation is illustrated in Figure 9.
The operation is now a current address read. This

No
By Master Start Address Acknowledge
Stop

S Slave Address 1 A Data Byte 1 P

By FM24C16 Acknowledge Data

Figure 7. Current Address Read

No
Start Address Acknowledge Acknowledge
By Master
Stop

S Slave Address 1 A Data Byte A Data Byte 1 P

By FM24C16 Acknowledge Data

Figure 8. Sequential Read

No
Start Address Start Address Acknowledge Acknowledge
By Master
Stop

S Slave Address 0 A Word Address A S Slave Address 1 A Data Byte A Data Byte 1 P

By FM24C16 Acknowledge Data

Figure 9. Selective (Random) Read

Endurance superior to EEPROM in all but one-time

programmable applications. The advantage is most
The FM24C16A internally operates with a read and
obvious in data collection environments where writes
restore mechanism. Therefore, endurance cycles are
are frequent and data must be nonvolatile.
applied for each read or write cycle. The FRAM
architecture is based on an array of rows and
The attributes of fast writes and high write endurance
columns. Rows are defined by A10-A3. Each access
combine in many innovative ways. A short list of
causes an endurance cycle for a row. Endurance can
ideas is provided here.
be optimized by ensuring frequently accessed data is
placed in different rows. Regardless, FRAM read and
1. Data collection. In applications where data is
write endurance is effectively unlimited at the 1MHz
collected and saved, FRAM provides a superior
two-wire speed. Even at 3000 accesses per second to
alternative to other solutions. It is more cost effective
the same row, 10 years time will elapse before 1
than battery backup for SRAM and provides better
trillion endurance cycles occur.
write attributes than EEPROM.

2. Configuration. Any nonvolatile memory can

Applications retain a configuration. However, if the configuration
The versatility of FRAM technology fits into many changes and power failure is a possibility, the higher
diverse applications. Clearly the strength of higher write endurance of FRAM allows changes to be
write endurance and faster writes make FRAM recorded without restriction. Any time the system
Rev 2.0
July 2003 Page 7 of 13
 FM24C16A

state is altered, the change can be written. This avoids 5. RF/ID. In the area of contactless memory, FRAM
writing to memory on power down when the available provides an ideal solution. Since RF/ID memory is
time is short and power scarce. powered by an RF field, the long programming time
and high current consumption needed to write
3. High noise environments. Writing to EEPROM EEPROM is unattractive. FRAM provides a superior
in a noisy environment can be challenging. When solution. The FM24C16A is suitable for multi-chip
severe noise or power fluctuations are present, the RF/ID products.
long write time of EEPROM creates a window of
vulnerability during which the write can be corrupted. 6. Maintenance tracking. In sophisticated systems,
The fast write of FRAM is complete within a the operating history and system state during a failure
microsecond. This time is typically too short for noise is important knowledge. Maintenance can be
or power fluctuation to disturb it. expedited when this information has been recorded.
Due to the high write endurance, FRAM makes an
4. Time to market. In a complex system, multiple ideal system log. In addition, the convenient 2-wire
software routines may need to access the nonvolatile interface of the FM24C16A allows memory to be
memory. In this environment the time delay distributed throughout the system using minimal
associated with programming EEPROM adds undue additional resources.
complexity to the software development. Each
software routine must wait for complete programming
before allowing access to the next routine. When time
to market is critical, FRAM can eliminate this simple
obstacle. As soon as a write is issued to the
FM24C16A, it is effectively done -- no waiting.

Rev 2.0
July 2003 Page 8 of 13
 FM24C16A

Electrical Specifications

Absolute Maximum Ratings

Symbol Description Ratings Notes
VDD Power Supply Voltage with respect to VSS -1.0V to +7.0V
VIN Voltage on any signal pin with respect to VSS -1.0V to +7.0V 1
and VIN < VDD+1.0V
TSTG Storage Temperature -55°C to +125°C
TLEAD Lead Temperature (Soldering, 10 seconds) 300° C
Note 1: The VIN < VDD+1.0V requirement does not apply to the SDA and SCL pins.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only,
and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol Parameter Min Typ Max Units Notes
VDD Main Power Supply 4.5 5.0 5.5 V
IDD VDD Supply Current 1
@ SCL = 100 kHz 115 150 µA
@ SCL = 400 kHz 400 500 µA
@ SCL = 1 MHz 800 1 mA
ISB Standby Current 1 10 µA 2
ILI Input Leakage Current 10 µA 3
ILO Output Leakage Current 10 µA 3
VIL Input Low Voltage -0.3 0.3 VDD V 4
VIH Input High Voltage 0.7 VDD VDD + 0.5 V 4
VOL Output Low Voltage
@ IOL = 3 mA 0.4 V
RIN Input Resistance (WP pin)
For VIN = VIL (max) 50 KΩ 5
For VIN = VIH (min) 1 MΩ
VHYS Input Hysteresis 0.05 VDD V 4
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to pins with pull down resistors.
4. This parameter is characterized but not tested.
5. The input pull-down circuit is strong (50KΩ) when the input voltage is below VIL and much weaker (1MΩ)
when the input voltage is above VIH.

Rev 2.0
July 2003 Page 9 of 13
 FM24C16A

AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol Parameter Min Max Min Max Min Max Units Notes
fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1
tLOW Clock Low Period 4.7 1.3 0.6 µs
tHIGH Clock High Period 4.0 0.6 0.4 µs
tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs
tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs
tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs
tSU:STA Start Condition Setup for Repeated 4.7 0.6 0.25 µs
Start
tHD:DAT Data In Hold Time 0 0 0 ns
tSU:DAT Data In Setup Time 250 100 100 ns
tR Input Rise Time 1000 300 300 ns 2
tF Input Fall Time 300 300 100 ns 2
tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs
tDH Data Output Hold 0 0 0 ns
(from SCL @ VIL)
tSP Noise Suppression Time Constant 50 50 50 ns
on SCL, SDA
Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.
1 The speed-related specifications are guaranteed characteristic points from DC to 1 MHz.
2 This parameter is periodically sampled and not 100% tested.

Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V)

Symbol Parameter Max Units Notes
CI/O Input/output capacitance (SDA) 8 pF 1
CIN Input capacitance 6 pF 1
Notes
1 This parameter is periodically sampled and not 100% tested.

AC Test Conditions
Input Pulse Levels 0.1 VDD to 0.9 VDD
Input rise and fall times 10 ns
Input and output timing levels 0.5 VDD

Equivalent AC Load Circuit

5.5V

1700 Ω
Output
100 pF

Rev 2.0
July 2003 Page 10 of 13
 FM24C16A

Diagram Notes
All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

tHIGH
tR tF tLOW tSP tSP

SCL
tSU:SDA 1/fSCL
tBUF tHD:DAT
tSU:D AT
SDA
tAA tDH
Start Stop Start Acknowledge

Write Bus Timing

tHD:DAT
SCL
tHD:STA tSU:DAT tAA
tSU:STO

SDA

Start Stop Start Acknowledge

Data Retention (VDD = 4.5V to 5.5V unless otherwise specified)

Parameter Min Units Notes
Data Retention 10 Years 1
Notes
1. The relationship between retention, temperature, and the associated reliability
level is characterized in a separate reliability report.

Rev 2.0
July 2003 Page 11 of 13
 FM24C16A

8-pin SOIC (JEDEC MS-012 variation AA)

Index
Area E H

Pin 1

D h
45 °
A
α
B .10 mm L C
e A1
.004 in.

Selected Dimensions
Refer to JEDEC MS-012 for complete dimensions and notes.
Controlling dimensions in millimeters.
Conversions to inches are not exact.

Symbol Dim Min Nom. Max

A mm 1.35 1.75
in. 0.053 0.069
A1 mm 0.10 0.25
in. 0.004 0.010
B mm 0.33 0.51
in. 0.013 0.020
C mm 0.19 0.25
in. 0.007 0.010
D mm 4.80 5.00
in. 0.189 0.197
E mm 3.80 4.00
in. 0.150 0.157
e mm 1.27 BSC
in. 0.050 BSC
H mm 5.80 6.20
in. 0.228 0.244
h mm 0.25 0.50
in. 0.010 0.197
L mm 0.40 1.27
in. 0.016 0.050
α 0° 8°

Rev 2.0
July 2003 Page 12 of 13
 FM24C16A

Revision History

Revision Date Summary

0.1 6/26/02 Initial Release
2.0 7/23/03 Changed to Production status.

Rev 2.0
July 2003 Page 13 of 13