Badih El-Kareh

Silicon Devices
and Process
Integration
Deep Submicron and Nano-Scale Technologies
Silicon Devices and Process Integration

Deep Submicron and Nano-Scale Technologies

Badih El-Kareh

Silicon Devices
and Process Integration
Deep Submicron and Nano-Scale
Technologies

ABC
Badih El-Kareh
Independent Consultant
Cedar Park, TX
USA
[email protected]

ISBN: 978-0-387-36798-9 e-ISBN: 978-0-387-69010-0

DOI: 10.1007/978-0-387-69010-0

Library of Congress Control Number: 2008936300

°c Springer Science+Business Media, LLC 2009

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Preface

State-of-the-art silicon devices and integrated process technologies are covered in

this book. The eight chapters represent a comprehensive discussion of modern
silicon devices, their characteristics, and the relationship between their electrical
properties and processing conditions. The material is compiled from industrial and
academic lecture-notes and reflects years of experience in the development of sili-
con devices.
The book is prepared specifically for engineers and scientists in semiconduc-
tor research, development and manufacturing. It is also suitable for a one-semester
course in electrical engineering and materials science at the upper undergraduate or
lower graduate level.
The chapters are arranged logically, beginning with a review of silicon properties
that lays the groundwork for the discussion of device properties, including mobility-
enhancement by straining silicon.
Junctions and contacts are inherent to practically all semiconductor devices.
Chapter 2 covers junctions under forward and reverse characteristics, including
high-level injection and high-field effects. Understanding the properties of contacts
has become increasingly important as the contact size is reduced to deep submicron
and nanoscale dimensions. The last part of Chap. 2 discusses ohmic and rectifying
contacts.
Chapter 3 begins with bipolar fundamentals and moves to an advanced treat-
ment of bipolar enhancements with silicon–germanium (SiGe). This chapter is par-
ticularly important to analog and mixed-signal applications where complementary
metal-oxide semiconductor (CMOS) and bipolar transistors are integrated in a BiC-
MOS process. It also benefits engineers in understanding important bipolar effects
in CMOS-only applications, such as subthreshold current and parasitic latch-up.
The metal-oxide silicon (MOS) capacitor is a key part of a metal-oxide semicon-
ductor field-effect transistor (MOSFET) and a powerful process and device charac-
terization tool. The physics and characterization of MOS structures are detailed in
Chap. 4, beginning with an ideal stack of a conductor, an insulator and silicon, and
gradually moving to real structures and quantum effects.

v
vi Preface

Chapter 5 deals with the insulated-gate field-effect transistor. It begins with a

description of the modes of transistor operation and the different transistor types.
Transistor current–voltage characteristics are detailed, followed by a discussion of
scaling the structure to smaller dimensions, scaling limitations, short-channel, re-
verse short-channel, narrow-channel, and reverse narrow-channel effects. Mobility
enhancement techniques are described, including strained silicon and optimization
of crystal orientation. The discussion extends to ultra-thin gate-oxide, high-K di-
electrics, advanced gate-stacks, and three-dimensional structures.
Analog devices and passive components are introduced in Chap. 6. As an exten-
sion of bipolar transistors detailed in Chap. 3, the properties of junction field-effect
transistors are described, followed by optimization of MOSFETs for analog appli-
cations. The design and properties of integrated precision resistors, capacitors, and
varactors are then detailed. The chapter concludes with the important topics of com-
ponent matching and noise.
Chapter 7 covers advanced enabling processes and process integration. It be-
gins with integrated CMOS and BiCMOS processes to illustrate typical sequences
of processing steps. Crystal growth and wafer parameters, including properties
of silicon-on-insulator (SOI), relevant to modern integrated processes are dis-
cussed. Front-end of the line unit processes include short-duration thermal pro-
cesses, atomic-lay deposition (ALD), ionized physical-vapor deposition (IPVD),
optical proximity correction (OPC), double exposure and patterning, immersion
lithography, and new silicides. Back-end of the line processes include copper in-
terconnects and low-K dielectrics.
The last chapter reviews selected CMOS and BiCMOS digital and memory ap-
plications. The inverter is used to analyze the important parasitic latch-up effect
and methods to suppress it. The second part covers memory cells, including dy-
namic random-access memory (DRAM), static random-access memory (SRAM),
and nonvolatile memory (NVM).
It would not have been possible for me to complete this book in its present
form without the continuous invaluable help with corrections and suggestions for
improvement and encouragement from Dr. Wendell Noble, independent consul-
tant, retired IBM semiconductor physicist, Professor Carlton Osburn of the North
Carolina State University, and Dr. Albert Puttlitz, IEEE-Components, Packaging
and Manufacturing Technology Society, VP of Education. I also thank my former
colleagues at IBM, Russell Houghton and Ashwin Ghatalia, for their reviews and
inputs. My special thanks to the personnel of the University of Texas library for
their kind support in my research.

August 18, 2008 Badih El-Kareh

Contents

List of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

1 Silicon Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Valence-Bond and Two-Carrier Concept . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.1 Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Energy Bands in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 Energy Band Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 Metals, Semiconductors and Insulators . . . . . . . . . . . . . . . . . . 10
1.3.3 Band Model for Impurities in Silicon . . . . . . . . . . . . . . . . . . . . 11
1.3.4 Energy Band Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.5 Effective Mass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4 Thermal Equilibrium Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.1 The Boltzmann Distribution Function . . . . . . . . . . . . . . . . . . . 18
1.4.2 Fermi-Dirac Distribution and Density of States . . . . . . . . . . . 18
1.4.3 Density of States and Carrier Distribution in Silicon . . . . . . . 20
1.4.4 Doped Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 Carrier Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1 Carrier Transport by Drift: Low Field . . . . . . . . . . . . . . . . . . . 29
1.5.2 Matthiesson’s Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.3 Carrier Transport by Drift: High Field . . . . . . . . . . . . . . . . . . . 37
1.5.4 Carrier Transport by Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.6 Nonequilibrium Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.6.1 Carrier Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.6.2 Diffusion Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.7 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2 Junctions and Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2 PN Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.1 Junction Profiles and Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

vii
viii Contents

2.2.2 Step-Junction Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.2.3 PN Junction at Thermal Equilibrium . . . . . . . . . . . . . . . . . . . . 64
2.2.4 PN Junction in Forward Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.2.5 PN Junction in Reverse Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.3 Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.3.1 Rectifying Contacts, Schottky Barrier Diode . . . . . . . . . . . . . 111
2.3.2 Current–Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 118
2.3.3 Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.4 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3 The Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
3.2 Transistor Action, a Qualitative Description . . . . . . . . . . . . . . . . . . . . 136
3.2.1 Nomenclature and Regions of Operation . . . . . . . . . . . . . . . . . 136
3.2.2 Idealized Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
3.2.3 Ebers-Moll Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
3.2.4 Collector Saturation Voltage, VCEsat . . . . . . . . . . . . . . . . . . . . . 142
3.3 Planar Transistor, Low-Level Injection . . . . . . . . . . . . . . . . . . . . . . . . . 143
3.3.1 Low-Level Injection Parameters . . . . . . . . . . . . . . . . . . . . . . . . 144
3.3.2 Collector-Base Reverse Characteristics . . . . . . . . . . . . . . . . . . 151
3.3.3 Emitter-Base Reverse Characteristics . . . . . . . . . . . . . . . . . . . . 156
3.3.4 Polysilicon Emitter and Interface Oxide . . . . . . . . . . . . . . . . . 158
3.3.5 Transistor Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
3.4 High-Level Injection Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
3.4.1 Base Conductivity Modulation . . . . . . . . . . . . . . . . . . . . . . . . . 172
3.4.2 Base-Push Effect (Kirk Effect) . . . . . . . . . . . . . . . . . . . . . . . . . 173
3.5 Frequency Response of Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . 175
3.5.1 Emitter Delay, τE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
3.5.2 Base Transit Time, τB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
3.5.3 Collector Delay, τC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
3.6 The Transistor as a Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.6.1 Delay Time, td . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3.6.2 Rise Time, tr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3.6.3 Storage Time, ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
3.6.4 Fall Time, t f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
3.7 Silicon-Germanium Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.7.1 SiGe Film Deposition and Properties . . . . . . . . . . . . . . . . . . . . 188
3.7.2 Bandgap Lowering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.7.3 Density of States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
3.7.4 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
3.7.5 Transistor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
3.7.6 Transistor Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
3.8 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Contents ix

4 The MOS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
4.2 Physics of an Ideal MOS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
4.2.1 Description of Semiconductor Surface Conditions . . . . . . . . . 215
4.2.2 Surface Charge and Electric Field . . . . . . . . . . . . . . . . . . . . . . 220
4.2.3 Approximations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
4.2.4 Excess Surface Carrier Concentrations . . . . . . . . . . . . . . . . . . 224
4.2.5 MOS Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
4.3 Calculation of Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
4.3.1 Calculation of Low-Frequency Capacitance . . . . . . . . . . . . . . 228
4.3.2 Description of the Low-Frequency CV-Plot . . . . . . . . . . . . . . 229
4.3.3 Calculation of High-Frequency Capacitance . . . . . . . . . . . . . . 237
4.4 Measurement of MOS Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
4.4.1 Low-Frequency, or Quasi-Static CV Measurement . . . . . . . . 239
4.4.2 High-Frequency CV Measurement . . . . . . . . . . . . . . . . . . . . . . 240
4.5 Non-Uniform Impurity Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
4.5.1 Profile Approximations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
4.5.2 Surface Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
4.6 Non-Ideal MOS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
4.6.1 Workfunction Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
4.6.2 Dielectric Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
4.7 Characterization and Parameter Extraction . . . . . . . . . . . . . . . . . . . . . 253
4.7.1 Extraction of Equivalent Oxide Thickness, teq . . . . . . . . . . . . 253
4.7.2 Workfunction Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
4.7.3 Extraction of Dopant Concentration . . . . . . . . . . . . . . . . . . . . . 255
4.7.4 Lifetime Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
4.7.5 Extraction of Interface-State Distribution . . . . . . . . . . . . . . . . 259
4.7.6 Extraction of Mobile Ion Concentration . . . . . . . . . . . . . . . . . 263
4.8 Carrier Transport Through the Dielectric . . . . . . . . . . . . . . . . . . . . . . . 264
4.8.1 Tunneling Through the Oxide . . . . . . . . . . . . . . . . . . . . . . . . . . 265
4.8.2 Avalanche Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
4.9 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

5 Insulated-Gate Field-Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.2 Qualitative Description of MOSFET Operation . . . . . . . . . . . . . . . . . . 273
5.3 Gate-Controlled PN Junction, or Gated Diode . . . . . . . . . . . . . . . . . . . 277
5.3.1 Junction at Equilibrium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
5.3.2 Reverse Biased Junction: Depleting Gate Voltage . . . . . . . . . 279
5.3.3 Reverse Biased Junction: Accumulating Gate Voltage . . . . . . 281
5.4 MOSFET Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
5.4.1 Long and Wide Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
5.4.2 Scaling to Small Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 304
x Contents

5.4.3 Short-Channel Effects, SCE . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

5.4.4 Reverse Short-Channel Effects, RSCE . . . . . . . . . . . . . . . . . . . 319
5.4.5 Narrow Channel Effects, NCE . . . . . . . . . . . . . . . . . . . . . . . . . 322
5.4.6 Reverse Narrow-Channel Effects, RNCE . . . . . . . . . . . . . . . . . 326
5.4.7 Small-Size Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
5.5 Mobility Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
5.5.1 Mean-Free Time Between Collisions, τ . . . . . . . . . . . . . . . . . . 331
5.5.2 Effective Mass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
5.6 Ultrathin Oxide and High-K Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . 340
5.6.1 High-K Dielectric Requirements . . . . . . . . . . . . . . . . . . . . . . . 341
5.6.2 High-K Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
5.7 Gate Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
5.7.1 Polysilicon Workfunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
5.7.2 Metal Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
5.8 Three-Dimensional Structures, FinFETS . . . . . . . . . . . . . . . . . . . . . . . 352
5.9 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

6 Analog Devices and Passive Components . . . . . . . . . . . . . . . . . . . . . . . . . . 369

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
6.2 Analog Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
6.2.1 Junction Field-Effect Transistor, JFET . . . . . . . . . . . . . . . . . . . 370
6.2.2 Analog/RF MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
6.2.3 Integrated Passive Components . . . . . . . . . . . . . . . . . . . . . . . . 385
6.3 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
6.3.1 MOSFET Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
6.3.2 Bipolar Transistor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
6.3.3 Resistor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
6.3.4 Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
6.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
6.4.1 Classification of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
6.5 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

7 Enabling Processes and Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
7.2 A Conventional CMOS Logic Process Flow . . . . . . . . . . . . . . . . . . . . 439
7.3 A BiCMOS Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
7.4 Advanced Enabling Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
7.4.1 Crystal Growth and Wafer Preparation . . . . . . . . . . . . . . . . . . 451
7.4.2 Short-Duration Thermal Processes . . . . . . . . . . . . . . . . . . . . . . 460
7.4.3 Thin-Film Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
7.4.4 Integration of Ultra-Shallow Junctions . . . . . . . . . . . . . . . . . . 479
7.4.5 Gate Stack Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Contents xi

7.5 Advanced Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

7.5.1 Copper Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
7.5.2 Low-K Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
7.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
8.2 Logic Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
8.2.1 The Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
8.2.2 The CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
8.2.3 The BiCMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
8.2.4 CMOS NAND and NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . 534
8.2.5 BiCMOS Two-Input NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
8.2.6 The Transmission Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
8.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
8.3.1 Dynamic Random-Access Memories, DRAM . . . . . . . . . . . . . 537
8.3.2 Static Random Access Memories, SRAM . . . . . . . . . . . . . . . . 546
8.3.3 Nonvolatile Memory, NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
8.3.4 BiCMOS for Analog/RF Applications . . . . . . . . . . . . . . . . . . . 566
8.4 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

Appendix A: Universal Physical Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Appendix B: International System of Units, SI . . . . . . . . . . . . . . . . . . . . . . . . . 577

Appendix C: The Greek Alphabet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Appendix D: Properties of Silicon and Germanium (300 K, Intrinsic

Semiconductor Unless Otherwise Stated) . . . . . . . . . . . . . . . . . . . . . . . . . 581

Appendix E: Conversion Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
List of Symbols

a acceleration (cm/s2 )
a JFET metallurgical channel width (cm)
a lattice constant (cm)
a voltage ramp-rate (V/s)
A geometry-dependent factor
A area (cm2 )
A∗ effective Richardson constant (A/cm2 · K2 )
AE emitter area (cm2 )
AC cross-sectional area (cm2 )
AΔR process-related resistor mismatch factor (cm)
AΔVT process-related threshold voltage-mismatch factor (cm)
AG gate area (cm2 )
AS surface area (cm2 )
b mobility ratio (μn /μp )
BL bit-line
BV breakdown voltage (V)
BVCBO collector-base breakdown voltage, emitter open (V)
BVCBS collector-base breakdown voltage, emitter-base shorted (V)
BVCEO collector-emitter breakdown voltage, base open (V)
BVDGO drain-gate breakdown voltage, source open (V)
BVDGS drain-gate breakdown voltage, source-gate shorted (V)
BVEBO emitter-base breakdown voltage, collector open (V)
BVEBS emitter-base breakdown voltage, collector-base shorted (V)
C capacitance per unit area (F/cm2 )
c velocity of light (2.998 × 1010 cm/s)
CBL bit-line capacitance (C)
CD diffusion capacitance per unit area (F/cm2 )
Cdecap decoupling capacitance (F)
Cdeep deep deletion capacitance per unit area, CV plot (F/cm2 )
CFG-CG capacitance between floating and control gate (F)

xiii
xiv List of Symbols

CGCh gate to channel capacitance per unit area (F/cm2 )

CGD gate to drain capacitance (F)
CGS gate to source capacitance (F)
CHF high-frequency capacitance per unit area, CV plot (F/cm2 )
Ci intrinsic capacitance, varactor (F)
CILD inter-level dielectric capacitance (F)
Cinv silicon inversion capacitance per unit area, CV plot (F/cm2 )
Cj junction capacitance (F)
CjE emitter-base junction capacitance (F)
CjC collector-base junction capacitance (F)
CL atomic concentration in liquid state (cm−3 )
CL load capacitance (F)
CLF low-frequency capacitance per unit area, CV plot (F/cm2 )
Cmax maximum capacitance per unit area, CV plot (F/cm2 )
Cmin minimum capacitance per unit area, CV plot (F/cm2 )
Cox oxide capacitance per unit area, CV plot (F/cm2 )
Cpar parasitic capacitance (F)
CPMD pre-metal dielectric capacitance (F)
Cpoly polysilicon, e.g., depletion capacitance per unit area, (F/cm2 )
CS atomic concentration in solid state (cm−3 )
CS storage node capacitance (F)
CSi silicon capacitance per unit area, CV plot (F/cm2 )
CSidep silicon depletion capacitance per unit area, CV plot (F/cm2 )
CSiFB silicon capacitance at flatband per unit area, CV plot (F/cm2 )
CSimin silicon minimum capacitance per unit area, CV plot (F/cm2 )
CSTI shallow-trench capacitance (F)
d distance (cm)
D diffusion constant (cm2 /s)
D̃ effective diffusion constant (cm2 /s)
Dn electron diffusion constant (cm2 /s)
Dp hole diffusion constant (cm2 /s)
E energy (eV)
E electric field (V/cm)
e tensile strain (Pa)
EC critical field (V/cm)
EC bottom of conduction band energy level (eV)
ECNL charge neutrality level (eV)
ED donor energy level (eV)
EF Fermi level (eV)
EFn electron quasi-Fermi level (eV)
EFp hole quasi-Fermi level (eV)
Eg energy gap (eV)
Egrad field induced by grading Ge profile (V/cm)
Ei intrinsic silicon energy level (eV)
List of Symbols xv

Ei ionization energy (eV)

Ei(A) acceptor ionization energy (eV)
Ei(D) donor ionization energy (eV)
En nitride field Qn ≈ 0 (V/cm)
Eox oxide field (V/cm)
EOO characteristic tunneling energy (eV)
EP phonon energy (eV)
Epeak peak electric field (V/cm)
Es surface field (V/cm)
ESi field in silicon (V/cm)
ET trap energy level (eV)
EV top of valence band energy level (eV)
Ex field in silicon normal to surface (V/cm)
Ey surface field parallel to silicon surface (V/cm)
F force (N)
F dimensionless electric field (F-function)
f frequency (Hz)
f (E) Fermi-function
fT gain-bandwidth product, cut-off frequency (Hz)
fmax maximum frequency of operation (Hz)
G constant
G bulk generation rate (cm−3 · s−1 )
gD channel (drain) conductance (S)
gD-lin linear channel (drain) conductance (S)
gD-sat saturated channel (drain) conductance (S)
gm transconductance (S)
gm-lin linear transconductance (S)
gm-sat saturated transconductance (S)
GR generation-recombination
G0 lumped JFET parameter
I current (A)
IB base current (A)
IB body current (A)
IBC base-collector current (A)
IBE base-emitter current (A)
IC collector current (A)
ICBO collector-base current, emitter open (A)
ICEO collector-emitter current, base open (A)
ICsat collector saturation current (A)
ID drain current (A)
IDiff diffusion current (A)
IDsat saturated drain current (A)
ID0 drain current per channel-square at threshold (A)
IE emitter current (A)
IEBO emitter-base current, collector open (A)