Scribd
Upload
41 views

EC2 2018 HomeWork03

Uploaded by

Viyaash Venkatesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
41 views

EC2 2018 HomeWork03

Uploaded by

Viyaash Venkatesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 8

Numerical calculation이 필요한 경우 다음의 parameter 들을 사용하시오.

VTN = |VTP| =1 V μnCox=100X10-6 μpCox=50X10-6


V’An = 20 V/m V’Ap = 10 V/m  npn=200  pnp=100

1. Assuming perfect symmetry and VA < . Draw the half circuit and compute the differen
tial voltage gain, (Vout1-Vout2)/(Vin1-Vin2), of each stage depicted below. (use gm, rπ, ro, β)
(a)

IEE

Vin1 Q1 Q2 Vin2
RL

Vout2 Vout1

Q3 Q4
R1 R1

(b)

M3 M4
R1 R1

Vout2 Vout1

Vin1 M1 M2 Vin2
RS RS

ISS
2. For the op-amp circuit shown below
(a) Find DC bias currents (I1~I3) and voltages (~ ) when input and input common-mode
voltage VICM is 2.5 V. Ignore the current mismatch resulted from the channel length
modulation effect.
(b) Determine the W/L of M3 transistor to maximize the output swing range of the op-amp.
(c) Find DC bias voltages (~ ) and allowable output swing range at .
(d) Compute the differential voltage gain (in1-in2)/(out1-out2). (Numerical calculation)
(e) Calculate CMRR when M7 and M8 have 2% mismatch in W/L ratios. (Numerical
calculation)
* Use the given parameters in the first page for the numerical calculations.

VDD = 5V

50/1 50/1 50/1 200/1


M1  M2 M4 M6
I3

400/1 400/1 VICM + in2
VICM + in1
M7 M8
VOCM + out2  VOCM + out1
W/L  50/1 50/1
M3 M9 M10
 
50uA
25/1 50/1 50/1
M5 M11 M12
I1 I2
3. Calculate the common-mode gain of the circuit shown below. Assume  > 0. gmro >>1, and use
the relationship Av = -GmRout.
4. Consider the circuit shown below, where the inputs are tied to a common-mode level. Assume
M1 and M2 are identical and so are M3 and M4.
(a) Neglecting channel length modulation, calculate the voltage at node N.
(b) Invoking symmetry, determine the voltage at node Y.
(c) What happens to the results obtained in (a) and (b) if VDD changes by a small amount V?

5. Find the MOS differential pair size, (W/L)1 and (W/L)2, for Vin,max=0.3V and a power budget
of 3 mW. Assume RD=500, =0, nCox=100 A/V2, and VDD=1.8V.
6. In this circuit, find the IEE, R1, and R2 for a gain of 100 and a power budget of 1 mW. Assume
R1 = R2, VA,n=10V, VA,p=5V, and VCC=2.5V.

7. Decide the transistor size, (W/L)1, (W/L)2, (W/L)3, and (W/L)4, for a voltage gain of 20 and a
power budget of 1 mW with VDD=1.8V. Assume M1 operates at the edge of saturation if the
input common-mode level is 1 V. Also, nCox=2pCox=100 A/V2, VTH,n=0.5V, VTH,p=-0.4V,
n=0.5p=0.1V-1.
8. In the circuit shown below, I1=I0cost+I0 and I2=-I0cost+I0. Plot waveforms at X and Y and
determine their peak-to-peak swings and common-mode level.

9. In this circuit, IEE=1mA and VA=5V. Calculate the voltage gain of the circuit. Note that the
gain is independent of the tail current.

10. Consider the circuit shown below, where IEE=2mA, VA,n=5V and VA,p=4V. What value of
R1=R2 allows a voltage gain of 50?
11. Assuming perfect symmetry and VA < , compute the differential voltage gain of each stage
depicted below.

12. Calculate the differential voltage gain of the circuits depicted below. Assume perfect symmetry
and  > 0.
13. Calculate the differential voltage gain of the circuits depicted below. Assume perfect symmetry
and  > 0. You may need to compute the gain as A=-GmRout in some cases.

14. We wish to design the stage shown below for a voltage gain of 100. If VA,n=5V, what is the
required Early voltage for the pnp transistors?

15. Sedra/Smith Microelectronic Circuit Sixth Edition Problems: 7.1, 7.2, 7.5, 7.16, 7.17, 7.19, 7.20

You might also like