Digital Design

CS302
Ref: Digital Design. M. Morris Mano , and Michael D. Ciletti.
Pearson, FIFTH EDITION, 2013
Combinational
Logic
CHAPTER 4 (PART2)
4.6 DECIMAL ADDER
A decimal adder requires a minimum of nine
inputs and five outputs, since
◦ four bits are required to code each decimal
digit and
◦ the circuit must have an input and output
carry
Since each input digit does not exceed 9, the
output sum cannot be greater than 19 (9 + 9 + 1),
the 1 in the sum being an input carry

Chapter 4- 3
Binary-Coded Decimal BCD
The code most
commonly used for the
decimal digits is the
straight binary
assignment.
This scheme is called
binary-coded decimal
and is commonly
referred to as BCD.

Chapter 4-
4
Binary-Coded Decimal (BCD)
Suppose we add the BCD digits as if they were
binary numbers. Then the binary sum will
produce a result in the range from 0 to 19.

Chapter 4- 5
BCD Adder
In binary, this range will be from 0000 to 10011.
In BCD, it is from 0000 to 1 1001, with the first 1
being a carry and the next four bits being the BCD
sum.
Although the other four bits are less than 1001, the
binary sum requires a correction because of the
carry by adding 0110 (6 =16-10).
This is because a carry in the most significant bit
position of the binary sum and a decimal carry
differ by 16 - 10 = 6
Chapter 4- 6
BCD Adder
The addition of two n-digit unsigned BCD numbers
follows the same procedure.
Consider the addition of 184 + 576 = 760 in BCD:

Chapter 4- 7
BCD Adder
BCD adder : performs operations on number
stored in B C D form.
- Four Xi (input): X8 , X 4 , X 2 , X 1
- Four Yi (addend input): Y8 , Y4 , Y2 , Y1
◦ The sum will be stored in Z8 , Z4 , Z2 , Z1
The basic adder consists of base-16 addition
while the intent is to perform base-10 addition
Thus 2 modifications are required:
◦ generate carries
◦ Correct sums greater than 9.
Chapter 4- 8
C= K+ Z8 Z4 + Z8 Z2
Chapter 4- 9
C= K+Z8 Z4 + Z8 Z2

Chapter 4- 10
 4.7 Binary Multiplier
For J multiplier bits and K multiplicand bits, we
need (J x K) AND gates and (J - 1) K-bit adders to
produce a product of J + K bits.

J=3, B3 B2 B1 B0
K=4 A2 A1 A0
(12) AND gates A0B 3 A0B 2 A0B 1 A0B 0
(2) 4-bit adders A1B 3 A1B 2 A1B 1 A1B 0
A2B 3 A2B 2 A2B 1 A2B 0
C6 C5 C4 C3 C2 C1 C0

Chapter 4- 11
Binary
Multiplier
For 3
multiplier
bits and 4
multiplicand
bits

Chapter 4- 12
Gate implementation For 4 bit adder

Chapter 4- 13
Chapter 4- 14
Chapter 4- 15
Chapter 4- 16
Chapter 4- 17
4-bit by 4-bit multiplication

Chapter 4- 18
Chapter 4- 19
4.8 MAGNITUDE
COMPARATOR
A magnitude comparator is a combinational circuit
that compares two numbers A and B and
determines their relative magnitudes.

The outcome of the comparison is specified by

three binary variables that indicate whether
A > B, A = B, or A < B.

Chapter 4-
20
Chapter 4- 21
Build a one-bit comparator
B 0 1
A A>B : AB'
0 A=B A<B
A=B : A'B' + AB
1 A>B A=B
A<B : A'B

A
A>B

B A=B

A<B

Chapter 4- 22
Four-bit comparator
Consider two numbers, A and B , with four digits each.
A = A3 A2 A1 A0 and B = B3 B2 B1 B0
The two numbers are equal if all pairs of significant digits are
equal:
A3 = B3 , A2 = B2 , A1 = B1, and A0 = B0 .
When the numbers are binary, the digits are either 1 or 0, and
the equality of each pair of bits can be expressed logically with an
exclusive-NOR function as
xi = Ai Bi + Ai ' Bi ' = Ai' Bi NOR Ai Bi ' for i = 0, 1, 2, 3
where xi = 1 only if the pair of bits in position i are equal

Chapter 4-
23
Four-bit comparator
For equality to exist, all xi variables must be equal to 1, a
condition that dictates an AND operation of all variables:
(A = B)= x3 x2 x1 x0
To determine whether A is greater or less than B , we inspect
the relative magnitudes of pairs of significant digits, starting
from the most significant position.
If the two digits of a pair are equal, we compare the next
lower significant pair of digits.
The comparison continues until a pair of unequal digits is
reached.

Chapter 4-
24
Four-bit comparator
To determine whether A is greater or less than B , we inspect the
relative magnitudes of pairs of significant digits, starting from the
most significant position.
If the two digits of a pair are equal, we compare the next lower
significant pair of digits.
The comparison continues until a pair of unequal digits is reached.
If the corresponding digit of A is 1 and that of B is 0, we conclude
that A > B. If the corresponding digit of A is 0 and that of B is 1, we
have A < B. The sequential comparison can be expressed logically by
the two Boolean functions
(A > B ) = A3 B’3 + x3 A2 B’2 + x3 x2 A1 B’1 + x3 x2 x1 A0 B’0
(A < B ) = A’3 B3 + x3 A’2 B2 + x3 x2 A’1 B1 + x3 x2 x1 A’0 B0
Chapter 4- 25
Four-bit comparator

Page 192,
4.1 a,b, 4.2, 4.3, 4.4, 4.6 a, 4.7 a, 4.8 a, 4.9, 4.10

Chapter 4-
26
(A < B ) = A’3 B3 + x3 A’2 B2 + x3
x2 A’1 B1 + x3 x2 x1 A’0 B0

(A > B ) = A3 B’3 + x3 A2 B’2 + x3

x2 A1 B’1 + x3 x2 x1 A0 B’0

(A = B)= x3 x2 x1 x0

Chapter 4-
27
Chapter 4- 28
4.9 DECODERS
A decoder converts binary information from n
input lines to a maximum of 2n output lines.

The decoders presented here are called

n-to-m-line decodes, where m <= 2n.

Purpose: generate the 2n (or fewer) mintems of n

input variables.

Chapter 4- 29
A decoder is a circuit which has n inputs and 2n outputs, and
outputs 1 on the wire corresponding to the binary number
represented by the inputs.

Chapter 4- 30
Chapter 4- 31
Implement the Decoder using AND gates
(the outputs and the ENABLE input are active-high and each
realization should be equivalent to a sum of minterms)

Chapter 4- 32
Using NAND and NOR gates only to build logic circuits is a
good thing to do (as it is desirable to construct circuits with
less number of transistors)

• a 2-inputs NAND gate can be constructed using

4transistors (2n for n-inputs) while a 2-inputs AND gate
requires 6 transistors (2n+2 for n-inputs).

• Also, a 2-input OR gate requires 6 transistors (2n+2 for

n-inputs) while a NOR gate requires only 4 Transistor (2n
for n-inputs).

Chapter 4- 33
Chapter 4- 34
Implement the Decoder using NAND gates (the outputs are
active-low and the ENABLE input is active-high and each
realization should be equivalent to a sum of minterms)

E A B D0 D1 D2
0 x x 1 1 1
1 0 0 0 1 1
Chapter 4- 35
1 0 1 1 0 1
Implement the Decoder using NOR gates (the outputs are
active-low and the ENABLE input is active-high and each
realization should be equivalent to a sum of minterms)

E A B D0 D1
1 x x 1 1
Chapter 4- 36
When w = 0, the top decoder is enabled and the other is disabled.
◦ The bottom - decoder outputs all 0's, and
◦ the top eight outputs generate minterms 0000 to 0111.
When w =1, the bottom decoder outputs generate minterms 1000 to
1111, while the outputs of the top decoder are all 0’s.

Chapter 4- 37
 4x16 decoder using two 3x8 decoders
w x y z

0 0 0 0 0000

0 0 0 1 0001

0 0 1 0 0010

0 0 1 1 0011

0 1 0 0 0100

0 1 0 1 0101

0 1 1 0 0110

0 1 1 1 0111

1 0 0 0 1000

1 0 0 1 1001

1 0 1 0 1010

1 0 1 1 1011

1 1 0 0 1100

1 1 0 1 1101

1 1 1 0 1110

1 1 1 1 1111

Chapter 4- 38
Combinational Logic Implementation
Implementing a combinational circuit by means of
a decoder and OR gates requires that
◦ the Boolean function be expressed as a sum of
minterms.
◦ A decoder is then chosen that generates all the
minterms of the input variables.
◦ The inputs to each OR gate are selected from the
decoder outputs according to the list of minterms of
each function.

Chapter 4-
39
Chapter 4- 40
Full Adder

S(x, y, z) = Σ (1, 2, 4, 7 )
C (x, y, z) = Σ (3, 5, 6, 7 )

Chapter 4- 41
4.10 ENCODERS
Encoding - the opposite of decoding - the
conversion of an m-bit input code to a n-bit output
code with n ≤ m ≤ 2n such that each valid code
word produces a unique output code
Circuits that perform encoding are called encoders
An encoder has 2n (or fewer) input lines and n
output lines which generate the binary code
corresponding to the input values

Chapter 4- 42
z = D1+ D3 + D5 + D7
y = D2 + D 3 + D 6 + D 7
x = D 4 + D5 + D6 + D7,

Chapter 4- 43
Priority Encoder
A priority encoder is an encoder circuit that
includes the priority function. The operation of the
priority encoder is such that if two or more inputs
are equal to 1 at the same time, the input having
the highest priority will take precedence.

Chapter 4- 44
Priority Encoder

Chapter 4- 45
Chapter 4- 46
Chapter 4- 47
Chapter 4- 48
 4.11 MULTIPLEXERS
A multiplexer selects information from an input line and
directs the information to an output line
Normally, a multiplexer has
1. 2n inputs (I2n − 1, … I0), ( 2n information)
2. n control inputs (S0 , …, Sn − 1) (selection inputs), and
3. one output Y
A multiplexer can be designed to have m information
inputs with m <= 2n as well as n selection inputs

Chapter 4- 49
2-to-1-Line Multiplexer
Since 2 = 21, n = 1
The single selection variable S has two values:
◦ S = 0 selects input I0
◦ S = 1 selects input I1
Y = I0 S’+ SI1

Chapter 4-
50
2-to-1-Line Multiplexer (Y = I0 S’+ SI)

Chapter 4- 51
4-to-1-line multiplexer
Each of the four inputs, I0 through I3, is applied to one
input of an AND gate.
Selection lines S1 and S0 are decoded to select a
particular AND gate.
The outputs are applied to a single OR gate .
A multiplexer is also called a data selector, since it
selects one of many inputs and steers the binary
information to the output line.

Chapter 4-
52
Chapter 4-
53
Chapter 4- 54
Implement the multiplexer using a
decoder
In general, a 2n -to-1-line multiplexer is constructed from an
n -to-2n decoder by adding 2n input lines to it, one to each
AND gate.

The outputs of the AND gates are applied to a single OR

gate. The size of a multiplexer is specified

Chapter 4-
55
 Implement the multiplexer using a
decoder (cont’)
A decoder is a circuit which has n inputs and 2n outputs, and outputs 1 on the wire
corresponding to the binary number represented by the inputs. For example, a 2-4
decoder might be drawn like this:

Chapter 4- 56
 Implement the multiplexer using a
decoder (cont’)
We can immediately see that

i.e. each of the d outputs corresponds to one of the four minterms.

Chapter 4- 57
Implement the multiplexer using a
decoder (cont’)
The Decoder Circuit:
The following circuit generates all four minterms
from two inputs, and implements the 2-4
decoder.

Chapter 4- 58
 Implement the multiplexer using a
decoder (cont’)
Multiplexers
A multiplexer is a device which allows one of a number of inputs to be routed to a
single output. Here is a 4-1 multiplexer.

The control inputs c0 and c1 represent a 2-bit binary number, which determines
which of the inputs i0-i3 is connected to the output d.

If c1c0 represents the number n in binary, then the value of the output d is the
value of input in.
Chapter 4- 59
Implement the multiplexer using a
decoder (cont’)
The implementation of a multiplexer is straightforward,
and uses a decoder. Here is a 4-1 multiplexer.

Chapter 4- 60
 Implement the multiplexer using a
decoder (cont’)
All the outputs of the decoder are 0, apart from one. The inputs c1c0 determine which
of the outputs is non-zero. All but one of the AND gates have 0 on one input and
therefore output 0.

The remaining AND gate has 1 on one input and in (where n is represented in binary
by c1c0) on the other input. The output of this AND gate is the value of in.

The OR gate has 0 on all of its inputs apart from one, and has the value of in on the
remaining input. The output of the OR gate is therefore the value of in.

Larger multiplexers can be implemented in the same way.

Chapter 4- 61
 Boolean Function Implementation
It was shown that a decoder can be used to implement
Boolean functions by employing external OR gates.
The minterms of a function are generated in a
multiplexer by the circuit associated with the selection
inputs.
The individual minterms can be selected by the data
inputs, thus providing a method of implementing a
Boolean function of n variables with a multiplexer that
has n selection inputs and 2n data inputs, one for each
minterm.
Chapter 4-
62
Implement a
Multiplier
Using
active-low
ENABLE input
and only one
select signal that
selects one
output from one
input group
(either group A
or group B)

Chapter 4- 63
Decoder - Demultiplexer
A decoder with enable input can function as a demultiplixer
A demultiplixer circuit that receives information from a
single Line and directs it to one of 2n possible outputs lines
The selection of a specific output is controlled by the bit
combination of n selection lines.
The preceding decoder can function as a one-to-four-line
demultiplexer when E is taken as a data input line and A
and B are taken as the selection inputs.

Chapter 4- 64
 Demultiplexe
rswith an enable input can function as a Demultiplexer.
• A decoder

• A demultiplexer is a circuit that receives information on a single line and

transmits this information on one of 2n possible output lines.

• Selection of a specific output line is controlled by the bit values of n

selection lines.

• E line is taken as a data input line and line A & B are taken as the
selection lines.

• Example from truth table, AB=10 output D2 will be same as the input E
Chapter 4- 65
Demultiplexer
(implemented using a
decoder)

Chapter 4- 66
4.1 , 4.2, 4.4, 4.5, 4.6 a, 4.7a, 4.9,4.10
4.11,4.12,4.12(a),4.15, 4.16 (first part)
4.21, 4.23
4.25 → 4.28,4.31, 4.32
Ngw:1 , 4.2, 4.4, 4.5, 4.6 a, 4.7a, 4.9,4.10
4.11,4.12,4.12(a),4.15, 4.16 (first part)
4.21, 4.23

Chapter 4-
67