EXPERT WORKSHOP SERIES

Part 1: Line Differential Protection Basics

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Agenda

1 Line Differential Protection Principle

2 Multi-Ended Line Differential Applications

3 SIPROTEC 5 Line Differential Protection

• Data alignment
• Stabilization methods
• Protection stages

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Line differential protection principle
History

• 1896 patent DRP92442 (d.c. differential, balanced beams)

• 1899 Schuckert: patent DRP110166 (local line differential)
• 1900 Schuckert: patent DRP113521 (~, balanced beams)
• 1904 Merz & Price: patent GB190403896A (pilot wire)

(source: DEPATISnet)

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Line differential protection principle
History

Electro - mechanical relays Analog electronic relays Digital processing relays

(1910 – 1980) (1960 – 1990) (1997)

Sensitive Differential relay, Siemens RYDSA20, ASEA 7SD502, Siemens

(source: W. Schossig, Netzschutzmagazin) (source: W. Schossig, Netzschutzmagazin)

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Line Differential
Protection principle

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Line Differential Protection Principle

Advantages Disadvantages
• No voltage transformer (VT) needed – only CT‘s • Communication channel required
• 100% of line protected without time delays • Fast
• Suitable for: • Reliable
• (Short) cables and overhead lines • Supervision of communication channel
• Multi-ended lines (tapped lines) • No backup protection for external equipment
• In-zone transformer applications • Following lines, transformers, …
• Series compensated lines • Only „in-zone“, defined by CT locations
• No impact of parallel lines
• No impact of power swings
• All kinds of network grounding
• Sensitive for high resistive and arcing faults
• Simple relay settings

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Line Differential Protection Principle

• Protected zone/object is defined by CT locations → „selectivity“

• Comparison of local phase current and remote end(s) phase current 1st Kirchhoff‘s current law:
• Fundamental frequency current phasors (Fourier filters)
෍ 𝐼𝑛 = 0
• Current measurement towards protected object (line, transformer, …) 𝑛
• No operation delay needed → „instantaneous“ 𝐼1 𝐼2
• Communication link required between line end(s)
𝐼3

𝐼𝐴 𝐼𝐵
A B
𝐼𝑙𝑖𝑛𝑒
protected zone

87L 87L
communication link
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Line Differential Protection Principle
Im

• Normal load condition CTA error

• Small CT errors 𝐼𝐵 𝐼𝐴
(phase, amplitude)
• Small differential current 𝐼𝑑𝑖𝑓𝑓 ≈ 0 Re
෍ 𝐼𝑛 = 𝐼𝑑𝑖𝑓𝑓 𝐼𝐵
𝑛 CTB error

𝐼𝑑𝑖𝑓𝑓 = 𝐼𝐴 + 𝐼𝐵

𝐼𝐴 𝐼𝐵
A B
𝐼𝑙𝑜𝑎𝑑

87L 87L
communication link
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Line Differential Protection Principle
Im

• External fault condition CTA error

• Differential current due to 𝐼𝐴
CT errors to consider
(phase, amplitude) Re
෍ 𝐼𝑛 = 𝐼𝑑𝑖𝑓𝑓 𝐼𝐵 𝐼𝑑𝑖𝑓𝑓 ≈ 0
• CT saturation ?
𝑛 CTB error
• Stabilization needed
𝐼𝑑𝑖𝑓𝑓 = 𝐼𝐴 + 𝐼𝐵

𝐼𝐴 𝐼𝐵
A B
𝐼𝑓

ext. fault
87L 87L
communication link
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Line Differential Protection Principle
Im

• Internal fault condition

𝐼𝐵
• High differential current 𝐼𝐴
𝐼𝑑𝑖𝑓𝑓
• Operate / Trip required
𝐼𝐵 Re
෍ 𝐼𝑛 = 𝐼𝑑𝑖𝑓𝑓
𝑛

𝐼𝑑𝑖𝑓𝑓 = 𝐼𝐴 + 𝐼𝐵

𝐼𝐴 𝐼𝐵
A B
𝐼𝑓

int. fault
87L 87L
communication link
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Line Differential Protection Principle
Im
𝑈𝐴

• Capacitive charging current

• Differential current equals 𝐼𝐴 𝐼𝐶
𝐼𝑑𝑖𝑓𝑓
line charging current
𝐼𝑙𝑖𝑛𝑒 𝐼𝐶
• Stabilization required 𝐼𝐵 −𝐼𝐵 Re
෍ 𝐼𝑛 = 𝐼𝑑𝑖𝑓𝑓
𝑛

𝐼𝑑𝑖𝑓𝑓 = 𝐼𝐴 + 𝐼𝐵 = ෍ 𝐼𝐶

𝐼𝐴 𝐼𝐵
A 𝑍𝐿 B
𝐼𝑙𝑖𝑛𝑒

𝐼𝐶 𝐼𝐶
𝐶 𝐶
𝑈𝐴 2 2
87L 87L
communication link
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Line differential protection principle
Conventional dual-slope differential characteristic
single fed fault
Dual-slope
characteristic
Idiff characteristic
• Dual-slope characteristic
m2
• m1 – covers measuring errors 𝐼𝑑𝑖𝑓𝑓 = 𝐼𝐴 + 𝐼𝐵
TRIP influence by
• m2 – covers also signal distortion
CT saturation
(low CT saturation) 𝐼𝑟𝑒𝑠𝑡 = 𝐾 ⋅ 𝐼𝐴 + 𝐼𝐵 m1
• Factor 𝐾 depends on vendor CT measuring
Idiff> STABILIZE
• Changeover setting: 𝐼𝑠𝑒𝑡 errors
Line charging
currents
Iset Irest
𝐼𝐴 𝐼𝐵
A 𝑍𝐿 B
𝐼𝑙𝑖𝑛𝑒

𝐼𝐶 𝐼𝐶
𝐶 𝐶
𝑈𝐴 2 2
87L 87L
communication link
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Line differential protection principle
Adaptive restrained differential characteristic – 7SD5/6/8
m=1
Idiff 7SD
• Single slope characteristic characteristic
• Fixed 45° slope TRIP
• Adaptive restraining current
(incl. measuring errors, signal distortion)
𝐼𝑑𝑖𝑓𝑓,𝑝ℎ = 𝐼𝐴,𝑝ℎ + 𝐼𝐵,𝑝ℎ Idiff> STABILIZE

𝐼𝑟𝑒𝑠𝑡,𝑝ℎ = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐

𝑛 𝑛 Irest
𝐼𝐴 𝐼𝐵
A 𝑍𝐿 B
𝐼𝑙𝑖𝑛𝑒

𝐼𝐶 𝐼𝐶
𝐶 𝐶
𝑈𝐴 2 2
87L 87L
communication link
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Line differential protection principle
Phase comparison principle – 7SD80

• Only exchange of currents polarity (positive sign of fundamental current component)

• Lower Bandwidth requirements → powerline communication (PLC) sufficient
• Current amplitude information gets lost (only used for min. current release) → Less accuracy

Mark Space Mark Space Space Mark Space Mark

𝐼𝐴 𝐼𝐵
A B
𝐼𝑓
Legacy technology:
Mark Mark Mark Mark t
Information “compression”
ext. fault 3ph currents → one current
Combined binary signal: Only “Marks” → no tripping
low bandwidth signal (e.g. neg. sequence
87L 87L
communication link
Small phase differences must be tolerated → setting parameter current 𝐼2 )

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Line differential protection principle
Phase comparison principle – 7SD80

• Only exchange of currents polarity (positive sign of fundamental current component)

• Lower Bandwidth requirements → powerline communication (PLC) sufficient
• Current amplitude information gets lost (only used for min. current release) → Less accuracy

Mark Space Mark Space Mark Space Mark Space

TRIP
𝐼𝐴 𝐼𝐵
A B STABILIZE
𝐼𝑓
180° 0°
Δ𝜑𝑠𝑒𝑡
Mark Space Mark Space t
int. fault
Combined binary signal: “Marks” and “Spaces” → Tripping
87L 87L

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Line differential protection principle
Alpha plane characteristic
𝐼𝑟𝑒𝑚𝑜𝑡𝑒
𝐼𝑝ℎ,𝑟𝑒𝑚𝑜𝑡𝑒 𝐼2,𝑟𝑒𝑚𝑜𝑡𝑒 𝐼0,𝑟𝑒𝑚𝑜𝑡𝑒 ℑ
• Evaluation of the current ratio or or 𝐼𝑙𝑜𝑐𝑎𝑙
𝐼𝑝ℎ,𝑙𝑜𝑐𝑎𝑙 𝐼2,𝑙𝑜𝑐𝑎𝑙 𝐼0,𝑙𝑜𝑐𝑎𝑙
• Principle is similar to phase comparison
1
• Considering also current amplitudes (ratio limits: 𝑅 and ) STABILIZE TRIP
𝑅
• Fundamental current component (DFT) calculation
• Stabilization required for 𝐼𝑟𝑒𝑚𝑜𝑡𝑒
𝛼 ℜ
• External faults with CT saturation 𝐼𝑙𝑜𝑐𝑎𝑙
1
180° 1 0°
𝑅

A 𝐼𝐴 𝐼𝐵 B

TRIP

87L 87L 𝑅
communication link

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Multi-Ended Line
Differential Applications

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Multi Ended Line Differential Applications
Tapped Line Application

• DER connected to existing lines 87L 87L

• Smaller generation (wind, PV) 𝑆𝑙𝑜𝑎𝑑
A B
• Smaller / rural load centers
𝑅𝑓
𝐼𝑓
𝐼𝐴 𝐼𝐵
• Differential current setting above infeed
• Reduced sensitivity for fault currents

• High load current at line → high restraining currents

• Reduced sensitivity for high impedance faults

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Multi Ended Line Differential Applications
Tapped Line Application

• Larger DER connected to existing lines 87L 87L

• Higher load centers
A B
• Multi-ended line differential protection
• Communication required to all line ends
D C
87L 87L

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Multi Ended Line Differential Applications
Chain or Ring Topology
𝐼𝐷 + 𝐼𝐶 + 𝐼𝐵 𝐼𝐴
• Chain or Ring topology 87L
1
87L
4

• Standby path in Ring → Chain 𝐼𝐷 + 𝐼𝐶

• Transmission of partial vector sums A 𝐼𝐴 + 𝐼𝐵 B

• Applied for SIPROTEC 7SD8

D C
2 𝐼𝐷 3
87L 87L

𝐼𝐴 + 𝐼𝐵 + 𝐼𝐶

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Multi Ended Line Differential Applications
Star Topology
𝐼𝐵
• Star topology 87L 87L
• Centralized protection (Master-Slave) Trip
A 𝐼𝐷 𝐼𝐶 B
• Decentralized (Master-Master)

D C
87L 87L

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Multi Ended Line Differential Applications
Star Topology

• Star topology 87L 87L

• Centralized protection (Master-Slave)
• Decentralized (Master-Master) A B

D C
87L 87L

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SIPROTEC 5
Line Differential Protection

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Line differential protection
Overview – SIPROTEC series

Hardware, 7SD86,87
I/O, Modules 7SL86,87

7SX85

7SD5
7SD82 7SX82
7SL82

7SD80 7SD610 Functionality,

Applications

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 Line differential protection
Overview – SIPROTEC series

SIP 4
SIPROTEC 4 Compact SIPROTEC 5
Feature Set 7SD61 7SD52 7SD80 7SD82 7SD86 7SD87 7SL82 7SL86 7SL87
Number of line ends 2 2…6 2 2…6 2…6 2…6 2…6 2…6 2…6
Tripping mode, min. T.-time 3-pol., 19ms 1/3-pol., 9ms 3-pol., 21ms 3-pol., 19ms 3-pol., 9ms 1/3-pol., 9ms 3-pol., 19ms 3-pol., 9ms 1/3-pol., 9ms
Transformer on line ⚫ ⚫ – ⚫ ⚫ ⚫ ⚫ ⚫ ⚫
Comm.: direct FO 100 1) 100 1) 24 100 1) 100 1) 100 1) 100 1) 100 1) 100 1)
(max. km)
Comm.: 2-wire Cu 20 2) 20 2) 20 (internal) 20 2) 20 2) 20 2) 20 2) 20 2) 20 2)
(max. km)
Comm.: IEEE C37.94 ⚫ ⚫ – ⚫ ⚫ ⚫ ⚫ ⚫ ⚫
Comm.: G703(1/6), X.21 2) ⚫ ⚫ – ⚫ ⚫ ⚫ ⚫ ⚫ ⚫
Comm.: Diff over IP/Eth. – – – – ⚫ ⚫ – ⚫ ⚫
Inputs and Outputs 4I, 4U 4I, 4U 4I, 3U 4I, 4U 8I, 8U1) 8I, 8U1) 4I, 4U 8I, 8U1) 8I, 8U1)
(max. standard variant) 7BI, 5BO 24BI, 31BO 7BI, 9BO 11BI, 23BO 31BI, 46BO1) 31BI, 46BO1) 11BI, 23BO 31BI, 46BO1) 31BI, 46BO1)
9BI, 16BO 9BI, 16BO
Distance protection (2 in 1) – ⚫ – – – – ⚫ ⚫ ⚫
SIP 4 Compatibility NA NA – ⚫ ⚫ ⚫ ⚫ ⚫ ⚫

1) Changeable (modular)
2) Using external communication converter

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7SD8 Line Differential Protection
Overview

• Up to 6 line ends (applications with multiple tapped lines)

• Transformer in zone protection
• Capacitive charging current compensation
• Remote tripping

• Several Protection communication interface options

• Direct fiber connections (long distance)
• Access to multiplexers (electrical and optical interfaces)
• Line Differential over IP/Ethernet

• Line differential test features

• Local / Loopback / Characteristic
• Sampled values (SAMU/MU) / test flags

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7SD8 Line Differential Protection
Overall Logic Diagram

• Core protection stages

• I-DIFF: sensitive phase current
differential
• I-DIFF fast 2: faster phase
current/charge differential
• Additional stages
• IN-DIFF: sensitive earth differential
• I2-DIFF: sensitive negative sequence
differential

• Features
• In-zone Transformer protection
• Charging current compensation
• Remote tripping (Rx, Tx)
• Supervision functions
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7SD8 Line Differential Protection
General

• Current phasors are estimated from sampled current waveform using FIR filters
• Sample time and data window must not be equal at all line ends → asynchronous phasors
• Alignment of current phasors → current phasor correction → needed for Kirchhoff‘s law

• For each protection interface:

• Measure the round trip delay between relays
• Estimation of DTO (device time offset) → supervise trend of CPU crystal drift
• Transient compensation of unsymmetrical transmission delays (Tx, Rx channel)

• Line differential protection uses data from synchronized protection interface (with highest bandwidth)

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SIPROTEC 5
Line Differential Protection
Data Alignment

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7SD8 Line Differential Protection
General – Data Alignment

• Timebase counters running independent

in both relays (derived from CPU crystal)
i
• Data windows for phasor calculation is different
• Offset in device times → Δ𝑡𝑊𝑖𝑛𝑑𝑜𝑤

→ Synchronization required
t

Common synchronization methods:

• Ping-pong method T Window A
• Small bandwidth (min. 64 kBit/s) Relay A
• Sync. with global time reference Relay B
t Window
→ PTP, 1PPS, GNSS T Window B

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7SD8 Line Differential Protection
General – PingPong Method

• Timebase counters running Sync. Function DTO

Device at
independent in both relays Station A tAA1S tAB1R
TD

(based on CPU crystal)

• Device time offset → DTO
• Transmission delay → TD tA

send A1 A2 A3 (tAA1S,tAB1R) A4

receive B1 B2 B3(tBA1R,tBB1S) B4
• Timestamps taken with last bit TA->B TB->A
of send/received telegrams
tB
• Received messages contain
B1 B2 B3 (tBA1R,tBB1S) B4
remote timestamps send

receive A1 A2 A3 (tAA1S,tAB1R) A4

→ Estimation of transmission delay

→ Estimation of DTO and DTO drift Device at tBB1S tBA1R Sync. Function DTO
Station B
→ Microsecond accuracy achieved ! TD

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7SD8 Line differential protection
General – Channel delay and DTO supervision

• Transmission delay (TD)

• Calculated by time difference between send and received telegrams
• Jumps in transmission delay may occure due to (symmetrical) channel switching
• Up to 155 ms transmission delays can be tolerated by Line Differential (therory)

• Device time offset (DTO)

• Difference of local and remote time base counter 𝐷𝑇𝑂 = 𝑇𝐵𝑙𝑜𝑐𝑎𝑙 − 𝑇𝐵𝑟𝑒𝑚𝑜𝑡𝑒
• No jumps are expected in DTO measurements
→ any DTO jump is assumed as channel asymmetry

• Setting for max. tolerated channel asymmetry Δ𝑇𝑎𝑠𝑦𝑚 → restraining current component

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SIPROTEC 5
Line Differential Protection
Stabilization Methods

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7SD8 Line Differential Protection
Adaptive Restrained Differential Characteristic

m=1
• Single slope characteristic Idiff 7SD
characteristic

𝐼𝑑𝑖𝑓𝑓,𝑝ℎ = 𝐼𝐴,𝑝ℎ + 𝐼𝐵,𝑝ℎ TRIP

𝐼𝑟𝑒𝑠𝑡,𝑝ℎ = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐

𝑛 𝑛 Idiff>
RESTRAIN

𝐼𝐴 𝐼𝐵 Irest
A 𝑍𝐿 B
𝐼𝑙𝑖𝑛𝑒

𝐼𝐶 𝐼𝐶
𝐶 𝐶
𝑈𝐴 2 2
87L 87L
communication link

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7SD8 Line Differential Protection
Adaptive Restrained Differential Characteristic

• Differential current

𝐼𝑑𝑖𝑓𝑓,𝑝ℎ = 𝐼𝐴,𝑝ℎ + 𝐼𝐵,𝑝ℎ

• Restraining current calculated from sum over line ends of max. phase current CT errors and signal distortion:

𝐼𝑟𝑒𝑠𝑡,𝑝ℎ = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐

𝑛 𝑛

Threshold Adaptive stabilization

parameter

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7SD8 Line Differential Protection 𝐼𝑟𝑒𝑠𝑡 = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐
Restraining Current: CT Errors (1) 𝑛 𝑛

• Steady state error • Differential current due to CT errors

(e.g. 5P10 → 5% error @ 10 In and Rbr) for two line ends
linear CT‘s fully
CT saturation
ideal CT range saturated
𝐼𝑠 real CT 𝐼𝑠
CT side A
𝐼𝑠,𝐶𝑇𝑒𝑟𝑟 CT saturation,
non-linear
CT side B

CT error

1 𝐾𝑠𝑠𝑐 𝐼𝑝 /𝐼𝑝𝑟 𝐼𝑝
𝐴𝐿𝐹
load currents

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7SD8 Line Differential Protection 𝐼𝑟𝑒𝑠𝑡 = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐
Restraining Current: CT Errors (2) 𝑛 𝑛

• Restraining current component for CT errors in linear range

• Differential currents due to CT errors are considered (not for CT saturation effects → see next slide)
• Two slope characteristic
• Higher sensitivity under load conditions
• Higher restraining for fault currents linear range CT saturation starts CT‘s fully saturated

𝐼𝑠,𝐶𝑇𝑒𝑟𝑟
CT error

CT error approx. for linear range

~𝜖𝐵
~𝜖𝐴

90% 100%
𝑘𝑐ℎ𝑎𝑛𝑔𝑒𝑜𝑣𝑒𝑟 𝐼𝑝 /𝐼𝑝𝑟
𝑘𝑐ℎ𝑎𝑛𝑔𝑒𝑜𝑣𝑒𝑟
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7SD8 Line Differential Protection 𝐼𝑟𝑒𝑠𝑡 = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐
Restraining Current: CT Errors (3) 𝑛 𝑛

• Recommended settings for different CT classes

• SIP 5 → SIP 5

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7SD8 Line Differential Protection 𝐼𝑟𝑒𝑠𝑡 = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐
Restraining Current: Signal Distortion 𝑛 𝑛

• Differential currents due to CT saturation and signal distortion (e.g. current harmonics)
• Transient errors

→ Deviation of measured signal compared to fundamental frequency component

→ Adaptive stabilization

measured signal
phasor calc. out of the measured signal
deviation between the measured signal
and the calculated phasor

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7SD8 Line differential protection 𝐼𝑟𝑒𝑠𝑡 = 𝐼𝑡ℎ𝑟 + ෍ 𝐼𝑝ℎ,𝐶𝑇𝑒𝑟𝑟 + ෍ 𝐼𝑝ℎ,𝑆𝑖𝑔𝐷𝑖𝑠𝑡 + 𝐼𝑠𝑦𝑛𝑐
Restraining current: Synchronization 𝑛 𝑛

• Differential currents due to synchronization mismatch

• Stabilization for asymmetrical transmission delays (difference in Rx and Tx channel)
• Applications using switched telecommunication networks (SDH, MPLS)

• Example for channel asymmetry

• 𝑇𝐴→𝐵 = 4 𝑚𝑠 Δ𝑇𝐷 = ±0.5 𝑚𝑠
𝑇𝐷 = 3.5 𝑚𝑠 𝐼𝑑𝑖𝑓𝑓 ≈ 𝐼𝑙𝑜𝑎𝑑 ⋅ 1 − 𝑒 𝑗 Δ𝜑
• 𝑇𝐵→𝐴 = 3 𝑚𝑠 Δ𝜑 = ±9 ° @ 50 Hz
Estimated by Synchronization error Apparent differential current
both relays

→ Ask your comms-experts for expected channel asymmetry

→ Set the max. expected difference in Tx and Rx asymmetry
• Direct FO connections → set to 0 ms
• IEEE C37.94 interfaces → set to 0.3 ms … 0.6 ms

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SIPROTEC 5
Line Differential
Protection Stages

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7SD8 Line Differential Protection
“I-DIFF” Stage

• Core protection stage

• Based on current phasors
• Two settable thresholds for I-DIFF >
• Optional Time delay

• Current jump detection to speed up operation

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7SD8 Line Differential Protection
“I-DIFF Fast” and “I-DIFF Fast 2” Stage

• Charge based differential principle

• Charge is calculated from current samples i
→ 5 ms data windows i(t)=A sin(t+)
• Stage active only for high currents
→ allows faster tripping than I-DIFF stage Q2 Q3
• Differential charge 𝑄𝑑𝑖𝑓𝑓 is calculated at all line ends Q1
1 sample
• Instantaneous tripping (time delay setting from V9.80)

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
𝑞 =𝑖⋅𝑡
i
tstart tend charge integration
Q window (5ms)
𝑞: charge
Q
𝑖: current 2,5ms
window offset
𝑡: time
෍ 𝑄𝑛 = 𝑄𝑑𝑖𝑓𝑓
𝑛
Page 43 Unrestricted | © Siemens 2024 | SI EA
7SD8 Line Differential Protection
“I-DIFF Fast 2” and “I-DIFF” Stage at Fault Inception

i(t)

I-DIFF is blocked, due

to jump in data window

I-DIFF fast is blocked

2 to 3 “windows”
20ms
1
2 invalid
6
7
11
after jump
3 invalid 8
I-DIFF 4 invalid 9
5 invalid 10

1 5 9 13 invalid17
2 6 10 14 18
3 7 11 invalid
I-DIFF fast invalid 15 invalid
19
4 8 12 invalid16 20
invalid
5ms

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7SD8 Line Differential Protection
“I-DIFF Fast 2” Stage – New Saturation Detection

Problem: Power Line

87L 87L
• CT saturation can result in conditions where the
A B
differential current during internal fault is smaller I/A I/A

than for external faults! t/s t/s

Differenzstrom
• High fault currents with saturation can result I/A

in blocking of the „I-DIFF fast“ stage Could be very large for ext. faults! t/s

Power Line
• “I-DIFF fast” stage is not fast enough
for all applications… 87L 87L

A B
I/A I/A

t/s t/s

Differenzstrom
Could be small for internal faults! I/A

t/s

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7SD8 Line Differential Protection
“I-DIFF Fast 2” Stage – New Saturation Detection with Matching “I-DIFF Fast” Stage

Solution: Power Line

→ Saturation detection based on waveform analysis!

87L 87L
Advantages in SIPROTEC 5:
A B
I/A

• I-DIFF stage → No changes

I/A

t/s t/s

• I-DIFF fast stage → Still available

Differenzstrom
(compatibility to existing SIPROTEC 4 relays)
I/A

• I-DIFF fast 2 → New, improved t/s

including saturation detector

Power Line
Response of “I-DIFF fast 2” when saturation is detected:
• Blocked when saturation is detected and external fault 87L 87L

A B
• Not blocked for internal faults I/A I/A

t/s t/s

• Fault changes from external to internal are cleared

faster Differenzstrom
I/A

→ Better response for high fault currents t/s

Page 46 Unrestricted | © Siemens 2024 | SI EA

7SD8 Line Differential Protection
Sensitive Earth Fault and Unsymmetrical Stages (from V09.30)

• High load current at line → high restraining currents

• Reduced sensitivity for high impedance faults

87L 87L

𝑆𝑙𝑜𝑎𝑑
A B

𝑅𝑓
𝐼𝐴 𝐼𝑓 𝐼𝐵

→ Use “IN-DIFF” or “I2-DIFF” Stages for special applications

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Contact/Disclaimer
Published by Siemens 2024
Smart Infrastructure
Electrification & Automation
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© Siemens 2024
Subject to changes and errors. The information given in this
document/video only contains general descriptions and/or performance
features which may not always specifically reflect those described,
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