Scribd
Upload
10 views

Verilog

Uploaded by

Hrishita Gupta
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
10 views

Verilog

Uploaded by

Hrishita Gupta
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

VERILOG

INTRODUCTION TO VERILOG:
1. What is Verilog?
✦ Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL), which is used

to describe a digital system such as a network switch or a microprocessor or a


memory a flip-flop in the form of code.
✦ The language is used to describe digital circuits hierarchically starting with the

most basic elements such as logic gates and flip flops and building up to more
Complex functional blocks and Systems .It also supports a range of modeling
techniques including gate- level ,RTL level and behaviour level modeling.
✦ Designs, which are described in HDL are independent of technology, very easy

for designing and debugging, and are normally more useful than schematics,
particularly for large circuits.

2. What is HDL?
✦ Hardware Description Language (HDL) is a programming language that is used

to describe the structure, behaviour and timing of electronic circuits, and most
commonly, digital logic circuits. HDLs are used for designing processors,
motherboards, CPUs and various other Digital circuits. In addition to their use in
circuit design, HDLs serve the purpose of simulating the circuit and verifying its
response. Many HDLs are available, but the most popular HDLs so far are Verilog
and VHDL.
✦ HDLs resemble a traditional programming language, but they are not identical.

These are specifically designed to describe the hardware.

3. What are the four abstraction levels to implement modules?


Verilog is basically a structural and behavior language and defines four
abstraction levels to implement modules.
1. Gate level – The module implementation is similar to the gate-level design
description in terms of logic gates and interconnections between them.
2. Dataflow level – The module implementation depends on data flow
specification i.e. how data flows and processes in the design circuit.

RENUKA R 1 of 4
3. Switch level – The module implementation requires switch level knowledge to
implement a design in terms of storage nodes, switches. This is the lowest level
of abstraction.
4. Behavior level – The module implementation is similar to C language
programming that includes algorithmic level implementation without worrying
about hardware implementation details.

4. How is verilog different from software languages like C and Java?


• Purpose: Verilog is used to describe digital circuits and systems, while C and Java
are used to write software programs that run on computers.
• Syntax: Verilog has a different syntax than C and Java, as it is designed to describe
the behavior of digital circuits rather than the execution of software instructions.
For example, Verilog describes the properties of wires, registers, and logic gates,
while C and Java define variables, functions, and control loops.
• Execution: Verilog is used to describe how digital circuits should behave, but it
doesn't directly execute code. Instead, the Verilog code is compiled into a hardware
configuration that can be implemented in a physical circuit or FPGA. C and Java
code, on the other hand, is compiled into machine code that can be executed
directly by a computer processor.
• Testing and Verification: Verilog is typically used to simulate the behavior of
digital systems before they are physically implemented, while C and Java programs
are usually tested and verified through software-based simulations or code reviews.
• Nesting of Design: In Verilog, the designs can be created as modules and can be
reused which is not in the case of programming languages like C and Java where
the code is written for a specific purpose.

5. What may replace Verilog in the future ?


High-Level Synthesis (HLS):
• Description: HLS automates the generation of hardware designs from higher-level
programming languages like C, C++, and SystemC.
• Advantages: Enables designers to express design intent at a higher level of
abstraction, speeding up design and exploration of design space.
• Impact: Could lead to more efficient and rapid development of digital systems
compared to traditional RTL design in Verilog or VHDL.

RENUKA R 2 of 4
Machine Learning and Artificial Intelligence (AI):
• Description: AI and machine learning techniques are being applied to optimize and
automate hardware design processes.
• Advantages: Can automate optimization tasks and generate designs, potentially
reducing manual effort and time-to-market.
• Impact: Promises to streamline digital system design and verification by
leveraging advanced algorithms for optimization and decision-making.

Emerging HDLs (Hardware Description Languages):


• Examples: Chisel and MyHDL are modern HDLs that address limitations of
Verilog and VHDL.
• Features: Based on contemporary programming concepts, they offer higher-level
abstractions and flexibility.
• Impact: These languages aim to improve productivity, design clarity, and
flexibility in describing hardware designs compared to traditional HDLs.

6. What is verification ?
This is checked by different methods and is collectively called as verification.
The most common and widely practiced method of verification is circuit simulation.
There are software tools to understand how a hardware described in Verilog should
behave and provide various input stimuli to the design model. The output of the
design is then checked against expected values to see if the design is functionally
correct.
All simulations are performed by EDA (Electronic Design Automation) software
tools and the Verilog design RTL is placed inside an entity called as testbench. Within
the testbench, various tests provide different stimuli to the design.

7. Sections of Verilog code


All behavior code should be described within the keywords module and
endmodule. Rest of the design code would mostly follow the given template.

Verilog sections template


1. Module definition and port list declaration.
2. List of input and output ports.
3. Declaration of other signals using allowed verilog data types.
RENUKA R 3 of 4
4. Design may depend on other Verilog modules and hence their instances are
created by module instantiations.
5. The actual Verilog design for this module that describes its behavior.

EXAMPLE:

module [design_name] ( [port_list] );

[list_of_input_ports]
[list_of_output_ports]

[declaration_of_other_signals]

[other_module_instantiations_if_required]

endmodule

RENUKA R 4 of 4

You might also like