Scribd
Upload
29 views

20ECH10 - Simulation and Testing Methods For VLSI Design

Uploaded by

Ganagadhar CH
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
29 views

20ECH10 - Simulation and Testing Methods For VLSI Design

Uploaded by

Ganagadhar CH
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

NSRIT | Academic Regulation 2020 | ECE | 20ECH10 Simulation and Testing Methods for VLSI Design| Approved in 4thBoS

and 5th ACM

HO 20ECH10 Simulation and Testing Methods for VLSI Design 4 0 0 4

At the end of the course, students will be able to

Code Course Outcomes


20ECH10.1 Identify the significance of testable design and specify Fabrication defects, Errors and Faults
20ECH10.2 Analyze various Simulation Methods in Modeling circuits
20ECH10.3 Understand the importance of Design verification
20ECH10.4 Implement the test methods for static and dynamic CMOS circuits
20ECH10.5 Analyze the BIST techniques to improve testability

Unit I : Introduction to Testing 12 Hours


Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI Technology Trends affecting Testing, Types of
Testing, FaultModeling: Defects, Errors and Faults, Functional Versus Structural Testing, Levels of Fault Models, Single Stuck-at
Fault.

Unit II : Logic and Fault Simulation 12 Hours


Simulation for Design Verification and Test Evaluation, Modeling Circuits for Simulation, Algorithms for True-value Simulation,
Algorithms for Fault Simulation, ATPG

Unit III : Testability Measures 12 Hours


SCOAP Controllability and Observability, High Level Testability Measures, Digital DFT and Scan Design: Ad-Hoc DFT Methods,
Scan Design, Partial-Scan Design, Variations of Scan.

UNIT IV : CMOS Testing 12 Hours


CMOS testing: Testing of static and dynamic circuits. Fault diagnosis: Fault models for diagnosis, Cause- effect diagnosis, Effect-
cause diagnosis.

UNITV : Built-In Self-Test 12 Hours


The Economic Case for BIST, Random Logic BIST: Definitions, BIST Process, Pattern Generation, Response Compaction, Built-
In Logic Block Observers, Test-Per-Clock, Test-Per Scan BIST Systems, Circular Self Test Path System, Memory BIST, Delay
Fault BIST.

Text Books
1. WenW. W., “VLSI Test Principles and Architectures Design for Testability”, Morgan Kaufmann Publishers, 2006.
2. AbramoviciM., BreuerM. and FriedmanA.,”Digital Systems Testing and Testable Design”, IEEE Press, 1990
3. William K. Lam “Hardware Design Verification: Simulation and Formal Method based Approaches”, Prentice Hall, 2008

Reference Books
1. Stroud and Kluwer,“A Designer’s Guide to Built-in Self-Test”, Academic Publishers, 2002
2. BushnellM. and AgrawalV. and Kluwer, “Essentials of Electronic Testing for Digital, Memory &MixedSignal VLSI Circuits”,
Academic Publishers, 2000
3. AgrawalV. and SethS.C.,”Test Generation for VLSI Chips”, Computer Society Press.1989.
4. LalaP. K., “Digital Circuit Testing and Testability”, Academic Press.

Web References
1. https://www.semanticscholar.org/paper/Advanced-simulation-and-test-methodologies-for-VLSI-Russell-
Sayers/c97ef40cf7a38b27bc3ec0496f9d0943dc29fdd4
2. nptel.ac.in/content/storage2/courses/106103116/handout/mod1.pdf

CONTROL COPY ATTESTED

Chairman
Board of Studies (ECE)

268

You might also like