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Notes DigitalSystems

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Notes DigitalSystems

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Omkar Patil

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1.

Introduction to Digital Signals

1.1 Creating Digital Signals

Additional Reading:
Textbook (Donzellini et. al.): Sections 1.1, 2.8.1
Textbook (Ashenden): Sections 1.1, 1.2, 1.3, 1.5, 2.3.3, 10.1, 10.24.1.1, 4.1.3

Note that the material presented in the course notes, videos, and exercise sets should be
considered as the main source for notations, formulations, and design principles while the
textbook material should be only considered as complementary.
Language, Words and Symbols
Current digital systems make it possible to communicate with
spacecraft at the edge of the Solar system, see activity inside
the living human brain, and probe the structure of atoms,
although they can not reliably predict next week's weather.
All achieved with machinery which can be described by, and is
constructed from, just two basic elements:

TRUE and FALSE

Just as a description of the brain given in terms of individual
atoms could not be read in a lifetime, and would have large-
scale features hidden by the fog of fine detail, so designing
digital systems using only a two-value (BINARY) language is
impractical for all but the smallest-scale parts of such systems.

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ELEE08015 Digital System Design 2 Introduction to digital signals
Language, Words and Symbols

Hence, digital system design requires that a more complex

language is used, one which is then translated into the final
(simple but voluminous) binary form.
In practice, many languages are used in the design of any
digital system, with successive translation from one to another.
Each language is designed to facilitate the solution of one
aspect of the design problem.
Thus the digital systems engineer designs one aspect of a
system in one language, then translates into another language
to tackle a different aspect, and so on.
As more of the simple/voluminous end of the process is
automated, engineering effort is freed, to be spent at the
complex end, where human intelligence is put to best effect.

3
ELEE08015 Digital System Design 2 Introduction to digital signals
Language, Words and Symbols

As well as the system design itself, the information it acts on is

often described in a different language (i.e., represented by a
different code) at each layer. The information is always encoded
with codes that become more complex at higher layers. A
sufficiently complex code (language) can describe itself.
Computer-aided design (CAD) tools treat codes describing
machinery as information to be processed. A machine's design
may stop at a layer higher than physical circuitry. In that case,
we have a "virtual machinery" (or software) that uses another
machine (e.g., a computer) to complete its interpretation and so
produce its effects.
The partitioning and co-design of software with hardware, to
produce a complete digital system, is an increasingly important
aspect of digital system design.

4
ELEE08015 Digital System Design 2 Introduction to digital signals
Design Abstraction Layers

RELATIONAL/FUNCTIONAL LAYER(S)
identify and define features of the problem
estimate likelihood that a solution exists within physical constraints

ALGORITHMIC/PROCEDURAL LAYER(S)
define large-scale features (method & modules) of alternative solutions
complexity choices strongly affect timing and other physical properties

REGISTER TRANSFER LAYER (RTL)

define hardware architecture ( medium-scale functional blocks)
extract initial estimates of physical properties

GATE LAYER
define small-scale logic structure (Boolean operations)
extract good timing, power and area estimates

PHYSICAL LAYOUT LAYER

micro-scale adjustments to a few critical regions (transistors)
timing, power and area calculations nearly exact but onerous

Digital system design progresses down through the layers shown above
starting from more abstract designs to more detailed designs. It also
usually involves design revisions using feedback from one layer to the
layer above. Longer distance feedback may indicate a serious design or
process flaw. Repeated feedback cycles increase commercial costs.
5
ELEE08015 Digital System Design 2 Introduction to digital signals
Design Abstraction Layers

RELATIONAL/FUNCTIONAL LAYER(S)
identify and define features of the problem
estimate likelihood that a solution exists within physical constraints

INCREASING CORRUPTION
INCREASING PHYSICALITY
ALGORITHMIC/PROCEDURAL LAYER(S)

INCREASING ABSTRACTION

INCREASING PERFECTION
define large−scale features (method & modules) of alternative solutions
complexity choices strongly affect timing and other physical properties

REGISTER TRANSFER LAYER (RTL)

define hardware architecture ( medium−scalefunctional blocks)
extract initial estimates of physical properties

GATE LAYER
define small−scale logic structure (Boolean operations)
extract good timing, power and area estimates

PHYSICAL LAYOUT LAYER

micro−scale adjustments to a few critical regions (transistors)
timing, power and area calculations nearly exact but onerous

Layered design allows for using imperfect approximations by gradually

increasing perfection. Each layer only focusses on part of total problem.
Different layers use different languages and tools. For example, the
GATE layer has ideal binary values (true/false), but discrete time
sequences is not ideal until the RTL layer (next up).
6
ELEE08015 Digital System Design 2 Introduction to digital signals
Making Continuous Signals Discrete
The analogue electrical circuit world of voltage and current
represents a continuous range of values over a continuous
interval of time.
The binary world at the heart of digital systems uses just two
discrete values, only one of which is used during each discrete
unit of time.
This discrete character is produced from analogue components
by using a nonlinear circuit behaviour to reliably generate the
binary values, and also a clock control to give the system a step-
by-step activity.
We shall examine the production of binary-level signals first,
and then will see how groups of several binary signals may be
used to represent non-binary information. Finally, we will
introduce the discrete time generated by the clock signal.
7
ELEE08015 Digital System Design 2 Introduction to digital signals
Making Continuous Signals Discrete

The simplest set of basic symbols for digital logic has just one
symbol, but this makes the electronic circuitry awkward to build.
In digital circuits we usually use a binary symbol set, containing
two symbols, so a single digital electrical signal carries one or
other of just two (logic) meanings:

TRUE or FALSE
We shall also write logic values in a variety of other ways, but
first we shall look at how an analogue electrical signal, having
a seemingly infinite range of possible values, can represent
binary digital TRUE and digital FALSE values.
Examples will be based on 5V CMOS logic technology. Many
others exist, but all share the same essential principles.

8
ELEE08015 Digital System Design 2 Introduction to digital signals
Making Continuous Signals Discrete
Voltage Transfer (Input-Output) Characteristic
+V ANALOGUE CIRCUIT

AMPLIFIER
input output
BIG

LINEAR
OUTPUT VOLTAGE

SMALL IN - > SMALL OUT

RANGE

MEDIUM IN - > MEDIUM OUT

circuit symbol BIG IN -> BIG OUT
SMAL

0V
SMALL BIG +V
INPUT VOLTAGE RANGE

Figure: Linear analogue circuit characteristic.

Considering a linear analogue circuit, each value in the input
range has proportional value in the output range. Any noise
added to the input signal is also correspondingly reproduced on
the output. That is the signal degrades from stage to stage.
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ELEE08015 Digital System Design 2 Introduction to digital signals
Making Continuous Signals Discrete
Voltage Transfer (Input-Output) Characteristic
+5V
o/p HIGH
region
90%
DIGITAL CIRCUIT
GATE (NON-INVERTING BUFFER)
OUTPUT VOLTAGE

input output
non-logic region

NON-LINEAR
logic transition region

SMALL IN -> VERY SMALL OUT

MEDIUM IN -> MEDIUM OUT
circuit symbol
BIG IN -> VERY BIG OUT

LOGIC GATE GIVES SMALLER OUT FOR SMALL

IN AND LARGER OUT FOR LARGE IN, KEEPING
10%
o/p LOW HIGH AND LOW REGIONS SEPARATED. MEDIUM
region
0V input non-logic region
SIGNALS ARE NOT VALID/STABLE LOGIC.
input LOW logic transition region input HIGH +5V
region 30% logic threshold range 70% region
INPUT VOLTAGE
Figure: The nonlinear logic gate characteristic.

A valid logic signal is in either the high or low region. Valid Input regions
are assumed to be wider than valid output regions. Thus, the nonlinear
behaviour reduces the intensity of the added input noise at the
output (no stage by stage degradation).
10
ELEE08015 Digital System Design 2 Introduction to digital signals
Making Continuous Signals Discrete
Voltage Transfer (Input-Output) Characteristic
+5V ANALOGUE CIRCUIT
logic HIGH AMPLIFIER
region input output
LINEAR

SMALL IN -> SMALL OUT

MEDIUM IN - >
OUTPUT VOLTAGE

non-logic region

MEDIUM OUT
circuit symbol BIG IN -> BIG OUT

DIGITAL CIRCUIT
GATE (NON-INVERTING BUFFER)
input output
NON-LINEAR

SMALL IN -> VERY SMALL OUT

MEDIUM IN -> MEDIUM OUT
logic LOW circuit symbol BIG IN -> VERY BIG OUT
region
0V
logic LOW non-logic region logic HIGH +5V UNLIKE AN ANALOGUE AMPLIFIER CIRCUIT, A DIGITAL
region region GATE CIRCUIT ALWAYS TRANSFERS A VALID LOGIC
INPUT VOLTAGE
INPUT VALUE TO A VALID LOGIC OUTPUT VALUE

Digital gate circuits push the output signal to either extreme

HIGH or LOW, making two nearly discrete signal values, reducing
the added noise, emphasising the logic value. Signals pass
through millions of gates and become immune to noise.
11
ELEE08015 Digital System Design 2 Introduction to digital signals
Making Continuous Signals Discrete
CMOS Transition (Rise / Fall) Times
OUTPUT
VOLTAGE input output

+5V
HIGH region
90% A gate's output is limited in the rate at which it can
change voltage. The consequent waveform
distortion can change logic VALID periods

i on

tran
sit
n

sitio
tra

VALID

n
logic VALID VALID
LOW logic INVALID logic HIGH logic INVALID logic LOW
10%
LOW region
0V
RISE TIME FALL TIME TIME
tTLH or tr tTHL or tf

Switching an output between HIGH and LOW takes time: the Rise
time (L to H) or fall time (H to L). The signal is not a valid logic value
during this transition time from one valid region to the other and thus
systems are designed to not use the output during this time.
12
ELEE08015 Digital System Design 2 Introduction to digital signals
Making Continuous Signals Discrete
Input to Output Propagation Delay
input output
OUTPUT A gate's output will not change instantaneously
VOLTAGE
with a change at its input
+5V The common propagation delay parameter
tPD or td
can be used to simplify propagation delay
calculations for a series of gates
nominal logic transition
50%
threshold - 50%

0V
TIME
RISING OUTPUT
PROPAGATION DELAY tPLH or tdr tPHL or t df
FALLING OUTPUT
PROPAGATION DELAY

There is a propagation delay period before a transition in the input of a

gate causes an output transition. Propagation delay is measured
between the half-way points (at 50%) of the corresponding transitions.

13
ELEE08015 Digital System Design 2 Introduction to digital signals
Representing Logic Gate Signals
Schematic (Stylised) Form of Signals

VOH
90% VO
10%
VOL
time tTLH / tTHL
tTLH tTHL tr / tf
tr tf

VIH
50%

VIL
VI VO
time
VOH
50%

VOL tPHL / tPLH tdf / tdr

time tPD
common form
tPLH tPHL td (dr-df)
tdr tdf

Abstraction: straight lines are used in the schematic form as an

approximation of real (wobbly) signals.
Key features retained (transition time, propagation delay)
14
ELEE08015 Digital System Design 2 Introduction to digital signals
Representing Logic Gate Signals
WHAT IS TRUTH?
The POSITIVE (+ve) LOGIC CONVENTION:
LOW voltage means FALSE
HIGH voltage means TRUE
The NEGATIVE (-ve) LOGIC CONVENTION:
HIGH voltage means FALSE
LOW voltage means TRUE
Our first two languages: express logic values as voltages
Unless stated otherwise, it is usual to presume the +ve logic
convention. Although a common choice, this is a design choice
and not universal. Sections of digital systems may use -ve logic,
for good design reasons.
Always verify assumptions, truth is subject to interpretation

15
ELEE08015 Digital System Design 2 Introduction to digital signals
Symbols Representing Logic Value

D Logic R Logic

TRUE FALSE

FALSE TRUE

Symbols may represent truly universal values,: π , e, but the

binary logic values of the symbols 1 and 0 can go either way.
Symbols π and e above represent numbers, but 1 and 0 do not.
In this course 1 will mean TRUE and 0 will mean FALSE.
Beware: some digital languages define 0 as TRUE, and others
(such as C) have more than one representation of TRUE.

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ELEE08015 Digital System Design 2 Introduction to digital signals
Symbols Representing Logic Value
Some closing words on the definition of truth:
Sometimes, we just don’t care, so a third symbol enters the
binary language: * (asterisk, sometimes X is used)
This "don’t care" symbol represents cases where 1 or 0 is
actually used, but we don’t yet know, or it doesn’t matter.
Finally, if there is a leak in your logical/physical layer boundary
(e.g., voltage remaining in a transitional level): Z may be used to
indicate that a logic value is neither 1 nor 0, but is invalid.
1 and 0 are the only logic values
Z is NOT a logic value

* Means either 1 or 0, we don’t care (don't know) which (yet)

17
ELEE08015 Digital System Design 2 Introduction to digital signals
Summary So Far
Binary logic deals with abstract perfection: TRUE and FALSE
... but in electronic circuitry there are transition periods of
neither — circuitry is always imperfect — during which we
must avoid looking for an answer (using the output)
Voltages to represent TRUE/FALSE need a code: +ve or -ve logic

Writing to represent TRUE/FALSE needs a code: D logic or R logic

• Thus we already have a choice of four ways to encode the

DS2 VH
VL

CLOCK VH
VL

tPD

PROPAGATION DELAY - measured from active clock edge

New stored input value transferred to output
Once no longer inside setup/hold time window, input may change
DFF propagation delay defined not from D to Q, but CLOCK to Q

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ELEE08015 Digital System Design 2 Introduction to digital signals
The D (data) FLIP-FLOP (positive edge triggered)
CLOCK CONTROLLED LOGIC VALUE PROPAGATION
IN DS1 DS2
D Q D Q

Ck Ck

CLOCK CLOCK

VH
IN
VL
VH
DS1
VL
VH
DS2 V
L
VH
CLOCK VL

tsu
th

Input D is ignored in (long) period after hold and before next setup
Inactive (negative, falling) clock edge ignored
This is the time window in which combinational gates compute new
codewords causing temporary (glitch) and final transitions of signal.

ELEE08015 Digital System Design 2 IAB Lindsay L5 CONTROLLING TIME DELAY - THE CLOCK FOIL 15
27
ELEE08015 Digital System Design 2 Introduction to digital signals
The D (data) FLIP-FLOP (positive edge triggered)
CLOCK CONTROLLED LOGIC VALUE PROPAGATION
IN DS1 DS2
D Q D Q

Ck Ck

CLOCK CLOCK

VH
IN
VL

DS1 VH
VL

DS2 VH
VL

CLOCK VH
VL
tsu
th

Next active clock edge

Input must remain stable within setup and hold window
Input value being stored within DFF circuitry
Output is still old stored value

28
ELEE08015 Digital System Design 2 Introduction to digital signals
The D (data) FLIP-FLOP (positive edge triggered)
CLOCK CONTROLLED LOGIC VALUE PROPAGATION
IN DS1 DS2
D Q D Q

Ck Ck

CLOCK CLOCK

VH
IN
VL

DS1 VH
VL

DS2 VH
VL

CLOCK VH
VL

tPD

New stored value propagates to output

Typically this feeds combinational gates,
whose output(s) change after some delay +/-variability,
but design calculations ensure stability before next active clock edge

29
ELEE08015 Digital System Design 2 Introduction to digital signals
The D (data) FLIP-FLOP (positive edge triggered)
CLOCK CONTROLLED LOGIC VALUE PROPAGATION
IN DS1 DS2
D Q D Q

Ck Ck

CLOCK CLOCK

VH
IN
VL

DS1 VH
VL

DS2 VH
VL

CLOCK VH
VL

Cycle by cycle: process, store, process, store, ...

Signals may become unstable for a (worst-case) period,
followed by a stable period while the new value(s) are stored,
then a further period is allowed for more processing/instability

30
ELEE08015 Digital System Design 2 Introduction to digital signals
1. Introduction to Digital Signals
1.2 Boolean Algebra

Additional Reading:
Textbook (Donzellini et. al.): Sections 1.2-1.8, 1.12, 1.13, 2.6.1
Textbook (Ashenden): Sections 2.1.1, 2.1.2 4.1.1, 4.1.3

Note that the material presented in the course notes, videos, and exercise sets should be
considered as the main source for notations, formulations, and design principles while the
textbook material should be only considered as complementary.
Boolean Variables and Functions
Boolean variables are binary variables that can assume two values X = 0 indicating
logic value false and X = 1 indicating logic value true.

For Boolean variables 𝑋! , 𝑋" , . . ., 𝑋# , Boolean function 𝑓(𝑋! , 𝑋" , . . ., 𝑋# ) can

assume only the values 0 and 1. This function associates a Boolean value to every
element in its domain.
Truth Table: The domain of a function of n-variables is composed of all the
2# combinations of their values. Therefore, domain’s elements are countable. Two
functions are equivalent if they assume the same value for any combination of their
variables’ values. We can represent Boolean functions using Truth tables:

𝑋! 𝑋" 𝑋#. f
0 0 0 Values
Let’s assume a three-variable 0 0 1
function 𝑋! , 𝑋" , 𝑋$ . We can
0 1 0 assumed
construct a table with all the
values assumed by f :
0 1 1
1 0 0 by function
1 0 1
1 1 0 f (𝑋!, 𝑋",𝑋$)
ELEE08015 Digital System Design 2 Introduction to digital signals
1 1 1 32
Fundamental Elements of Boolean algebra: Logic Gates

Operation: OR AND NOT

Algebraic symbols: 𝑋 + 𝑌 𝑋(𝑌 𝑋)

Circuit diagram
symbols:

Truth table: 𝑋 𝑌 𝑋+𝑌 𝑋 𝑌 𝑋(𝑌 𝑋 𝑋)

0 0 0 0 0 0 0 1
0 1 1 0 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1

33
ELEE08015 Digital System Design 2 Introduction to digital signals
Basic Principles of Boolean Algebra:

Duality Principle: 𝑋+1=1 (dual:) 𝑋'0=0

𝑋+0=𝑋 (dual:) 𝑋'1=𝑋

Idempotent Law: 𝑋+𝑋 =𝑋 (dual:) 𝑋'𝑋 =𝑋

Commutative Law: 𝑋 + 𝑌 = 𝑌 + 𝑋 (dual:) 𝑋'𝑌 =𝑌'𝑋

Associative Law: 𝑋+𝑌 +𝑍 =𝑋+ 𝑌+𝑍 =𝑋+𝑌+𝑍

(dual:) 𝑋 ' 𝑌 ' 𝑍 = 𝑋 ' 𝑌 ' 𝑍 = 𝑋 ' 𝑌 ' 𝑍

Distributivity: 𝑋+𝑌 ' 𝑋+𝑍 =𝑋+ 𝑌'𝑍

(dual:) 𝑋 ' 𝑌 + 𝑋 ' 𝑍 = 𝑋 ' 𝑌 + 𝑍

Complementation: 𝑋 + 𝑋+ = 1 (dual:) 𝑋 ' 𝑋+ = 0

Absorption: First form: 𝑋+𝑋'𝑌 =𝑋 (dual:) 𝑋 ' (𝑋 + 𝑌) = 𝑋

Second form: 𝑋 + 𝑋+ ' 𝑌 = 𝑋 + 𝑌 (dual:) 𝑋 ' (𝑋+ + 𝑌) = 𝑋 ' 𝑌

34
ELEE08015 Digital System Design 2 Introduction to digital signals
Logic Adjacency: 𝑌𝑋 + 𝑌𝑋+ = 𝑌
(dual:) + =𝑌
𝑌 + 𝑋 ' (𝑌 + 𝑋)

Consensus: 𝑋 ' 𝑌 + 𝑌 ' 𝑍 + 𝑍 ' 𝑋+ = 𝑋 ' 𝑌 + 𝑍 ' 𝑋+

(dual:) 𝑋 + 𝑌 𝑌 ' 𝑍 (𝑍 ' 𝑋)+ = 𝑋 + 𝑌 (𝑍 ' 𝑋) +

Involution (Also known as Double Complement law): 𝑋. = 𝑋

De Morgan’s Theorem
A logical product of two variables can be substituted by the negation of their logical
sum. Dual: a logical sum of two variables can be substituted by the negation of their
logical product:
𝑋 ( 𝑌 = 𝑋) + 𝑌)
(dual:) 𝑋 + 𝑌 = 𝑋) ( 𝑌)

Generalized De Morgan’s Theorem:

𝑋! ( 𝑋" ( … ( 𝑋# = 𝑋! + 𝑋" + … + 𝑋#
(dual:) 𝑋! + 𝑋" + … + 𝑋# = 𝑋! ( 𝑋" ( … ( 𝑋#
35
ELEE08015 Digital System Design 2 Introduction to digital signals
Other Operations: NAND and NOR

Operation: NAND NOR

Algebraic symbols: (𝑋 ( 𝑌) (𝑋 + 𝑌)

Circuit diagram
symbols:

Truth table: 𝑋 𝑌 𝑋 nand 𝑌 𝑋 𝑌 𝑋 nor 𝑌

0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

36
ELEE08015 Digital System Design 2 Introduction to digital signals
Other Operations: XOR

The XOR operation is said “anticoincidence” (it provides 1 when the

inputs are different):
𝑋⨁𝑌 = 𝑋 xor 𝑌 = 𝑋𝑌) + 𝑋𝑌
)

Circuit diagram symbol: Truth table:

𝑋 𝑌 𝑋⨁𝑌
0 0 0
0 1 1
1 0 1
1 1 0

Generalized XOR:
1 if there is an odd number of inputs = 1
𝑋!⨁𝑋"⨁ … ⨁𝑋# = 0
0 if there is an even number of inputs = 1

37
ELEE08015 Digital System Design 2 Introduction to digital signals
NOR-only Design
We can obtain the fundamental logic gates AND, OR and NOT from NOR only. If we
connect a NOR as in the ﬁgure below, we obtain a NOT. Given that the X and Y
inputs are connected together, we obtain the following from the NOR table:
𝑋 𝑌 𝑋 nor 𝑌
𝑋 𝑋% 0 0 1
1 1 0
However, we obtain the OR gate by negating the NOR output with a NOT:

𝑋+𝑌
𝑋
𝑋+𝑌
𝑌

To obtain the AND, we apply De Morgan 𝑋 ' 𝑌 = 𝑋+ + 𝑌:

+
𝑋%
𝑋

𝑋(𝑌

𝑌
𝑌%
38
ELEE08015 Digital System Design 2 Introduction to digital signals
NAND-only Design
Similar to NOR, NAND can be used to generate fundamental gates, e.g., NOT is
obtained as follows,

𝑋 𝑌 𝑋 nand 𝑌
𝑋 𝑋% 0 0 1
1 1 0
Therefore, to obtain the AND, it is sufﬁcient to connect the NAND to a NOT made
with a NAND. :
𝑋(𝑌
𝑋
𝑋(𝑌
𝑌

Finally, by De Morgan, we obtain the OR:

𝑋%
𝑋

𝑋+𝑌

𝑌
𝑌%
39
ELEE08015 Digital System Design 2 Introduction to digital signals
Minterms and Maxterms
Minterm: If an AND term in a Boolean expression contains all the direct or negated
variables in the entire expression, it is called a fundamental product, or minterm. For
example:
𝑓 𝑋!, 𝑋",𝑋) = 𝑋! ( 𝑋" ( 𝑋) is a minterm.

An n-variable function has 2# minterms since every variable in the function must be
part of a minterm, in its direct or negated form.
Maxterm: If an OR term in a Boolean expression contains all the direct or negated
variables in the entire expression, it is called a fundamental sum, or maxterm. As above, if
there are n-variables, there are 2# maxterms. For example:

𝑓 𝑋!, 𝑋",𝑋) = 𝑋! + 𝑋" + 𝑋) is a maxterm.

Remember that there is only one combination of variables for which a certain maxterm
equals zero, e.g., 𝑋! + 𝑋" + 𝑋$ = 0 if and only if 𝑋! = 0, 𝑋" = 1, 𝑋$ = 0, or a certain minterm
equals 1, e.g., 𝑋! ' 𝑋" ' 𝑋$ = 1 if and only if 𝑋! = 1, 𝑋" = 1, 𝑋$ = 0.

Also a general Boolean function can be written either in terms of sum of minterms (sum
of products) or in terms of product of maxterms (product of sums).
40
ELEE08015 Digital System Design 2 Introduction to digital signals
Example: Decoder
Row and column decoders are typically used to implement accessing data in a specific
part of memory arrays. They have n inputs and 2n outputs: every combination of inputs
activates one and only one output.

● Truth table:
– k = 3 address line inputs A2 , A1 and A0
Row
– 2k = 8 word line outputs WL0 - WL7 Decoder
A A A WL WL WL WL WL WL WL WL WL 0
2 1 0 0 1 2 3 4 5 6 7
0 0 0 1 0 0 0 0 0 0 0 WL 1
0 0 1 0 1 0 0 0 0 0 0 WL 2
A2
0 1 0 0 0 1 0 0 0 0 0 WL 3
0 1 1 0 0 0 1 0 0 0 0 A1
WL 4
1 0 0 0 0 0 0 1 0 0 0 A0
WL 5
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0 WL 6
1 1 1 0 0 0 0 0 0 0 1 WL 7
ELEE08015 Digital System Design 2 Introduction to digital signals
41
Decoder Circuit Implementation

A2 A1 A0 Truth Table Minterms

WL0 = A2 . A1 . A0
WL 0

WL 1 WL1 = A2 . A1 . A0

WL 2
WL2 = A2 . A 1 . A0 ... etc
WL 3 A A A WL WL WL WL WL WL WL WL
2 1 0 0 1 2 3 4 5 6 7
0 0 0 1 0 0 0 0 0 0 0
WL 4
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
WL 5 0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
WL 6 1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
WL 7 1 1 1 0 0 0 0 0 0 0 1
ELEE08015 Digital System Design 2 Introduction to digital signals
42
L2.1 Non-Number Codes
Codes
In the digital world, everything is in code: it is encoded.
There are innumerable digital codes in use and new codes are
invented every day. Codes are simple languages.
• The code used for a design affects the logical structure and
physical properties of the system (we will see later how).
• Weaknesses and strengths of physical circuitry influence the
design of the code(s) used to describe the data being
processed in the machine and also the machine design itself
(e.g., algorithm).
For good system design, engineers have to select or invent
codes appropriate to the application (top layer), the physical
fabric (bottom layer), and many layers in-between.
How Are Codes Used?
• To hide information - cryptography (One-time pad)
• To preserve information - integrity (error correcting codes)
• To condense information - compression (Lempel-Ziv, mp3)
• and finally to represent information - the underlying function of
all codes and the primary focus within this course
Transistor circuits form logic gates which work only with true
and false, but engineers design complex networks of gates to
process more complex types of information, and so:
• The information must be encoded in carefully designed
collections of the basic 1/0 symbols (TRUE/FALSE, Hi/Lo)
It is vital to keep track of which code is in use in each section of
any digital system: lose the code and you lose the meaning
Some Language for Talking About Codes
Symbol: The basic element(s) used to construct codewords
Cardinality: The number of different symbols available
Codeword: A particular arrangement of symbols

Bit (digit): Each place in a codeword where a symbol may be put

Encoding: A particular mapping between a set of codewords and
the set of data which they represent

Code: A particular set of codewords and their encoding/decoding

We shall mostly consider fixed-length binary codes, so their
cardinality is 2 (with binary symbols 1/0) and for each code the
codewords all have the same number of bits each bit being filled
by either a 1 or a 0.
Unary (Cardinality One) Codewords

Codewords built from a symbol set containing only one symbol

must have a different number of digits for each codeword:
apple
banana
cumquat
A code having variable length codewords can require the
circuitry to change size according to the value of information
being represented, which is possible but often inconvenient.
For unary codes, the quantity of information that can be
represented by the code grows only linearly with the circuit size,
which is bad news for anything but quite small sets of
information.
Binary (Cardinality Two) Codewords
A fixed number of bits filled from a set of two options (1/0) can
efficiently represent a very large number of values:
One Bit: 2 meanings 2 choices
Two Bits: 4 meanings 2x2 choices
Three Bits: 8 meanings 2x2x2 choices
Four Bits: 16 meanings (One Nibble)
... ... ... ...
Eight Bits: 256 meanings (Octet, Byte)
... ... ... ...
N Bits: 2ˆN meanings (Word)
Therefore, the quantity of information represented grows
exponentially with the length of codewords (size of the circuit),
so a modest size of circuit can manage a large quantity of
information values.
Codes are Maps
A digital code comprises a set of (digital world) codewords
mapped to a set of (real world) meanings
• The mapping (encoding) can be arbitrary, but usually has a
structure designed based on an understanding of the
information being mapped (represented) to simplify operations to be
performed (e.g., addition in number codes) on the information.
• In digital systems it is usual to use different codes in different
parts of a system, requiring circuits which simply translate one
set of codewords into another (decoder/encoder)
• Without knowledge of the mapping (encoding) the digital
codewords are meaningless and so the circuit is useless
Let us study structural features of some binary codes:
Some Examples of Digital Codes And Their Design:
Non-Number Codes
Engineers are accustomed to encoding all forms of information
(temperature, pressure, height, weight, ...) as numbers, then
applying multi-purpose number-processing tools to manipulate
the numbers, before turning them back into information again.
IN A DIGITAL SYSTEM NUMBERS HAVE TO BE ENCODED
Before getting confused by all the different number codes, we
shall examine some general properties and issues of code
construction, and become familiar with some non-number codes
found in and around the home:
• Food Cooker code, Thermometer code, Gray code (that’s
Frank Gray, not grey), ASCII (ANSI_X3.4-1986)
‘‘Food Cooker’’ Code
top BIT ORDER MAPPING bottom

000100
true <−> lamp on
LOGIC MAPPING
false <−> lamp off

100000 keeping cinders warm 6th stage

010000 incinerating 5th stage
001000 cooking 4th stage
000100 CODEWORD ORDER / SEQUENCE 3rd stage
000010 de−frosting 2nd stage
000001 stand−by 1st stage
(0 0 0 0 0 0) potential codeword reserved/excluded/ambiguous

A "one−hot" code − always exactly one bit true

A "sparse" code − only 6 of 64 (2^6) potential codewords defined value

Bit position within the codeword is often significant/deliberate

In many codes the codewords have a natural/proper order
In many codes specific codewords are deliberately excluded
Thermometer Code
A UNIT DISTANCE CODE (Hamming distance)
NATURAL BIT ORDER

equal bit significance

The name is only an analogy, this code
111111 may be found in fast analogue-to-
011111 digital converters, and elsewhere.
001111
000111 NATURAL CODEWORD ORDER
000011
000001
000000

The codewords in Thermometer code have natural order of

significance/occurrence where every codeword has a hamming
distance of one with the previous and the next codewords.
Hamming distance is defined as the count of bits where two
codewords differ. The bits have equal significance (equal
weight), but the codeword bit-patterns (...00|11...) show a
natural order. This is also another sparse code (less than 1/2
possible codewords used).
00 000 Gray Code N
01 0 01 0 0 00 N
0 11 NNW
11 0 0 01 NNE
10 0 10 0 0 11 NE NW NNE
1 10 0 0 10 ENE
Frank Gray (Bell Labs) 1 11 0 1 10 E WNW NE
1 01 0 1 11 ESE
1 00 0101 SE
0 1 00 SSE W ENE
Reflective structure: can create 1 1 00 S
any N−bit Gray code by formula 1 1 01 SSW
1 1 11 SW WSW E
1 1 10 WSW
circular sequence of codewords 1010 W
ESE
1011 WNW SW
1001 NW
A UNIT DISTANCE CODE 1000 NNW SSW SE
0000 N S SSE

Gray code is another unit-distance (Hamming) code, with circular

continuity of codewords. It has a reflective structure allowing to
systematically generate larger length codes based on shorter ones
as in the figure above. It is a dense code as it uses all the codewords.
It was originally designed for digital communications systems, but
commonly found in rotary shaft position encoders, and elsewhere
7-Segment Code

A graphic symbol code to display decimal number symbols.

It is not really a number code and thus unsuitable for doing arithmetic.
Specific bit <-> lamp mapping (top bar always bit-0 &c.)
l0
l6 l5 l4 l3 l2 l1 l0 SYMBOL
0 1 1 1 1 1 1 0
0 0 0 0 1 1 0 1 l5 l1
1 0 1 1 0 1 1 2 l6
1 0 0 1 1 1 1 3
1 1 0 0 1 1 0 4 l4 l2
&c. l3
1 1 0 0 1 1 1 9
It is a sparse code. Without graphic interpretation it appears un-
structured - no obvious relation between: codewords for successive
symbols, bits in a codeword, or any other feature.
ASCII (ANSI_X3.4-1986)
ASCII code is a dense 7-bit code for communicating graphical
symbols. It has a complex but useful/important/deliberate structure.
00***** 32: non-graphic symbols

0000000, 1111111: two codewords meaning "no symbol"

1000011 -> ’C’, 1100011 -> ’c’,
Bit-5 (6th from right) signifies U/L case for alphabetics only and the last 5
bits show the order of the letters, for example:
1000001 (A), 1000010 (B), 1000011 (C), ... 1011010 (Z)
Alphabetic order matches natural order of some numeric codes
0110000 -> ’0’, 0110001 -> ’1’, ... 0111001 -> ’9’
Numeric symbols are also clustered (starting with ‘011’) and are similar
to some numeric codes. Study the full code from other sources.
L2.2 Number Codes I: integers
Numbers and Number Encoding
A code of fixed-length codewords can only represent a
finite set of values: many useful sets of numbers come
in an infinite quantity.
Hence most digital systems will have missing number values
• actually almost all the numbers will be missing!
Integer number codes can push the missing values to the end(s) of
the range: all values within range have a codeword, but outside the
range will either have no codeword, or share special/reserved
codeword(s) (overflow).
Rational and pseudo-real number codes have holes:
missing numbers, even within the limited range of these codes
Code design may not eliminate holes, but resolution and range
choices can put them where they do least harm.
Binary Codes For NUMBER PROCESSING
All the codes discussed here are based on two symbols (1/0)
so they are all binary codes. Beware of numbers stated simply
as being "in binary":
in Maths: this probably means base-2 numbers:
plus eleven +1011, minus five -101, zero 0.
in Digital Systems: this is a meaningless phrase unless we know
which binary code is being used to represent numbers.
Digital logic deals with true/false not numbers. In fact, we can
encode a finite subset of the numbers as a set of binary logic
codewords in many different ways...
All numbers (ALGORITHM LAYER) are just codewords to digital
logic (RTL/GATE LAYER). You can not know what 0101010
means unless you know the code.

3
Codeword Notation:
binary hexadecimal octal decimal
00000000 0000 0000 00 00 000 000 000 ...
00000001 0000 0001 01 00 000 001 001 ...
00000010 0000 0010 02 00 000 010 002 ...
00000011 0000 0011 03 00 000 011 003 ...
00000111 0000 0111 07 00 000 111 007 ...
00001000 0000 1000 08 00 001 000 010 ...
00001001 0000 1001 09 00 001 001 011 ...
00001010 0000 1010 0A 00 001 010 012 ...
00001011 0000 1011 0B 00 001 011 013 ...
00001111 0000 1111 0F 00 001 111 017 ...
00010000 0001 0000 10 00 010 000 020 ...
00010001 0001 0001 11 00 010 001 021 ...
11111110 1111 1110 FE 11 111 110 376 ...
11111111 1111 1111 FF 11 111 111 377 ...
hexadecimal & octal notations are simple compact ways of writing binary
codewords but they are not numbers. Hexadecimal notation in engineering
is not the base-16 number in maths.
4
Binary Natural Number (BNN) Code (‘‘binary’’, ‘‘unsigned binary’’)

Place-Value Exponential-Weight Code: successive bits have

exponentially increasing numeric significance (weight, value).
b0 is the "least significant" bit, b5 the "most significant" bit. This terminology is often
used with other codes even when the weights are not necessarily increasing.
b5 b4 b3 b2 b1 b0 bits (b0 is often called "the first bit")
25 24 23 22 21 20 weights (exponential form)
32 16 8 4 2 1 weights (plain form)
1 0 1 0 1 0 codeword: false/true (de-)/selects
32 0 8 0 2 0 effective place/bit value

32 + 8 + 2 = 42 numeric value of codeword

Regular structure mirrors modern place-value notation where the numeric
value is computed as sum of the weights of true bits. Easily confused with
base-2 number notation in which ’1’ is ’one’ rather than ’true’.
Range: 0 to (2N - 1) for N bits.
Resolution: uniform and unity.
Signed Magnitude (SM) Number Code
Essentially BNN, plus an extra bit (sign) to multiply result by ±1
b6 b5 b4 b3 b2 b1 b0 bits
-1/ + 1 32 16 8 4 2 1 factor (b6) & weights (b5-0)

0 1 0 1 0 1 0 codeword: false/true
+1 32 0 8 0 2 0 +1 × (32 + 8 + 2) = 42

1 1 0 1 0 1 0 codeword: false/true
-1 32 0 8 0 2 0 -1 × (32 + 8 + 2) = -42
Two codewords for zero (Not ± zero as number zero is unsigned)
The sign bit makes structure irregular, but it gives a symmetrical
value range which mathematically convenient.
Range: -(2(N -1) - 1) to +(2(N -1) - 1) for N bits (zero balanced),
Resolution: uniform, unity
Offset / Excess BNN Number Codes (many variants)
Add a positive constant (the "bias") to the value to be encoded
and then encode the biased value (which is now strictly positive)
in BNN. See examples of 4-bit offset BNN with a bias of +7:
0010 minus five: -5 + 7 = 2 Encode 2 in BNN
1001 plus two: +2 + 7 = 9 Encode 9 in BNN
0000 minus seven: -7 + 7 = 0 Encode 0 in BNN
1111 plus eight: 8 + 7 = 15 encode 15 in BNN
0111 zero: 0+7=7 encode 7 in BNN
Range: -bias: 2N -1-bias, range limit changes by bias value
(but never zero balanced),
Resolution: uniform, unity
Unique value for each codeword
Natural codeword order same as many other codes (BNN &c.)
One’s Complement (1’sC) Number Code
For positive values, same as BNN with the msb false:
0010 two
0111 seven (maximum positive value in 4 bits)
For negative values, invert the corresponding +ve codeword:
1101 minus two
1000 minus seven ( the most negative value in 4 bits)
Zero has two possible codewords: 0000 and 1111 (in 4 bits)
Range: -(2(N -1) - 1) to +(2(N -1) - 1) for N bits (zero balanced),
Resolution: uniform, unity.
Most 1’sC systems use only one codeword for zero,
the other may represent "no value" - distinct from "zero value" or
the system is designed to convert it to the proper codeword.
widely used in digital communications e.g. TCP/IP packet
checksums
Two’s Complement (2’sC) Number Code
Like BNN code, but most significant bit has negative weight
b5 b4 b3 b2 b1 b0 bits
-(25) 24 23 22 21 20 weights (exponential form)
-32 16 8 4 2 1 weights (plain form)
1 0 1 0 1 0 codeword: false/true (de-)/selects
-32 0 8 0 2 0 effective place/bit value
-32 + 8 + 2 = -22 numeric value of codeword
Range: -2(N -1) to +(2(N -1) - 1) for N bits (not zero balanced),
Resolution: uniform, unity
Add/Subtract logic for 2’sC and BNN identical (except overflow),
not good for multiply/divide.
Large Hamming distance for small value codewords around
zero implies large switching energy, compared with SM code.
L2.3 Number Codes II: Real Numbers
Binary Coded Decimal (BCD) Number Codes
This is a code within a code.
Create ten "super-symbols" using groups of four binary symbols:
These 4-bit super-symbols represent numbers 0-9 (encoded by
BNN, or others), with six unused codewords.
Partition number value as base-10 place-value and encode with
new super-symbols. Using 4-bit BNN super-symbols, we have:

102 101 100 super-symbol (cardinal-10) place weight

3 2 9 three hundred and twenty nine
0011 0010 1001 12-bit BCD codeword: three 4-bit super-symbols

Can be sign encoded as well in different ways.

Use with further fixed-point or floating-point structure to generate
exact representation of 0.1, 0.2, etc., e.g. for legally exact
financial calculations. Convenient for numerical In/Out where
little arithmetic processing needed e.g. bank cards
Fixed-Point Number Codes
A modified version of BNN, SM, 2’sC, BCD codes which include a
"fraction point" beyond which the weights have negative exponents
and can thus represent a subset of rational numbers within range.
An example of fixed-point BNN code:
b5 b4 b3 b2 b1 b0 bits
23 22 21 20 2-1 2-2 weights (exponential form)
8 4 2 1 1⁄2 1⁄4 weights (plain form)
1 0 1 0 1 1 codeword: false/true (de-)/selects
8 0 2 0 1⁄ 2 1⁄ 4 effective place/bit value
8 + 2 + 1⁄2 + 1⁄4 = 103⁄4 (10. 75) numeric value of codeword
Range (for BNN variant shown): 0 to (2(N -F)- 2-F) for a total number
of N bits and F fractional bits,
Resolution: uniform, 2-F
Finite codeword size: missing values within range (c.f. integer)
Exact representation of 0.1, 0.2, 0.3, 0.4, 0.6, 0.7, 0.8, 0.9 is impossible
using fixed-point BNN regardless of codeword size.
Floating-Point Number Code: IEEE 754-1985
Ashenden p138 and on WWW
Actually a family of several similar codes, all have three fields: sign,
exponent and significand (or fraction, also called "mantissa"). In the 32-bit
base-2 (single-precision) format, the fields are 1 : 8 : 23 bits wide:
• Sign: 0 (+ve) or 1 (-ve), as in Signed Magnitude code
• Exponent: an 8-bit offset BNN code with bias +127 allowing for the
generation of very small to very large values by multiplying a normalised
value with 2E where E is the numeric value of the exponent that varies
from -126 to +127. Special codewords for exponent such as 00000000, 11111111
(-127, +128) are used to represent NaN, denorm, inf, zero.

• Significand: a 24-bit Fixed-Point BNN code with 23 fraction bits. Only

23 fraction bits are stored since the msb is considered as 1 by default
(thus dropped) generating a normalised value range of [1,2). (beware
that a de-normalised range also exists)
Floating-Point Number Codes: IEEE 754-1985
The numeric value of the code is then computed as:
Numeric value = (-1)sign × 2E × numeric value of Significand
For example, 1:10000001:11000000000000000000000 represents
the value -1× 22 ×1.75 = -7. Note that 10000001 represents 2 in
offset BNN with bias of +127 and the Significand can be written as
1.1100…0 in fixed-point BNN representing the value 1.75.
Special codewords indicate extreme accuracy or arithmetic issues:
Infinity (overflow), Tiny (close to zero, denormalised, reduced precision),
Underflow (±0, total loss of precision), Not_A_Number or NAN (0÷0 &c.)
The code cannot represent all Real numbers but a sub-set of the Rationals. The
exponent scaling gives a large range, at a cost to resolution. Resolution varies
across range and the gaps/holes between exactly represented values expand. For
example, just below 16,777,216 the resolution is 1 but it becomes 2 just above it.
This means that 16,777,217 is not specifically represented by the code and the
next number it exactly represents is 16,777,218. The variable resolution can be
written based on the lsb weight in significand (2-23) times the exponent factor (2E),
which is equal to 2E-23.
3. Combinational Logic
3.1 Boolean Implementation of Arithmetic Functions
Combinational Logic for Binary addition
Suppose we want to design a circuit to add two single bit numbers A and B.
0 and 1 now signify numerical values.
This is called a Binary Half Adder:
Truth table
A
A B Carry Sum
0 0 0 0
0 1 0 1 Sum
1 0 0 1
1 1 1 0 B
Boolean expression
Carry = A . B Carry
A
Sum = A . B + A . B Equivalent to: Sum
B
Sum = A⊕B Carry
Full Addition: 4-bit Example
Add two unsigned n-bit binary natural numbers. Let’s see an example of n = 4.
A3 :0 = { A3 ,A2 , A1 ,A0 } and B 3 : 0 = {. B 3 ,B 2 ,B1 ,B0 }
Representing
A3 23 + A2 22+ A1 21 + A0 20 and B 3 23 + B 2 2 2+ B 1 21 + B 0 20

Example: 11 + 7 = 18
D D D

❖ Full addition requires input carry and 1−bit Full Addition

output carry
❖ Addends are 4-bits, but result requires
5-bits (overflow)
●
Full Addition: 4-bit Example
Add two unsigned n-bit binary natural numbers. Let’s see an example of n = 4.
A3 :0 = { A3 ,A2 , A1 ,A0 } and B 3 : 0 = {. B 3 ,B 2 ,B1 ,B0 }
Representing
A3 23 + A2 22+ A1 21 + A0 20 and B 3 23 + B 2 2 2+ B 1 21 + B 0 20

Example: 11 + 7 = 18
D D D
Full Adder Truth Table 1−bit Full Addition
A B Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1 ●

1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Synthesising Truth Table: Karnaugh map
• A Karnaugh map is a table of cells with each cell representing one minterm (or maxterm).
• Maps for two variables have four cells, for three variables eight cells, for four variables
sixteen cells and so on.
• The cells are laid out so that moving from one cell to any adjacent cell results in a
change in one variable, i.e., hamming distance of 1 between codewords.
• Where a minterm is to be included in the logic function a 1 is written in the cell.
Otherwise a 0 is written in or it is left blank. Don’t cares can be also included and treated
as 1 or 0 as appropriate!
• Thus, any two adjacent cells that both contain a 1 represent terms that differ in one
variable and can be combined as: X.Y+ X.𝑌= ത X
• The map can be inspected for groups of ones and BC
their minimised form can be written.
A 00 01 11 10
• The minimisation relies on combining adjacent 1s into
0 1 1 0 1
groups as large as possible of given the group has a
size of power of 2 and a rectangular shape. 1 1 1 0 0
• Note that the maps have cyclic property and thus the
groups can be rolls over from left end to the right and 3-variable Karnaugh Map
so on.
Synthesising Truth Table: Karnaugh map
• A Karnaugh map is a table of cells with each cell representing one minterm (or maxterm).
• Maps for two variables have four cells, for three variables eight cells, for four variables
sixteen cells and so on.
• The cells are laid out so that moving from one cell to any adjacent cell results in a
change in one variable, i.e., hamming distance of 1 between codewords.
• Where a minterm is to be included in the logic function a 1 is written in the cell.
Otherwise a 0 is written in or it is left blank. Don’t cares can be also included and treated
as 1 or 0 as appropriate!
• Thus, any two adjacent cells that both contain a 1 represent terms that differ in one
variable and can be combined as: X.Y+ X.𝑌= ത X
• The map can be inspected for groups of ones and BC
their minimised form can be written.
A 00 01 11 10
• The minimisation relies on combining adjacent 1s into
0 1 1 0 1
groups as large as possible of given the group has a
size of power of 2 and a rectangular shape. 1 1 1 0 0
• Note that the maps have cyclic property and thus the
groups can be rolls over from left end to the right and 3-variable Karnaugh Map
so on.
Synthesising Truth Table: Karnaugh map
• A Karnaugh map is a table of cells with each cell representing one minterm (or maxterm).
• Maps for two variables have four cells, for three variables eight cells, for four variables
sixteen cells and so on.
• The cells are laid out so that moving from one cell to any adjacent cell results in a
change in one variable, i.e., hamming distance of 1 between codewords.
• Where a minterm is to be included in the logic function a 1 is written in the cell.
Otherwise a 0 is written in or it is left blank. Don’t cares can be also included and treated
as 1 or 0 as appropriate!
• Thus, any two adjacent cells that both contain a 1 represent terms that differ in one
variable and can be combined as: X.Y+ X.𝑌= ത X
• The map can be inspected for groups of ones and BC
their minimised form can be written.
A 00 01 11 10
• The minimisation relies on combining adjacent 1s into
0 1 1 0 1
groups as large as possible of given the group has a B
size of power of 2 and a rectangular shape. 1 1 1 0 0
• Note that the maps have cyclic property and thus the
groups can be rolls over from left end to the right and 3-variable Karnaugh Map
so on.
Synthesising Truth Table: Karnaugh map
• A Karnaugh map is a table of cells with each cell representing one minterm (or maxterm).
• Maps for two variables have four cells, for three variables eight cells, for four variables
sixteen cells and so on.
• The cells are laid out so that moving from one cell to any adjacent cell results in a
change in one variable, i.e., hamming distance of 1 between codewords.
• Where a minterm is to be included in the logic function a 1 is written in the cell.
Otherwise a 0 is written in or it is left blank. Don’t cares can be also included and treated
as 1 or 0 as appropriate!
• Thus, any two adjacent cells that both contain a 1 represent terms that differ in one
variable and can be combined as: X.Y+ X.𝑌= ത X
• The map can be inspected for groups of ones and BC
their minimised form can be written.
A 00 01 11 10
• The minimisation relies on combining adjacent 1s into
0 1 1 0 1
groups as large as possible of given the group has a B
size of power of 2 and a rectangular shape. 1 1 1 0 0
• Note that the maps have cyclic property and thus the
groups can be rolls over from left end to the right and 3-variable Karnaugh Map
so on.
Synthesising Truth Table: Karnaugh map
• A Karnaugh map is a table of cells with each cell representing one minterm (or maxterm).
• Maps for two variables have four cells, for three variables eight cells, for four variables
sixteen cells and so on.
• The cells are laid out so that moving from one cell to any adjacent cell results in a
change in one variable, i.e., hamming distance of 1 between codewords.
• Where a minterm is to be included in the logic function a 1 is written in the cell.
Otherwise a 0 is written in or it is left blank. Don’t cares can be also included and treated
as 1 or 0 as appropriate!
• Thus, any two adjacent cells that both contain a 1 represent terms that differ in one
variable and can be combined as: X.Y+ X.𝑌= ത X
• The map can be inspected for groups of ones and BC
their minimised form can be written.
A 00 01 11 10
• The minimisation relies on combining adjacent 1s into
0 1 1 0 1
groups as large as possible of given the group has a B
size of power of 2 and a rectangular shape. 1 1 1 0 0 A.C
• Note that the maps have cyclic property and thus the
groups can be rolls over from left end to the right and 3-variable Karnaugh Map
so on.
Karnaugh Map
Consider the following map for two variables. All four
minterms are present and given a truth table can be entered
B
in the map. Now assume the Kmap for truth table below:
A 0 1
0 A.B A.B

1 A.B A.B
Karnaugh Map
Consider the following map for two variables. All four
minterms are present and given a truth table can be entered
B
in the map. Now assume the Kmap for truth table below:
A 0 1
A B F 0 A.B A.B
B
0 0 1 1 A.B A.B
A 0 1
0 1 1
0 1 1
1 0 0
1 0 1
1 1 1

Truth table Truth table applied to map

Karnaugh Map
Consider the following map for two variables. All four
minterms are present and given a truth table can be entered
B
in the map. Now assume the Kmap for truth table below:
A 0 1
A B F 0 A.B A.B
B
0 0 1 1 A.B A.B
A 0 1
0 1 1
0 1 1
1 0 0
1 0 1
1 1 1

Truth table Truth table applied to map

• We can now draw loops round groups of 1s in

the map to represent the mimimised terms.
B
A 0 1
0 1 1
1 0 1
Karnaugh Map
Consider the following map for two variables. All four
minterms are present and given a truth table can be entered
B
in the map. Now assume the Kmap for truth table below:
A 0 1
A B F 0 A.B A.B
B
0 0 1 1 A.B A.B
A 0 1
0 1 1
0 1 1
1 0 0
1 0 1
1 1 1

Truth table Truth table applied to map

• We can now draw loops round groups of 1s in

Truth table Truth table applied to map

• We can now draw loops round groups of 1s in

the map to represent the mimimised terms.
B
A 0 1
0 1 1
1 0 1
A
Karnaugh Map
Consider the following map for two variables. All four
minterms are present and given a truth table can be entered
B
in the map. Now assume the Kmap for truth table below:
A 0 1
A B F 0 A.B A.B
B
0 0 1 1 A.B A.B
A 0 1
0 1 1
0 1 1
1 0 0
1 0 1
1 1 1

Truth table Truth table applied to map

• We can now draw loops round groups of 1s in

Truth table Truth table applied to map

• We can now draw loops round groups of 1s in

the map to represent the mimimised terms.
B
A 0 1
0 1 1
1 0 1
A
B
Karnaugh Map
Consider the following map for two variables. All four
minterms are present and given a truth table can be entered
B
in the map. Now assume the Kmap for truth table below:
A 0 1
A B F 0 A.B A.B
B
0 0 1 1 A.B A.B
A 0 1
0 1 1
0 1 1
1 0 0
1 0 1
1 1 1

Truth table Truth table applied to map

• We can now draw loops round groups of 1s in • Hence F = A + B directly from the
the map to represent the mimimised terms. map. We know how to reduce the
function using Boolean algebra too:
B
A 0 1
0 1 1
1 0 1
A
B
Karnaugh Map
Consider the following map for two variables. All four
minterms are present and given a truth table can be entered
B
in the map. Now assume the Kmap for truth table below:
A 0 1
A B F 0 A.B A.B
B
0 0 1 1 A.B A.B
A 0 1
0 1 1
0 1 1
1 0 0
1 0 1
1 1 1

Truth table Truth table applied to map

C C
A B in out AB
0 0 0 0 Cin 00 01 11 10 A⋅B
0 0 1 0 0 0 0 1 0
0 1 0 0 A⋅C in
0 1 1 1 1 0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1 B⋅C in
1 1 1 1
C = A ⋅ B+A ⋅ C + B ⋅ C
out in in
Full Adder synthesis:
AB
C
A B in Sum Cin 00 01 11 10
0 0 0 0
0 0 1 0 1
0 0 1 1
0 1 0 1
1 1 0 1 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0 Sum = 𝐴 ⋅ 𝐵 ⋅C i n +𝐴 .B⋅ 𝐶 𝑖𝑛 + A ⋅ B⋅C i n +𝐴 ⋅ 𝐵 ⋅ C i n
1 1 1 1

Using Boolean
algebra:
Full adder circuit #1

A
Sum
B
C
in

Sum = A ⊕ B ⊕ C in

C = A ⋅ B + A ⋅ C + B⋅ C C
out in in out
Full adder circuit #2

● Full adder can be C

in
Sum
made from 2-half A
B
adders and a 2- C out
input OR gate
C in
Sum Sum
A
Sum
B Half Adder
Sum = A ⊕ B ⊕ Cin Half Adder C out
Carry
Carry
C = A ⋅ B + A ⋅ C + B⋅ C
out in in

C = A ⋅ B + (A ⊕ B ) . C
out in
4-bit ripple carry adder

Full addition of A3 :0 = {A 3 , A 2 , A1 , A 0 } and B 3 :0 = {B 3 , B 2 , B 1 , B 0 }

generating S 3 :0 = {S 3 , S 2 , S 1 , S 0 }

A B3 A B2 A B1 A B0 An Bn
3 2 1 0

Cout + Cin
C
out + + + + C
in

Sn
S S S S Full adder symbol
3 2 1 0

Sum is generated as the carry ripples through the chain of adders

Ripple Carry Adder Critical Path
Critical path occurs when
●

– Carry generated at the lsb position propagates all the way to the msb position
– Carry consumed at msb position to produce the sum
Propagation delay from Cin to Cout : tcarry
●
Assume that both the delay from input signals
Propagation delay from Cin to Sum: tsum A0 (or B0) to Cout,0 for the lsb, and the Cin to
●
Cout delay for all other bits equal to tcarry .

Adder Truth Table: Carry Status

A B Cin Cout Sum Carry Status
– Critical path length linearly proportional 0 0 0 0 0 Delete
to N – increasingly significant for adders 0 0 1 0 1 Delete
0 1 0 0 1 Propagate
with wide data paths 0 1 1 1 0 Propagate
– Priority is to optimise tcarry rather 1 0 0 0 1 Propagate
1 0 1 1 0 Propagate
than tsum as tsum has minor 1 1 0 1 0 Generate
influence on total delay, tadder . 1 1 1 1 1 Generate
Example: Critical Path
Derive values of inputs An-1:0 and Bn-1:0 so that worst case delay is obtained for
ripple carry adder
– Carry generated in lsb position. If Cin,0 is 0, both A0 and B0 = 1 (see truth table,
Generate Carry Statusrow)
– All other stages in Propagate mode (see truth table), hence either Ai = 1 or Bi= 1
– Set up a 0 to1 transition on the msb sum bit:achieved by setting both An-1:0 and
Bn-1:0 to 0 (or 1).

For an 8-bit addition the following values of A7:0 and B7:0 set up a worst case delay:
A = { 0, 0, 0, 0, 0, 0, 0, 1}, B= { 0, 1, 1, 1, 1, 1, 1, 1}
Carry ripples through addition:
Subtraction
S = A− B is the same as S = A + ( − B)
● Create the code for -B from the input +B and then add to A to (-B)

● Any two's complement number can have its sign changed by

●

complementing and adding 1.

Two's Complement Addition
Use 4-bit two's complement numbers. Number range:
n−1
●

−2n −1
≤ MD < 2
3 3
●

−2 ≤ M < 2
i.e. -8 to +7 D
− 8 ≤ MD < 8
Add +3 to +4 :
D D

– result correct!
Further Examples

despite overflow!

despite overflow! out of range

Two's Complement Overflow
● Two overflow cases
– negative numbers:
●

– and positive numbers: out of range

–

● Overflow detected by
noting msb has changed:
out of range
Overflow = A n−1 ⋅ B n−1 ⋅ S n − 1 + A n−1 ⋅ Bn − 1 ⋅ S n −1
●
Binary Subtraction
Any two's complement number can have its sign changed by
●

complementing and adding 1.

Cin Cout Sum Overflow
A B B B B B
3 2 1 0
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 1 0 A A A A
3 2 1 0
0 1 1 1 0 0
1 0 0 0 1 0 C C = 1
+ + + +
out,3 in,0
1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0
S S S S
3 2 1 0
– Complement the bits of B and
add 1 to form -B anduse the
full adder to perform A + (-B) 4-bit Subtracter
i.e. subtraction.
Overflow
Overflow = C in ⊕ Cout
4-bit Adder/Subtracter
● Use an XOR gate as a selectable inverter:
bit B
invert n XOR bitinvert
0 0 0 B B B B
0 1 1 3 2 1 0

1 0 1
1 1 0 A A A A
3 2 1 0

C
out,3
+ + + +
S S S S
3 2 1 0

bit = 0 : adder
invert

bitinvert = 1 : subtracter
Overflow
3. Combinational Logic
3.2 CMOS Implementation of Boolean Functions
CMOS technology
● Complementary Metal Oxide Semiconductor
technology (CMOS)
– dominant integrated circuit technology
– implements digital circuits with high noise immunity
and low static power consumption
– implements analogue circuits and image sensors
– technology development over many decades has
provided ever smaller transistors
– current microprocessors contain hundreds of millions
of CMOS logic gates (transistors) on a single chip.
Switches in CMOS technology
● Two fundamental transistor/switch types: NMOS and PMOS transistors.

NMOS Transistors:
A
– ON/closed when control G = hi
G
– Poor conduction if A/B signals hi
– Good conduction of A/B signals lo
B
– Hence used in pull-down networks.

PMOS transistor
– ON/closed when control G = lo A
– Good conduction if A/B signals hi G
– Hence used in pull-up networks.
–

– Poor conduction of A/B signals lo B

●
CMOS inverter (NOT gate) V dd
in hi: M1 OFF, M2 ON, out lo V dd R1
in lo: M1 ON, M2 OFF, out hi M1 SW 1
in
out out
in out SW0
M2
R0
0V
Vdd
in
0V
0V ● Output signal with propagation delay,
Vdd
●
rise and fall time.
out
0V
Virtually no power consumption for
Imax
I static signals.
0A
● Power consumed when signals change.
time (S)
CMOS NAND gate Design
●
Output F lo (connected to 0V) only when both inputs are hi.
A B F V dd
A
F 0 0 1
B 0 1 1 Pull− up
1 0 1
network
F= A. B 1 1 0

0V
CMOS NAND gate Design
● Output F hi (connected to Vdd) when either input is lo.

A A B F V dd
F 0 0 1
B 0 1 1
1 0 1
F= A. B 1 1 0 A B
F

Pull− down
network

0V
CMOS NAND gate Design

A A B F V dd
F 0 0 1
B 0 1 1
1 0 1
F= A. B 1 1 0 F

0V
CMOS NAND gate Design

A A B F V dd
F 0 0 1
B 0 1 1
1 0 1
F= A. B 1 1 0 F

B
● Complete circuit
– When PMOS transistors
A
connect F to Vdd, NMOS
transistors do not connect to
0V (and vice-versa). 0V

– No short circuit between Vdd and 0V.

3-input CMOS NAND gate

A B C F
0 0 0 1 V dd
0 0 1 1
0 1 0 1
0 1 1 1
F
1 0 0 1
1 0 1 1 A
1 1 0 1
1 1 1 0 B

F= A. B. C C

0V
CMOS AND gate

● Not possible to V dd
implement AND
function with simple
pull-up and pull-down F
network
A
A F
B B

A F 0V
B
CMOS NOR gate Design
● Output F lo (connected to 0V) when either inputs is hi.

A A B F
F 0 0 1
V dd
B 0 1 0
1 0 0 Pull−u p
F= A+B 1 1 0
network

A B

0V
CMOS NOR gate Design
● Output F hi (connected to Vdd) when both inputs are lo.

A A B F V dd
F 0 0 1
B 0 1 0 A
1 0 0
F= A+B 1 1 0
B
F

Pull− down
network

0V
CMOS NOR gate Design
● Output F hi (connected to Vdd) when both inputs are lo.

A A B F V dd
F 0 0 1
B 0 1 0 A
1 0 0
F= A+B 1 1 0
B
● Complete circuit
– When PMOS transistors F
connect F to Vdd, NMOS
transistors do not connect to
0V (and vice-versa).
0V
– No short circuit between Vdd and 0V.
3-input CMOS NOR gate

V dd
A B C F A
0 0 0 1
0 0 1 0
B
0 1 0 0
0 1 1 0
1 0 0 0 C
1 0 1 0
1 1 0 0 F
1 1 1 0

F= A+ B+ C 0V
CMOS OR gate
● Not possible to V dd
implement OR A
function with simple
pull-up and pull-down F
B
network

A F
B

A F 0V
B
Number of transistors per gate
● Different gates require different numbers of transistors:
– 4 transistors for 2-input NAND and 2-input NOR
– 6 transistors for 2-input AND and 2-input OR
● Therefore in a CMOS implementation of a Boolean expression it is
more efficient to use NAND/NOR gates
● De Morgan's laws can usually be used to convert expressions into forms
using NAND and NOR.
Number of transistors per gate
● Different gates require different numbers of transistors:
– 4 transistors for 2-input NAND and 2-input NOR
– 6 transistors for 2-input AND and 2-input OR
● Therefore in a CMOS implementation of a Boolean expression it is
more efficient to use NAND/NOR gates
● De Morgan's laws can usually be used to convert expressions into forms
using NAND and NOR.
Example I: Define the minimum number of CMOS transistors required to
implement the following Boolean expression:

F= A. B
A F
B
8 transistors
Number of transistors per gate
● Different gates require different numbers of transistors:
– 4 transistors for 2-input NAND and 2-input NOR
– 6 transistors for 2-input AND and 2-input OR
● Therefore in a CMOS implementation of a Boolean expression it is
more efficient to use NAND/NOR gates
● De Morgan's laws can usually be used to convert expressions into forms
using NAND and NOR.
Example I: Define the minimum number of CMOS transistors required to
implement the following Boolean expression:

F= A. B |Apply De Morgan  F= A+B

A F A F
B B
8 transistors 6 transistors
Number of transistors per gate
● Different gates require different numbers of transistors:
– 4 transistors for 2-input NAND and 2-input NOR
– 6 transistors for 2-input AND and 2-input OR
● Therefore in a CMOS implementation of a Boolean expression it is
more efficient to use NAND/NOR gates
● De Morgan's laws can usually be used to convert expressions into forms
using NAND and NOR.
Example II: Minimise the number of CMOS transistors required:

F = A . B+ C . D
A
B F
C
D 18 transistors
Number of transistors per gate
● Different gates require different numbers of transistors:
– 4 transistors for 2-input NAND and 2-input NOR
– 6 transistors for 2-input AND and 2-input OR
● Therefore in a CMOS implementation of a Boolean expression it is
more efficient to use NAND/NOR gates
● De Morgan's laws can usually be used to convert expressions into forms
using NAND and NOR.
Example II: Minimise the number of CMOS transistors required:

F = A . B + C . D |Apply De Morgan  F = A . B . C . D
A A
B F B F
C C
D 18 transistors D 12 transistors
NAND versus NOR

● PMOS transistors have less drive strength than

NMOS transistors (for a given geometry)
– a majority carrier mobility issue
● NAND gates: PMOS in parallel, NMOS in series
● NOR gates: PMOS in series, NMOS in parallel
●
NOR gate slower: weaker PMOS transistors in
series (whereas in parallel in a NAND gate).
●
NAND gate faster than a NOR gate and typically
occupies less area than a NOR gate.
General CMOS gates
● Complex CMOS gates may be constructed for general logic functions.
● Equal number of NMOS and PMOS transistors
● Every NMOS transistor has an equivalent PMOS transistor
connected to the same input V dd
• Series pull-down
NMOS correspond to Pull−up
parallel pull-up PMOS n− inputs network
n−PMOS
• Parallel pull-down
n
NMOS correspond to in
out (out.)
series pull-up PMOS
● The gate may have an n− inputs n−NMOS
inverter after the pull- Pull−down
down/pull-up gate. network
0V
General CMOS gate: Form of Boolean expression
● Boolean expression must be of the form: F = (SOP) (SOP: Sum Of Products)
● Bar over whole term indicates an inverter is not needed at the output
No bar indicates the need for an inverter at the output of the pull-up/pull-
● down network: use inverse of the SOP expression to design
General CMOS gate: Form of Boolean expression
● Boolean expression must be of the form: F = (SOP) (SOP: Sum Of Products)
● Bar over whole term indicates an inverter is not needed at the output
No bar indicates the need for an inverter at the output of the pull-up/pull-
● down network: use inverse of the SOP expression to design
Example: Sketch a CMOS transistor network to implement
the Boolean expression: F = (A.B)+C
General CMOS gate: Form of Boolean expression
● Boolean expression must be of the form: F = (SOP) (SOP: Sum Of Products)
● Bar over whole term indicates an inverter is not needed at the output
No bar indicates the need for an inverter at the output of the pull-up/pull-
● down network: use inverse of the SOP expression to design
Example: Sketch a CMOS transistor network to implement
the Boolean expression: F = (A.B)+C

Pull-down network implementation:

– Connect F to 0V when A is hi AND B is hi
OR C is hi
General CMOS gate: Form of Boolean expression
● Boolean expression must be of the form: F = (SOP) (SOP: Sum Of Products)
● Bar over whole term indicates an inverter is not needed at the output
No bar indicates the need for an inverter at the output of the pull-up/pull-
● down network: use inverse of the SOP expression to design
Example: Sketch a CMOS transistor network to implement V dd
the Boolean expression: F = (A.B)+C Pull - up
network

Pull-down network implementation: F

– Connect F to 0V when A is hi AND B is hi A
OR C is hi C

Pull-up network: rearrange expression C

using De Morgan:
F
F = (A+B).C
Connect F to Vdd when A is lo OR B is Pull−down
lo AND C is lo. network

0V
General CMOS gate: Form of Boolean expression
● Boolean expression must be of the form: F = (SOP) (SOP: Sum Of Products)
● Bar over whole term indicates an inverter is not needed at the output
No bar indicates the need for an inverter at the output of the pull-up/pull-
● down network: use inverse of the SOP expression to design
Example: Sketch a CMOS transistor network to implement V dd
the Boolean expression: F = (A.B)+C B
A
Pull-up network: rearrange expression
C
using De Morgan:
F
F = (A+B).C A
Connect F to Vdd when A is lo OR B is C
lo AND C is lo. B
0V
L4.1 The D-Flip Flop
Circuit-level feedback
Feedback over one invertor: '1' ' 0' ' 0' '1'
• Signal feedback gives new behaviour
• Signal feedback around one inverter is
unstable 5V 5V
– Behaviour may be used as basis of an
analogue oscillator but useless for 0V 0V
constructing controlled-time logic systems. t t
t PD tr = t f = 0 t PD < t r = t f

Feedback over two invertors:

'1' ' 0' '1'
• Signal feedback around two inverters is stable
• Signal may adopt one of two stable conditions
'0 '1' ' 0'
• Useful for constructing logic systems
–

'
– if a particular stable condition can be set by other
–

5V
(combinational) circuit signals.
0V
t
Circuit-level feedback: External Control
Add switches to input (Sin) and feedback (Sfb) paths:
S fb

' 0' S in ' 0' '1' ' 0'

D '1' '1' ' 0' '1'
Q

With Sin closed/ON and Sfb open/OFF:

– Circuit is a feed forward combinational logic circuit
– Input signal D defines inverter inputs and outputs.

Sfb

'X'
S in ' 0' '1' ' 0'
D 'X' '1' ' 0' '1'
Q
–

Activate feedback ( Sfb closed/ON) and isolate Input D (Sin open/OFF)

–

– to freeze this stable circuit state.

– the state of signal D at time of switching stored, visible at Q.
Switches in CMOS technology
● Two fundamental transistor/switch types: NMOS and PMOS transistors.

NMOS Transistors:
– ON/closed when control G = hi A
– Poor conduction if A/B signals hi G
– Good conduction of A/B signals lo
– Hence used in pull-down networks.
B
PMOS transistor
– ON/closed when control G = lo A
– Good conduction if A/B signals hi G
– Poor conduction of A/B signals lo
– Hence used in pull-up networks.
B
–

● Neither NMOS nor PMOS transistors suitable for conducting BOTH hi and lo
values on A/B.
●
Transmission Gate/Switch
• Combine an A/B-hi switch (PMOS) with an A/B-lo switch (NMOS)

• Complementary G control gives both-ON or both-OFF A/B signal path

• NMOS carries current when A/B lo
• PMOS carries current when A/B hi
• On resistance of switch is not zero and may be significant.

G = lo
G G
G
A B A B G = hi

G
D-Latch (Positive Transparent Latch)
• Combining circuit-level feedback with control by transmission gates gives
simple memory element
When G is hi ('1'):
– D/Q path transparent
– Q follows D in simple combinational behavior

As G makes hi-lo transition (falling edge):

– Q output frozen
– Non-combinational behaviour, Q ignores changes in input signal D

D Q
G G
D Q
G Q
Q G
G G
D-Latch Waveform Diagrams

G = hi G = lo

G = lo G = lo G = hi G = hi
D Q D Q

G = hi Q G = lo Q

G = hi (transparent) G = lo (memory)

Q
D-Latch Operation Table
● Assume positive logic convention (lo = 0, hi = 1)
● Q- indicates value of Q just before a change in G

G D Q
1 1 1 transparent
●
1 0 0 transparent
↓ * D input value captured
●

0 * Q- output value held

●

– Transparent condition can be a problem with a feedback

path from Q to D (finite state machines)
– D flip-flop (two D-latches in series) overcomes this problem
D-Flip-Flop (Master-Slave Latch)

Data Data
● When clock is lo: in
D Q D Q out
– master transparent Master Slave
Q Q
– slave retains memorised G G
Clock
–

output
● At clock lo – hi transition:
– master stores input, slave transparent D Q

– slave passes master stored value to output

– Data in sampled at rising edge of clock Clk Q
signal, stored and passed to Data out
9
D-Flip-Flop: Switch/Inverter Model
open
Transparent Memory
D Q

Clock signal lo

open
Memory Transparent
D Q

Clock signal hi

No transparent through path on either phase of the clock signal!

Positive edge triggered D Flip-Flop

Data Data
D Q D Q out D Q
in
Master Slave
Q Q Clk Q
G G
Clock

Clock

Q
Positive D Flip-Flop: Operation Table

● Not combinational, so doesn't have a truth table,

but can construct something similar
●

Clk D Q
0 * Q- emit stored value
1 * Q- emit stored value
●
↓ * Q- emit stored value
* D input value captured
●

– BUT what happens if the D input signal changes (in the

master latch) just as the clock signal lo to hi transition
is capturing its value?
D Flip-Flop: Sample Window Failure

DANGER ZONE
input data (D)
input data transitions input data
may change forbidden may change
IN IN OUT
D Q

OUT
t SU t PD
Clk
Clock
th th
t SU t PD Clock

time zero
reference

• Circuit imperfections creates small timing window around rising

clock edge where input sampling process may fail catastrophically
D-Flip-Flop: Sample Window Failure
Summary: Positive Edge Triggered D Flip-Flop
• Near ideal sequential logic gate
– clock controlled, non-transparent memory device
• Snapshot of D input signal value stored and sent to Q output
– by the rising edge of the clock
• Clock signal and D flip-flops enable
– Synchronisation of activity across large systems giving
– Parallel and serial co-ordinated operations
● Standard element of many semi-custom fabrics
– Field Programmable Gate Array (FPGA)
• Standard element of highly optimised designs available in full-
custom design libraries (ASIC)
• D-Latch circuit simpler (smaller/faster) BUT
– tricky behaviour
– design process more complex (longer/expensive), so
– D-type Flip-Flop usually preferred
L4.2 Memory
SRAM: Static Random Access Memory
• Static: does not require any refresh mechanism to maintain memory contents
• Random Access: information stored in SRAM arrays accessed in any order
• Memory: ability to store bits of information for subsequent use
• Read/Write (R/W): R/W control line distinguish between reading and writing.
- SRAM cells may be read by a sense amplifier and written by a driver
• SRAM cells are volatile: memory content lost when power supply switched off
• SRAM used in microprocessors, FPGAs, ASICs etc to provide on chip storage
SRAM Cell:
• Feedback around 2 invertors with NMOS replacing transmission gates
– Higher design complexity compared to D-FF
WL
– But only uses two NMOS transistors

• Bit to be stored/read differentially

– improves noise margin
– access to both nodes of cell required
M1 M2
– access to cell enabled by word line (WL)
BL : bit line BL
SRAM array (small example)

WL 1

A0
( Address
bus )
WL 0

Row
Decoder

BL 0 BL 0 BL 1 BL 1
R/ W Sense amplifier (read) Sense amplifier (read)
(Control signal) Driver (write) Driver (write)

(Bi−directional data bus) Bit 0 Bit 1

SRAM array: read operation

1 0 0 1
A0 = 1
ON ON ON ON

Row X X X X
Decoder
OFF OFF OFF OFF
1 0 0 1
R/ W = 1 Sense amplifier (read) Sense amplifier (read)

Data bus set to outputs Bit 0 = 1 Bit 1 = 0

SRAM array: write operation

0
X X X X
A0 = 0
OFF OFF OFF OFF

0 1 1 0
Row
Decoder
ON ON ON ON
0 1 1 0
R/ W = 0
Driver (write) Driver (write)

Data bus set to inputs Bit 0 = 0 Bit 1 = 1

Generic SRAM array k bits Memory unit
Address
• Bi-directional data bus carries data input, data output 2 k words :
bus
n bits per
• Memory contains 2k n bits (2k n-bit words) R/ W word

• k bit address bus selects one word out of 2k n bits

● Write asserted (R/W = 0): data bus input stored in memory unit

● Read asserted (R/W = 1): data transferred from memory Data bus

to data bus output L− k

Bit
2 lines Storage
Ak cell
Example: SRAM memory array with 1
A k+1
20 3 Word
million (2 ) 8 bit (2 ) words A L −1
line
20 3
– aspect ratio 2 /2 Row
Decoder M.2 k
– height ~128,000 times larger than width
Sense amplifiers
– not implementable R/ W Drivers

• Column decoder is required to include

A0
multiple words in each row for Column Decoder
A k −1
improving aspect ratio
Data input/ output: M bits
DRAM: Dynamic Random Access Memory
● Dynamic: requires a refresh mechanism to maintain memory contents
⎼ due to leakage of charge from capacitor
⎼ DRAM slower than SRAM

● Size: DRAM more compact than SRAM (1:4 ratio)

⎼ hence DRAM popular for large memories
⎼ external memory in microprocessor systems
● DRAM cells are volatile
DRAM cell consists of one NMOS transistor WL: Word Line
M1 and a Capacitor C
Write operation:
– set BL hi/lo depending on bit to be stored M1
– WL = hi, transistor M1 ON C
– hi/lo on BL line stored: charge/discharge C
– WL = lo, transistor M1 OFF
– voltage on capacitor isolated (stored) BL: Bit Line
DRAM Cell: Read Operation WL
– WL = lo, M1 OFF: voltage on capacitor isolated
– Pre-charge BL to VPRE=Vdd / 2 M1
C
– WL = hi, M1 ON
BL
– Charge redistribution takes place between capacitor C
and parasitic capacitance of BL, CBL M1
𝐶
Δ𝑉 = 𝑉𝐵𝐿 − 𝑉𝑃𝑅𝐸 = (𝑉𝐵𝐼𝑇 − 𝑉𝑃𝑅𝐸 ) V BIT V BL
𝐶 + 𝐶𝐵𝐿
C C BL
Ratio C/(C + CBL) typically 1% - 10%; ΔV ≈ 250 mV typ.

– Voltage change on BL “sensed” and the capacitor

charge is refreshed back WL
V DD V Sense
VBIT : Voltage of stored bit BL
V PRE
VC : voltage on storage capacitor
V T :threshold voltage of NMOS VC GND V DD − V T
Sensing
DRAM Control Signals
Address multiplexed in time on address bus
● Row address strobed (RAS) into row address latch on falling edge of RAS
control signal
● Column address strobed (CAS) into column address latch on falling edge of
CAS control signal
● Read/write controlled by WE control signal
– WE hi: memory read
Address
– WE lo: memory write
bus
k
Example: Write operation timing DRAM
RAS
Address bus
CAS
Row Address Column Addr.
WE
RAS
m
CAS
Data
WE
bus
Data bus Valid
Read Only Memory (ROM)
• Non-volatile: memory content not lost when power supply switched off
• Random Access: information stored in SRAM arrays accessed in any order
• Mask ROM: ROM contents may be programmed at manufacture
• PROM: ROM contents may be programmed by blowing fusible links
• EPROM: ROM may be electrically programmed and erased by UV light
• EEPROM: ROM may be programmed and erased electrically
• N-bit address is decoded to activate one of the inputs to the ROM array.
• Access to data is very fast (typically 20nS)

Address Data
ROM
Decoder
Array
N M
Simple MOS ROM: internal architecture
V DD
• Bit lines connected to PMOS load transistors
• NMOS transistor exists in a cell if a cell is
storing a logic 0 W 1 =0

• Cell storing a logic 1 has no NMOS: BL Off Off

pulled up by PMOS

Address = 012
W 2 =1

Decoder
Example: Let address bus = 01 On On

Decoder outputs logic 1 on W2 W 3 =0

word line only. Off

All NMOS transistors in this

W 4 =0
word line are on. All other
Off Off
NMOS transistors are off. Data
B3 = 1 B 2= 0 B1 = 1 B0 = 0
On NMOS transistors pull bit line
low – otherwise high. Simplified 16-bit MOS ROM
(4-words of 4-bits)
●
Combinational logic functions using a ROM

● ROMs have N address inputs and M data outputs

– ROM outputs may be thought of as implementing any
combinational logic function defined in the "truth table".

Address Data
A2 A1 A0 D3 D2 D1 D0
0 0 0 0 0 0 0
Address 0 0 1 0 0 0 0
ROM 0 1 0 0 0 0 0
0 1 1 0 0 0 0
N
1 0 0 0 0 0 0
M 1 0 1 0 0 0 0
1 1 0 0 0 0 0
Data 1 1 1 0 0 0 0
L4.3 Shift Registers
Two D flip-flops in series

● On every active (positive) clock edge

– Din is loaded into flip-flop A and appears at QA while
– QA is loaded into flip-flop B and appears at QB
– Information is shifted one flip-flop to the right.

QA QB
Clock
D D Q D Q Din
in A B
Clk Clk QA
Clock QB

Dr Alister Hamilton, School of Engineering, University of Edinburgh

Shift register: D flip-flops in series
– Input data applied to Din - data arrives serially one bit at a time. Data shifted
one flip-flop to the right on active clock edge.
– This shift register has serial input - parallel output data – and is called a SIPO
shift register. QA QB QC QD

Din DAQ DBQ DC Q DD Q

Clk Clk Clk Clk
Clock

Clock

Din
QA
QB
QC
QD
SIPO Shift register application
● Switch debounce using an 8-bit shift register. Switch
● open – shift register fills up with logic 1's
– Out is a logic 1
● Switch closed – shift register fills up with 0's
– Out is a logic 0

+ve PSU
Out
R QA QB QC QD QE QF QG QH
D Q D Q D Q D Q D Q D Q D Q D Q
Switch Clk Clk Clk Clk Clk Clk Clk Clk

Clock −1 kHz

Dr Alister Hamilton, School of Engineering, University of Edinburgh

SIPO Shift register application

Time QA QB QC QD QE QF QG QH Out
1mS 1 1 1 1 1 1 1 1 1
2mS 0 1 1 1 1 1 1 1 1
3mS 1 0 1 1 1 1 1 1 1
4mS 0 1 0 1 1 1 1 1 1
5mS 1 0 1 0 1 1 1 1 1
6mS 0 1 0 1 0 1 1 1 1
bounce 7mS 0 0 1 0 1 0 1 1 1
8mS 0 0 0 1 0 1 0 1 1
9mS 0 0 0 0 1 0 1 0 1
10mS 0 0 0 0 0 1 0 1 1
11mS 0 0 0 0 0 0 1 0 1
12mS 0 0 0 0 0 0 0 1 1
13mS 0 0 0 0 0 0 0 0 0
14mS 0 0 0 0 0 0 0 0 0

debounced output
The Multiplexer
● A combinational logic circuit that selects one of two (or more) logic input
signals to output onto a single logic output.
● In general, an N-bit control signal, C, selects the output from 2N input signals.
Example: Generate a truth table circuit for 2-to-1 multiplexer (N = 2)
– 3 inputs A, B and C for truth table; 23 = 8 input combinations.
A B C F
– When C is high, let F = A and when C is low, let F = B 0 0 0 0
0 0 1 0
C 0 1 0 1
0 1 1 0
A A 1 0 0 0
F F 1 0 1 1
B B
Mux 1 1 0 1
C 1 1 1 1
AB
A
C C
F = A.C + B.C F
B
Alternative designs for a 2-to-1 Multiplexer
NAND-only design: Apply De Morgan's laws and use the equivalent expression
for circuit implementation:
A
C
F = A.C + B.C F = A.C . B.C F
B

Design using Transmission Gates: For this design the output is not directly
connected to Vdd or 0V so Output signal, F, drive strength dependent upon drive
strength of inputs A, B and properties of transmission gate

A
F

C
Parallel Input Serial Output (PISO) Shift Register
● Formed by a cascade of multiplexers and D flip-flops.
C
● A 2-to-1 multiplexer is combined with each D flip-flop A
– D flip-flop input can come from one of two sources,
B F D Q
A or B determined by control bit C.
Clk Q

● Load/shift high: D flip-flops loaded with B0 – B3 on active clock edge.

● Load/shift low: data shifts right on clock edge.
B0 B1 B2 B3

Load /
shift AC AC AC AC
F F F F Dout
Logic 0 B D Q B D Q B D Q B D Q
Clk Clk Clk Clk
Clock
PISO Shift Register application
● Converting parallel data to serial data for transmission down a serial
communication link.
● Data is stored in computer systems in parallel form.
– For example in an 8-bit register
• But data may be transmitted between computers in serial form
– Over a communications link e.g. a wireless radio link
• Data may be corrupted in transmission
– Data may be protected against corruption using coding techniques (using parity bits).
Assume B0 = 1, B1 = 0, B2 = 1, B3 =0 for timing diagram below:

Clock

Load / shift
QA 1

QB 0
1
QC
Q D or D out B3 = 0 B2 B1 B0
Error control using Parity Bits
• Parity bit: an extra bit added to data. Used in the simplest error detecting code.
• Even parity: parity bit chosen to ensure there is an even number of logic 1s in
the whole data word.
• Odd parity: parity bit chosen to ensure there is an odd number of logic 1s in
the whole data word.
3 bits data with parity bit
Example: 3-bit data words with even and of data even odd
odd parity bits indicated in bold: 000 0000 1000
Draw a truth table and K-map for Even parity: 101 0101 1101
• 3 inputs B0, B1 and B2; 23= 8 input combinations 111 1111 0111
• Odd parity output, Podd and even parity output, Peven
B0 B1 B2 Podd. Peven
The checkerboard pattern in K-map indicates 0 0 0 1 0
that even parity can be implemented using XORs! 0 0 1 0 1

B0 B 1 0 1 0 0 1
B2 0 1 1 1 0
1 0 0 0 1
Peven = B0⊕ B 1 ⊕B 2 1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
PISO Shift Register transmitter with parity bit
● Load/shift high: D flip-flops loaded with B0 – B3 (data with even parity bit, B3)
on active clock edge.
● Load/shift low: data shifts right on clock edge.

● Even parity bit, Peven, generated using XOR gates. B0

P even = B3
B1
– Podd is simply the inverse of Peven. B2

B0 B1 B2 B3 = Peven = B0 ⊕B1⊕
B2
Load /
shift AC AC AC AC
F F F F D out
Logic 0 B D Q B D Q B D Q B D Q
Clk Clk Clk Clk
Clock
Serial data receiver circuit with parity check
● Receives data from a serial communication link using a SIPO shift register
converting it to parallel data
● XOR gates perform a parity check – simple form of error detection. The error
is declared if even parity is not satisfied and requestion is sent for
retransmission. Q A
Q B Q Q C D

Serial data input D Q D Q D Q D Q

●

Clk Clk Clk Clk

Clock

● Possible errors occur due to noise in circuits

although error rate is very small (e.g., 10-12)
in computer networks.
● Adding a single parity bit (e.g., even parity) is
the simplest form of error control and much
stronger codes can be used. Parity Check
VL5.1 Introduction to FSM and ASM Chart
Finite State Machines — The State Register
STATE REGISTER
IN 0 OUT0
D Q CLOCK CONTROLLED
CODEWORD MEMORY
Ck
codeword:
codeword X(t) n bits in − n bits out bits codeword X(t−1)
CLOCK unchanged BUT
n delayed one clock cycle n

OUTPUT IS STORED COPY

OF INPUT AT END OF
PREVIOUS CLOCK CYCLE
IN n−1 OUT n −1
D Q
PARALLEL FLIP−FLOPS
Ck DISTINCT IN/OUT PAIRS
SAME CLOCK SIGNAL

CLOCK

CLOCK
For RTL-layer design, the Finite St at e Machine (FSM) is a
general model capable of describing all machine structure and
behaviour. Other ("architectural") techniques exist, but are less
systematic, so require more human intervention.

2
ELEE08015 Digital System Design 2 Finite State Machine Design
... review

RELATIONAL/FUNCTIONAL LAYER(S) (PSL, UML)

increasing volume of design data - automation increasinglyimportant

design effort spent on the "big picture" - low-layer issues done later
design data: focus on PROBLEM features rather than solution details
increasing abstraction - escape from imperfect physicalproperties

decreasing abstraction - better prediction of speed / power / cost

ALGORITHMIC/PROCEDURAL LAYER(S) (ASM Chart, C, Matlab)
design data: SOLUTION structure: SEQUENCE not timing, VALUE not codewords
NUMBER−level operations and data

REGISTER TRANSFER LAYER (RTL)

design data: DISCRETE (digital) timing, DISCRETE (digital) amplitude
timing: CLOCK period | amplitude: binary CODEWORDS
CODEWORD−level operations and data

GATE LAYER (NETLIST)

design data: approximate analogue timing, DISCRETE (digital) amplitude
timing: propagation delay &c. | amplitude: pure TRUE/FALSE bits
BIT−level operations and data
PHYSICAL LAYOUT LAYER (BITSTREAM)
design data: analogue timing and amplitude
timing, power and area predictions nearly exact but onerous

Now at RTL layer, building machinery to support Algorithmic layer

3
ELEE08015 Digital System Design 2 Finite State Machine Design
Finite State Machine Classification (RTL Block Structure)

Class-1 FSM
(codeword feed-forward only)
Delay Machine, Pipeline Machine

INPUT COMBINATIONAL SEQUENTIAL COMBINATIONAL SEQUENTIAL COMBINATIONAL OUTPUT

GATES GATES GATES GATES GATES

CLOCK CLOCK

CLOCK regulates codeword flow through the machine.

Processing split into discrete stages (simple algorithm).

4
ELEE08015 Digital System Design 2 Finite State Machine Design
Finite State Machine Classification (RTL Block Structure)

Class-2 FSM
(codeword feedback, output without external input)
State-Output Direct State-Transition Machine
CURRENT−STATE CODEWORD

NEXT-STATE NEXT−STATE STATE OUTPUT MAPPING

LOGIC CODEWORD REGISTER LOGIC OUTPUT

COMBINATIONAL SEQUENTIAL COMBINATIONAL

GATES GATES GATES

CLOCK
Codeword feedback gives a complex behaviour but internal state clock
regulates codeword flow through State Register.
Internal state in state register evolves and determines output.

5
ELEE08015 Digital System Design 2 Finite State Machine Design
Finite State Machine Classification (RTL Block Structure)
Class-3 FSM
(codeword feedback, external input)
State-Output Conditional State-Transition Machine (Moore*)
CURRENT−STATE
CODEWORD

NEXT-STATE NEXT−STATE STATE OUTPUT MAPPING

LOGIC CODEWORD REGISTER LOGIC OUTPUT
INPUT
COMBINATIONAL SEQUENTIAL COMBINATIONAL
GATES GATES GATES

CLOCK
Codeword feedback gives complex behaviour but internal state clock
regulates codeword flow through State Register.
External input history modifies internal state hence the output.

* Moore, E.F. (1956) "Gedanken-experiments on Sequential Machines" Automata Studies, Annals of Mathematical Studies, 34,
129-153. Princeton University Press

6
ELEE08015 Digital System Design 2 Finite State Machine Design
Finite State Machine Classification (RTL Block Structure)
Class-4 FSM
(codeword feedback, external input, I/O bypass)
Conditional-Output Conditional State-Transition Machine (Mealy*)

CURRENT−STATE
CODEWORD

NEXT-STATE NEXT−STATE STATE

LOGIC CODEWORD REGISTER OUTPUT MAPPING
INPUT OUTPUT
COMBINATIONAL SEQUENTIAL LOGIC
GATES GATES
COMBINATIONAL
GATES

CLOCK

External input can bypass state register to control output

Poor Structure - output is not clock regulated and thus the signal
delay control inadequate for large-scale design.

* Mealy, George H. (September 1955). "A Method for Synthesizing Sequential Circuits". Bell Systems Technical Journal

7
ELEE08015 Digital System Design 2 Finite State Machine Design
Larger-Scale Machine Structures: Modularity and Linked FSM

FSM A FSM B FSM D

CURRENT −STA T CURRENT −STA T CURRENT −STA TE
E CODEW ORD E CODEW ORD CODEWOR D

NEXT-STATE NEXT−STATE STATE OUTPUT MAPPING NEXT-STATE NEXT−STATE STATE OUTPUT MAPPING NEXT-STATE NEXT−STATE STATE OUTPUT MAPPING
LOGIC CODEWORD REGISTER LOGIC OUTPUT LOGIC CODEWORD REGISTER LOGIC OUTPUT LOGIC CODEWORD REGISTER LOGIC OUTPUT
rN PU T
rN PU T
GATES COMBINATIONAL SEQUENTIAL COMBINATIONAL GATES
GATES COMBINATIONAL SEQUENTIAL COMBINATIONAL
COMBINATIONAL SEQUENTIAL COMBINATIONAL GATES
GATES GATES
GATES
GATES GATES

CLOCK CLOCK
CLOCK

CLOCK CLOCK CLOCK

FSM C FSM E OUTPUT X

INPUT 1 CURRENT −STA T CURRENT −STA TE
CODEWOR D
E CODEW ORD

NEXT-STATE NEXT−STATE STATE OUTPUT MAPPING NEXT-STATE NEXT−STATE STATE OUTPUT MAPPING
LOGIC CODEWORD REGISTER LOGIC OUTPUT LOGIC CODEWORD REGISTER LOGIC OUTPUT
rN PU T
rN PU T
COMBINATIONAL SEQUENTIAL COMBINATIONAL GATES
COMBINATIONAL SEQUENTIAL COMBINATIONAL GATES
GATES GATES
GATES
GATES

CLOCK CLOCK

CLOCK CLOCK
INPUT 2

Two keys to control behaviour and design of large-scale machines:

Synchronisation of all FSMs (states) by a common clock and
modularity in the design by dividing a single large problem into many
smaller ones. We can build non-finite state machines, using FSMs ...

8
ELEE08015 Digital System Design 2 Finite State Machine Design
The FSM - RTL Structure: Shows Body but not Soul
FINITE STATE MACHINE: STRUCTURE in Register Transfer Language
(current state codeword FEEDBACK)

current state codeword

j bits
COMBINATIONAL GATES SEQUENTIAL GATES COMBINATIONAL GATES
(TRUTH TABLE (AND, OR,NOT)) next state codeword (+ve edge D-FF) current state codeword (TRUTH TABLE (AND, OR, NOT)) output codeword
j bits j bits j bits l bits

input codeword NEXT-STATE LOGIC STATE REGISTER OUTPUT MAP LOGIC

k bits CALCULATE NEW STORE CURRENT CALCULATE CURRENT
STATE CODEWORD STATE CODEWORD OUTPUT CODEWORD
(ENCODED OPERATION) (memory) (CODE TRANSFORMATION)

LOGIC LAYER THE CLOCK

TIME CONTROL SIGNAL:

EACH OF THESE LANGUAGES DESCRIBES AN ASPECT OF THE FSM

FINITE STATE MACHINE: BEHAVIOUR in Codeword/Delay language
NONE CLEARLY SHOWS THE RELATIONSHIP OF INTERNAL STATES

WHAT IS IT THINKING?...
CODED VALUES & OPERATION CODED VALUES & OPERATION
input output input output INTERNAL STATE ORGANISATION
a2 a1 a0 b1 b0 y1 y0 z1 z0 Output is COPY of input a2 a1 a0 b1 b0 y1 y0 z1 z0
1 0 1 1 0 0 1 1 1 FROM
1 0 1 1 0 0 1 1 1 ...ANOTHER LANGUAGE IS NEEDED
1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0
1 0 1 0 PREVIOUS CLOCK PERIOD 0 1 1 1 0 1 0 1 0
0 1 1 1 0
VIH DANGER ZONE VIH
A LOGIC LANGUAGE description of MORE A LOGIC LANGUAGE description of MORE 50%
transitions forbidden
input data (D)

50%
rN
ABSTRACT LANGUGE, suitable for ABSTRACT LANGUGE, suitable for VIL
VI VO
OUT
VIL
VI VO
IN
translation to PHYSICAL circuits and signals translation to PHYSICAL circuits and signals VOH
time OUT D Q VOH
time

tsu tPD
50%
tPHL/ tPLH tdf / tdr
CLOCK Ck 50%
tPHL/ tPLH tdf / tdr
VOL VOL
t su th

tPLH tPHL time t PD th CLOCK

tPLH tPHL time
tdr tdf tdr tdf

New BEHAVIOUR due to feedback POORLY EXPRESSED

time zero reference

Arrangement of INTERNAL STATES CRYPTIC sort out physical-layer imperfections ... later

RTL structure brings circuit clarity, but limited insight into behaviour
The state structure (evolving in the state register) gives a complex behaviour.
The abstract state structure is obscure - only physical storage obvious in RTL

9
ELEE08015 Digital System Design 2 Finite State Machine Design
... REVIEW

RELATIONAL/FUNCTIONAL LAYER(S) (PSL, UML)

increasing volume of design data - automation increasinglyimportant

design effort spent on the "big picture" - low-layer issues done later
increasing abstraction - escape from imperfect physicalproperties design data: focus on PROBLEM features rather than solution details

decreasing abstraction - better prediction of speed / power / cost

ALGORITHMIC/PROCEDURAL LAYER(S) (ASM Chart, C, Matlab)
design data: SOLUTION structure: SEQUENCE not timing, VALUE not codewords
NUMBER−level operations and data

REGISTER TRANSFER LAYER (RTL)

design data: DISCRETE (digital) timing, DISCRETE (digital) amplitude
timing: CLOCK period | amplitude: binary CODEWORDS
CODEWORD−level operations and data

GATE LAYER (NETLIST)

The ASM chart is an ALGORITHMIC-LAYER language which will be

discussed next. It expresses the behaviour of internal state and external
output as a function of internal state combined with external input.

10
ELEE08015 Digital System Design 2 Finite State Machine Design
The Finite State Machine
(Algorithmic) State Machine, ASM, FSM
Combinational logic (Truth Table) gives simple behaviour:
• output depends directly on input
Feedback in FSM structure produces complex behaviour: output depends
on internal state which depends on sequence of many past inputs, e.g.
• Constant input (or none) may give regularly (clock) changing output
• Regularly changing input may give constant output
Output depends on current internal state
• The evolution of the current state is influenced by external input, if any
• Number and arrangement of possible states finite/fixed (hence name)
Engineer designs abstract state structure:
a) number of states, b) their relation to input and c) their control of output
- Automation (+help) translates state structure to physical circuit
• can synthesise many circuits with same behaviour - physical differences

11
ELEE08015 Digital System Design 2 Finite State Machine Design
The ASM Chart Language:
A formal language with precise usage and meaning (strict grammar)
• elements may only be used as formally defined
— Cannot invent our own language interpretation
* not a flowchart - different language/syntax/semantics
— Formality necessary for automated processing – CAD
Symbolic and Easy to Read/Write
Strong Structure:
• Most types of incompleteness are obvious
• Most types of ambiguity are obvious

Simple graphical composition (3 or 4 elements)

• Relationships between internal states clearly visible
• Selection of input by internal state clearly visible
• Control of output by internal state clearly visible

12
ELEE08015 Digital System Design 2 Finite State Machine Design
ASM Chart: Illustration of Correct Construction (Syntax)
(Class 3 FSM: conditional transition, state output)

Each rectangle represents a state

EAGER GRUMPY DOZY
LOOK, RUN LOOK LOOK

• unique codeword in state register

0 1 0
COLD && WET COLD
ASLEEP

• single state per clock period 1

COLD
0

• State controls output 1

WET

Each diamond groups a mini truth table

• ideal combinational function (zero delay & transition time)
• distinct function of selected inputs for each state
Ideal (abstract) logic and sequence. CURRENT-STATE
CODEWORD

No imperfect (physical) properties: NEXT-STATE

voltage, propagation delay, setup time, ...

NEXT−STATE STATE OUTPUT MAPPING
LOGIC CODEWORD REGISTER LOGIC OUTPUT

COMBINATIONAL SEQUENTIAL COMBINATIONAL

GATES GATES GATES

only stable values in ordered sequences CLOCK

13
ELEE08015 Digital System Design 2 Finite State Machine Design
Elements (Vocabulary) of the ASM Chart Language

STATE NAME
State Box:
LOOK, RUN unique name written in elipse by upper left corner
Output value(s) constant for state duration
Only True output values written inside the box
State Transition Decision Box:
0
INPUT
1 true/false exit path decision based on
the condition of the named input(s)
no dynamic conditions (no input change, only static true/false)
State Transition Link:
indicates path to (alternative) next state(s)
no delay or logic function
no state/input/output function

Conditional Output Box

OUTPUT Class−4 Machines Only
will not be considered in this course

14
ELEE08015 Digital System Design 2 Finite State Machine Design
Principal Unit of the ASM Chart — The ASM Block
FSM instantaneously in a single (new) state at
start of clock period for the whole period
Logic outputs named in state box are S NAME
OUTPUT_X
true while state active. That is all other OUTPUT_Y

outputs are false during that state. 0

INPUT_A

Single active link path indicates unique 1

next state at any instant during clock 0

INPUT_B

period. 1
1
INPUT_C
Transition to (new) next state, selected by 0

active link path, instantaneous at end/start

of old/new clock period
0

Transition to same state, staying

within current ASM block, is possible.
Direct transition path to next state (no i/p decisions) possible
15
ELEE08015 Digital System Design 2 Finite State Machine Design
ASM Chart Formal Language Rules
State Box (Square Ends)
STATE NAME Enter state at top of box, Exit state at bottom of box (sides kept clear)
OUTPUT(s)
Inside box: OUTPUT symbol(s), fixed value (must change state to change value) UNIQUE
SYMBOLIC/MNEMONIC State Name outside box, in ellipse at upper left corner State
Transition Sequence Controls Order of Output Change and Input Test Represents Time:
One complete CLOCK period, enter/leave at active clock edge

0
Decision Box (Triangular Ends)
INPUT

1
Enter decision box at top, Exactly two exits: choose from each side and bottom
Inside box: Logic expression of one or more INPUT logic symbols, result True or False
0
INPUT(s)
1 Tests only signal true/false value, no sequence property (no edge test, no pulse test, ...)
Represents no part of a clock period, no time delay (ideal truth−table)
Box order sets only logical precedence of inputs (no time order or sequence of test)

Transition/Link Line
Lines may merge but not split (split with decision box)
Every loop must include one or more state boxes (no loops around decision boxes
alone) Represents no part of a clock period, no time delay

Conditional Output Box (Round Ends) Class−4 Machines Only − not used in this course

Pure logic - no circuits, voltages, propagation delay, setup time, ...

Only logic (codeword/clock period) relationships
16
ELEE08015 Digital System Design 2 Finite State Machine Design
ASM Chart: Some Illustrations of FAULTY Syntax
Formal languages make it difficult, but not impossible, to write nonsense ...

STATE 1

STATE N
STATE N
SIG
STATE 2

no next state specified

EVERY state must have a successor SIG
STATE 3

next state not unique

only ONE state at any time a logic signal name cannot appear as both
an input and an output in the same FSM
this "decision" MUST be true always
INPUT
STATE N no state in transition
path − instantaneously
and forever nowhere

IN
wrong direction
wrong face

17
ELEE08015 Digital System Design 2 Finite State Machine Design
ASM Chart: Illustrations of Unusual Syntax
(Require Special Attention for Synthesis)

S_FINAL S_INITIAL

Terminal (final/initial) states are meaningful, but very much a

special case, especially final states: usually want FSM to keep
on working - to support higher-level machine function.
Only way out (final) or in (initial) for these states is non-data
signal (reset/initialisation) or circuit-level failure, rather than
normal data input (algorithmic) behaviour pattern.

18
ELEE08015 Digital System Design 2 Finite State Machine Design
The Finite State Machine: Design Process
1 Define and encode names for logic signal inputs:
switch, temperature, number value, … these affect internal state

2 Define and encode names for logic signal outputs: lamp, heater,
number value, … these are driven by internal state
3 Design required behaviour (algorithmic structure):
define the number, the names for, and sequence of, internal states
- to create particular output value sequence(s)
- Output names in state boxes
- to match/detect particular input value sequences
- Input names in decision boxes

3 Encode symbolic state names as state-register codewords

only when state/algorithmic structure (behaviour) is complete
4 Synthesis: CAD tools translate behaviour to physical circuit
- via RTL structure (class 2/3 FSM) and gate structure

19
ELEE08015 Digital System Design 2 Finite State Machine Design
VL5.2 FSM Design Using ASM chart
The FSM - Traffic Light Examples
Stage 1: I/O Names and Logic/Bit Mapping

IN/OUT NAMES / LOGIC MAPPING

NANO STREET
RED
INPUTS:
TLS_NS VEHICLE PRESENT => TRUE
TLS_EW VEHICLE PRESENT => TRUE
GREEN

SENSOR
TRAFFIC
OUTPUTS:

GREEN
NS_RED TRUE => LAMP ON

RED
NS_GRN TRUE => LAMP ON
EW_RED TRUE => LAMP ON
EW_GRN TRUE => LAMP ON ELECTRON WAY

Only logical symbols/values used.

High/Low voltage <=> off/on/off is a TRAFFIC
circuit, not logic, design choice. SENSOR

2
ELEE08015 Digital System Design 2 Finite State Machine Design
The FSM - Traffic Light Examples
Stage 1: I/O Codewords and Semantic Mapping (Meaning)

RED RED

GREEN GREEN

STOP PROCEED ? ?
WITH CAUTION (hazardous) (fail−safe)

What meaning and use should certain codewords be given?

• Considerations of application
Accuracy, Reliability, Fault Tolerance, Discrimination,
Resolution, Efficiency, ...

Regulate flow, mitigate collisions, tolerate lamp/cable failure, ...

3
ELEE08015 Digital System Design 2 Finite State Machine Design
The FSM - Traffic Light Example 1 (Class-2, no input)
Stage 2: Behaviour: Output-Codeword Sequence

NANO STREET ELECTRON W AY

NANO STREET
RED RED
RED RED

GREEN GREEN

GREEN

RED
STOP PROCEED
W ITH CAUTION
ELECTRON WAY

RED

GREEN

Notes:
RED RED

Allow moving traffic to stop before

permitting flow on other
carriageway.
RED

Permit flow on only one

GREEN carriageway.

4
ELEE08015 Digital System Design 2 Finite State Machine Design
The FSM - Traffic Light Example 1 (Class-2, no input)
Stage 2: Behaviour: State Sequence

NANO STREET ELECTRON W AY

NANO STREET
RED RED
RED RED ALL_STP_A
NS_RED GREEN GREEN

EW_RED

GREEN

RED
STOP PROCEED
W ITH CAUTION
ELECTRON WAY

RED EW_PWC
NS_RED
GREEN EW_GRN
ASM Chart Notes:
ALL_STP_B States:
RED RED
NS_RED ALL_STP_A,
EW_RED ALL_STP_B: Allow moving traffic to stop before
permitting flow on other carriageway.
NS_PWC EW_PWC,
RED
NS_GRN NS_PWC: Permit flow on only one carriageway.
GREEN
EW_RED

Transition from state to state

regulated by CLOCK signal

5
ELEE08015 Digital System Design 2 Finite State Machine Design
The Finite State Machine: Design Process

1 Define names for inputs and outputs

Input values may direct the next state of the FSM (decision box)
Output values are defined by the current state of the FSM (state box)
2 Define the internal states and state transitions (links between states)
- in simple linear sequences:
direct transition link paths, where input value not significant (or non-existent: class-2)
- in branched sequences:
link paths via decision boxes progressively match alternative histories of input value
- in loops:
to ensure that every state has a next state - the clock never stops
Define output values for states, reflecting recent input history - state
sequence(s) leading to the current state
3 Encode symbolic state names after state structure is complete
- adjust the FSM logical/physical structure to tune technical performance
4 CAD tools automatically translate A SM description of behaviour into
physical circuit implementation

6
ELEE08015 Digital System Design 2 Finite State Machine Design
CURRENT−STATE CURRENT−STATE
CODEWORD
... recapitulation CODEWORD

NEXT−STATE NEXT−STATE STATE OUTPUT MAPPING

NEXT−STATE NEXT−STATE STATE OUTPUT MAPPING
LOGIC CODEWORD REGISTER LOGIC OUTPUT
LOGIC CODEWORD REGISTER LOGIC OUTPUT
COMBINATIONAL SEQUENTIAL COMBINATIONAL INPUT
GATES GATES COMBINATIONAL SEQUENTIAL COMBINATIONAL
GATES GATES GATES
GATES

CLOCK CLOCK

The current state (codeword in state register) a1

TRUTH
input
a0 b1 b0
TABLE
output
y1 y0 z1 z0 a1
TRUTH
input
a0 b1 b0
TABLE
output
y1 y0 z1 z0
OUTPUT COPIES INPUT WITH

determines the current output value, through 0

1
1
1 1 0
0 1 0
1 1 0
0 1 1 1
1 1 0 0
1 0 1 0
POSITIVE INTEGER MULTIPLE
OF CLOCK PERIOD DELAY
0
1
1
1 1 0
0 1 0
1 1 0
0 1 1 1
1 1 0 0
1 0 1 0

the output-mapping logic. The next-state logic

this table is a binary description this table is a binary description
(encoding) of a transistor circuit (encoding) of a transistor circuit

Block structure in True/False/Delay language

calculates the next state value, using the New behaviour due to feedback poorly expressed
NEED HIGHER LEVEL LOGIC BEHAVIOUR LANGUAGE

current state value and any appropriate input.

The Clock initiates transition from current

state to next state, by causing the state register
to memorise the next-state codeword, which thus
becomes the new current state codeword.

Persistence of state memory is clock regulated.

(Salvadore Dali having doubts about his clock signal, 1931).

7
ELEE08015 Digital System Design 2 Finite State Machine Design
The FSM - Traffic Light Examples
Stage 1: I/O Names and Logic/Bit Mapping

IN/OUT NAMES / LOGIC MAPPING

NANO STREET
RED
INPUTS:
TLS_NS VEHICLE PRESENT => TRUE
TLS_EW VEHICLE PRESENT => TRUE
GREEN

SENSOR
TRAFFIC
OUTPUTS:

GREEN
NS_RED TRUE => LAMP ON

RED
NS_GRN TRUE => LAMP ON
EW_RED TRUE => LAMP ON
EW_GRN TRUE => LAMP ON ELECTRON WAY

Only logical symbols/values used.

High/Low voltage <=> off/on/off is a TRAFFIC
circuit, not logic, design choice. SENSOR

8
ELEE08015 Digital System Design 2 Finite State Machine Design
The FSM - Traffic Light Example 1 (Class-2, no input)
Stage 2: State Sequence and Output Definition
NANO STREET ELECTRON WAY

NANO STREET
RED RED
RED RED ALL_STP_A
NS_RED GREEN GREEN

EW_RED

GREEN

RED
STOP PROCEED
WITH CAUTION
ELECTRON WAY

RED EW_PWC
NS_RED
GREEN EW_GRN
ASM Chart Notes:
States:
ALL_STP_B
RED RED
ALL_STP_A,
NS_RED ALL_STP_B: Allow moving traffic to stop before
EW_RED permitting flow on other carriageway.

Two STATES have SAME OUTPUT values

NS_PWC but each has DIFFERENT NEXT−STATE
RED
NS_GRN
EW_RED hence they are DIFFERENT STATES
GREEN

EW_PWC,
NS_PWC: Permit flow on only one carriageway.

9
ELEE08015 Digital System Design 2 Finite State Machine Design
Traffic Light Example 2a (Class-3 FSM)
ASM Chart Notes:
ALL_STP: Allow moving traffic to stop before
ALL_STP permitting flow on other carriageway.
NS_RED
Rapid response when little traffic.
EW_RED
EW_PWC,
NS_PWC: Permit flow on only one carriageway.
0 1
TLS_NS

NANO STREET
RED

0
TLS_EW
GREEN

SENSOR
TRAFFIC

GREEN

RED
1
EW_PWC NS_PWC
NS_RED NS_GRN ELECTRON WAY

EW_GRN EW_RED
TRAFFIC
SENSOR

State (box) activation order controls sequence of input/output activity

ALL_STP duration is +ve integer number of state periods (clock cycles)
conditional state transition maintained while TLS_EW and TLS_NS both false

Duration of states EW_PWC and NS_PWC is single state period

unaffected by inputs (TLS_*), direct state transition from these states

10
ELEE08015 Digital System Design 2 Finite State Machine Design
Traffic Light Example 2a (Class-3 FSM)
ALL_STP
ALL_STP NS_RED
NS_RED EW_RED
EW_RED Identical
Truth Tables 0
TLS_EW
0 1
TLS_NS 1 0
TLS_NS
0
0 1 1
TLS_EW
TLS_NS
1
EW_PWC NS_PWC EW_PWC NS_PWC
NS_RED NS_GRN NS_RED NS_GRN
EW_GRN EW_RED EW_GRN EW_RED

These two ASM charts describe identical behaviour

Input decision box tests are simultaneous (unordered)
Decision box structure defines logic precedence (truth table)
Not sequence of test actions (not "test TLS_NS then test TLS_EW")
Only state boxes give control of sequence of actions

11
ELEE08015 Digital System Design 2 Finite State Machine Design
Traffic Light Example 2a (Class-3 FSM)
ASM Chart Notes:
ALL_STP: Allow moving traffic to stop before
ALL_STP permitting flow on other carriageway.
NS_RED
EW_RED Rapid response when little traffic.
BEWARE − PERSISTENT NS
TRAFFIC BLOCKS EW TRAFFIC.
0 1 EW_PWC,
TLS_NS
NS_PWC: Permit flow on only one carriageway.

NANO STREET
RED
TLS_EW

GREEN
1

SENSOR
TRAFFIC
EW_PWC

GREEN
NS_PWC

RED
NS_RED NS_GRN
EW_GRN EW_RED ELECTRON WAY

TRAFFIC
SENSOR

Even though TLS_EW & TLS_NS tested simultaneously the

decision box logical structure defines a logic precedence (truth table)
such that TLS_NS true gives unfair priority to waiting NS traffic
This is faulty behaviour evident from inspection of the ASM Chart
... let us try a different truth table for making the decision ☞

12
ELEE08015 Digital System Design 2 Finite State Machine Design
Traffic Light Example 2b (Class-3 FSM)
ASM Chart Notes:
ALL_STP: Allow moving traffic to stop before
ALL_STP permitting flow on other carriageway.
NS_RED
EW_RED Rapid response when little traffic.
BEWARE − PERSISTENT EW
TRAFFIC BLOCKS NS TRAFFIC.
0 1 EW_PWC,
TLS_NS
NS_PWC: Permit flow on only one carriageway.

0 1 1 0

NANO STREET
TLS_EW TLS_EW RED

GREEN

SENSOR
TRAFFIC

GREEN
EW_PWC NS_PWC

RED
NS_RED NS_GRN
EW_GRN EW_RED ELECTRON WAY

TRAFFIC
SENSOR

Graphical order of input tests drawn as before, but logic of structure (Truth table)
now gives TLS_EW precedence, so unfair priority now goes to waiting EW
traffic. What does fairness require?
Alternate between two decision structures by remembering previous direction
priority: additional states give memory of previous direction ☞

13
ELEE08015 Digital System Design 2 Finite State Machine Design
Traffic Light Example 2c (Class-3 FSM)
ALL_STP_NS ALL_STP_EW
NS_RED NS_RED
EW_RED EW_RED

0 1 1 0
TLS_NS TLS_EW

EW_PWC2
0 0
NS_RED TLS_NS
TLS_EW
EW_GRN
NS_PWC1
1 1
NS_GRN
EW_PWC1 NS_ PWC2
EW_RED
NS_RED NS_GRN
EW_GRN EW_RED

ASM Chart Notes:

Two states ALL_STP_* give alternate NS/EW ALL_STP_NS, Allow moving traffic to stop before
ALL_STP_EW: permitting flow on other carriageway.
priority — ALL_STP_EW and ALL_STP_NS Rapid response when little traffic.
Alternating states give alternating
each remember the previous priority bias EW_PWC1,
priority when traffic persistent.
EW_PWC2,
Chart notes explain design NS_PWC1,
NS_PWC2: Permit flow on only one carriageway.

This FSM does not count the number of vehicles waiting/moving, so a subtle bias is
still present.

14
ELEE08015 Digital System Design 2 Finite State Machine Design
Traffic Light Example 3 (LINKED FSMs)

FSM_A ALL_STP
NS_RED
EW_PREV
PRI_NS = 1
EW_RED

Road Signals 1 0
0
ACT_NS
PRI_NS
1
1
1
TLS_NS TLS_EW
NS_PREV
0 0 PRI_NS = 0
0 0
TLS_EW TLS_NS
0 1
1 1 ACT_EW

NS_PWC NS_GRN EW_PWC NS_RED

FSM_B
EW_RED
ACT_NS
EW_GRN
ACT_EW
Priority Policy

ASM Chart Notes: FSM_A

ALL_STP: Allow moving traffic to stop before
Distinct tasks, distinct functional units: FSM_A permitting flow on other carriageway.
Idle state, gives rapid
manages road data, FSM_B manages priority. response when little traffic.
Alternating NS/EW priority by FSM_B
Both linked by new signals: PRI_NS, EW_PWC, Permit flow on only one carriageway.
NS_PWC: Indicate flow to FSM_B for future priority.
ACT_NS, ACT_EW created to co-ordinate the FSM_B
NS_PREV, States remember last direction active
(clock synchronised) states of the two FSMs EW_PREV: and give priority to opposite direction,
ensuring equitable flow in each direction.

15
ELEE08015 Digital System Design 2 Finite State Machine Design
Traffic Light Example 3 (LINKED FSMs)
Translation to RTL Structure

FSM_B (Priority Policy)

CURRENT−STATE
CODEWORD

ACT_NS
NEXT−STATE NEXT−STATE STATE OUTPUT MAPPING OUTPUT
LOGIC CODEWORD REGISTER LOGIC

FSM_A (Vehicle Signalling)

INPUT
ACT_EW COMBINATIONAL SEQUENTIAL COMBINATIONAL
GATES ACT_NS
S PRI_NS
ACT_EW
CLOCK CURRENT−STATE
CODEWORD
NS_RED
NEXT−STATE NEXT−STATE STATE OUTPUT MAPPING
LOGIC CODEWORD REGISTER LOGIC NS_GRN
CLOCK OUTPUT
COMBINATIONAL SEQUENTIAL COMBINATIONAL
INPUT
TLS_EW TLS_EW GATES GATES
GATES
EW_RED
TLS_NS TLS_NS
EW_GRN
CLOCK

CLOCK CLOCK

I/O names for new linking signals: PRI_NS, ACT_NS, ACT_EW

Modularity: modify FSM_B (not FSM_A) to change priority policy,
modify FSM_A (not FSM_B) to change signal duration &c.
Clock signal synchronises state-change activity in both machines,
supports co-ordination of active states by linkage signals.

16
ELEE08015 Digital System Design 2 Finite State Machine Design
By using successive stages/layers of abstraction, we have designed a quite complex
system of subsystems
At each stage, only problems relevant to that layer are solved, turning one large
complex task into many smaller simpler essentially independent tasks
Process not perfect, a decision in one layer may cause problems in another, requiring
a previous layer to be revisited, but the approach is generally effective
Using it, we have designed a digital machine (previous two slides) needing about 40
NAND gates (160 transistors) for its construction, without ever needing to know what a
NAND gate or transistor is…
Stage 2 is complete

Next steps: Synthesise low-level logic circuit by:

b) Stage 3: Encoding states (engineering decision)
c) Stage 4: Translating codes into structure of standard gates (automated)
a) FIRST: Study logic gate circuits to understand stage-4 physical elements
then return to study stage-3 and apply heuristic knowledge from stage-4 study

17
ELEE08015 Digital System Design 2 Finite State Machine Design
VL6.1 Design Synthesis I: Fabrics
... review of design layers
FSM Behavioural Structure - ASM Chart Model

Ideal, Pure, Simple, Step-By-Step (Algorithmic) Behaviour

No concern for non-ideal properties: voltage, propagation delay, setup time, ...

2
ELEE08015 Digital System Design 2 Design Synthesis I
... review of design layers
FSM Function Block Structure (Register Transfer Model)

First stage in translation from ideal/abstract to non-ideal/physical

Codewords transformed/stored at each Clock period
State codeword design affects physical properties of each block

3
ELEE08015 Digital System Design 2 Design Synthesis I
... review of design layers
FSM Gate-Level Structure (Logic Switching Netlist Model)

SINGLE-BIT logic functions.

Functions manipulated into alternate shapes through algebraic transformation.
Many alternative solutions possible (e.g. pure 2-i/p NAND above) having different
physical properties, not all feasible: many will fail physical/commercial constraints

4
ELEE08015 Digital System Design 2 Design Synthesis I
... review of design layers
Transistor-Level Structure (Analogue/Physical Model)

Total control of physical performance: area, power, speed, noise immunity.

Large design effort/time cost is required for even simple logic functions.

Complete system design at this level is impractical.

5
ELEE08015 Digital System Design 2 Design Synthesis I
Synthesis of Physical Circuits
The following lectures explore the SYNTHESIS of physical (non-ideal)
realisations of the desired abstract (ideal) behaviour which must meet
physical/commercial constraints

higher symbolic behaviour (Input Adaptive): C (non−synth Verilog) int rf (int a) {

DESIGN (engineer)

non−finite state structure, which is data dependent S_A if (++a) return rf(a);
F_9 return a;
}
symbolic behaviour (non−Adaptive): ASM Chart, Synthesisable Verilog 0
Q_8

finite STATES in fixed structure, highly encoded data S_Z

K_2 1
OUTPUT
SYNTHESIS (machine)

LOGIC
higher abstract logic: Register Transfer Language (RTL)
CODEWORD transforms and storage NEXT−STATE STATE
LOGIC REGISTER
Q

abstract logic: Gate Netlist D

Q CLOCK
CK
single BITS, NAND NOR D−FF (gate features still flexible)

PHYSICAL LOGIC: FABRIC

gate features fixed: fan−in / loading / ... limits ??? ... ASIC ... ??? ... FPGA ... ???

Lower layers give fewer options to radically alter/improve machine structure

Translation of Netlist to Fabric is limited by mapping done at higher layers.

6
ELEE08015 Digital System Design 2 Design Synthesis I
Synthesis of Physical Circuits

With ideal engineering design languages and synthesis tools:

• SYNTHESIS (abstract -> physical) is automated
ONE DESIGN (abstract) -> MANY IMPLEMENTATIONS (physical)
• Symbolic design controls behaviour
• SYNTHESIS controls technical and commercial performance options
Rapid evolution of fabric technology and commercial environment makes re-
synthesis capability increasingly important and puts increasing emphasis on
human design effort at higher levels while automation handles lower levels.
Human expertise and effort at lower levels focussed mainly on tool design:
languages and transformation algorithms for use by engineers designing at
higher levels (closer to the application).

7
ELEE08015 Digital System Design 2 Design Synthesis I
Fabric Examples and Elements

Within a FABRIC we find:

•PHYSICAL LOGIC ("gates") and INTERCONNECT ("wires")
Each can be:
• FIXED ("hard-wired") or FLEXIBLE ("re-configurable" or "programmable")
Different fabrics give different balances of logic/interconnect quantity and
quality, and of hard-wired/programmable flexibility.
Different fabrics give technical performance options (energy, size, speed,
reliability, ...) linked to balance above

Different fabrics give commercial performance options (cost, reliability,

time-to-market, ...) linked to balance above

8
ELEE08015 Digital System Design 2 Design Synthesis I
Fabric Examples and Elements - overview

• Custom Gate Application Specific Integrated Circuit

(ASIC) static configuration of logic (hard-wired)
• Library Cell ASIC
static configuration of logic (hard-wired), rapid design/synthesis process
• Field Programmable Gate Array (FPGA)
episodic (static) RECONFIGURATION from design in memory array
• Computer Processor/Microcontroller
cycle-by-cycle (dynamic) RECONFIGURATION from memory array
• ... others & new/hybrid concepts arise (e.g. dynamic FPGA configuration)

DIFFERENT FABRICS -> DIFFERENT balance of performance options:

energy, size, speed, reliability, cost, time-to-market, ...
Business need: during product life change performance choice e.g:
first-in-market -> fastest-operation -> longest battery life -> cheapest
Ideal solution: RE-SYNTHESIS (cheap) WITHOUT RE-DESIGN (expensive)

9
ELEE08015 Digital System Design 2 Design Synthesis I
Fabric Examples and Elements
Custom Gate ASIC

Can choose or adjust everything:

•substrate, diffusion, implantation, ... (menu fixed by fabrication plant)
•transistor sizes, wire thickness, ... (chosen by designer)
•NAND/NOR gate-level physical structure (chosen by designer)
•block-level physical structure floor-planning (chosen by designer)
•interconnect physical structure floor-planning (chosen by designer)
Total physical chip size, speed, energy trade-off possible
Ultimate technical performance possible at very high commercial cost.
Commercial cost usually spread over very high sales volume.

10
ELEE08015 Digital System Design 2 Design Synthesis I
Fabric Examples and Elements
Library Cell ASIC

Some choices restricted by features of pre-designed library elements

Intensive library element design for performance and re-use

•different library (where available) for silicon fabrication plant choices

•transistor sizes, wire thickness, ... (fixed/chosen by library/automation)
•NAND/NOR gate-level physical structure (designer’s menu fixed by library)
•block-level physical structure floor-planning (automation or designer)
•interconnect physical structure floor-planning (automation or designer)
Partial physical chip size, speed, energy trade-off possible
Good technical performance possible at high commercial cost. Commercial
cost usually covered by moderate sales volume.

11
ELEE08015 Digital System Design 2 Design Synthesis I
Fabric Examples and Elements
FPGA

Type of gates and wiring fixed by physically pre-constructed chip, but

implementation of arbitrary logical functions and architecture still possible
• Physical chip fabrication process already complete
• NAND/NOR gate-level physical structure (fixed by chip)
• programmable block-level logical structure (automation and designer)
• programmable interconnect logical structure (automation)
Rapid synthesis and zero physical fabrication gives short time-to-market
Physical chip size, speed, energy trade-off mostly fixed by choice of chip
Acceptable technical performance possible at moderate commercial cost.
Even fairly small sales volume covers commercial cost.

12
ELEE08015 Digital System Design 2 Design Synthesis I
Fabric Examples and Elements
Computer Processor/Microcontroller

All physical circuit features, physical logic architecture, and certain logical
behaviour features (serialisation) fixed by physically pre-constructed chip.
•chip fabrication process already complete
•logic and interconnect structure complete (fixed by chip)
•programmable logical behaviour, with serialisation restrictions (designer)
Potentially rapid design and short time-to-market
Physical chip size, speed, energy trade-off mostly fixed by choice of chip
Acceptable technical performance possible at moderate to low commercial
cost. Almost any sales volume can be accommodated.

13
ELEE08015 Digital System Design 2 Design Synthesis I
Custom/Library CMOS ASIC

Map 8-Input AND Function to Gates: three options, logically identical,

physically different. Each has (dis)advantages. Design time required for
evaluation of choice at this level of detail gives high technical performance,
but at high commercial cost.
Weste and Eshraghian, "Principles of CMOS VLSI Design",
2nd Ed, 1993, section 5.2, pp 264-273
Shelfmark TK7874 Wes.: Murray 2 copies (+ older editions)

14
ELEE08015 Digital System Design 2 Design Synthesis I
FPGA — Physical Structure

"UPPER LAYER CIRCUITRY" "LOWER LAYER CIRCUITRY"

Physically identical logic cells (thousands) and interconnects, programmed to

implement logically customised behaviour of circuit network.
Separate circuit layer holds logical design (program bits).
Special wiring (interconnect) dedicated to Clock signal to limit SKEW.

15
ELEE08015 Digital System Design 2 Design Synthesis I
Simplified FPGA Architecture: Look-Up Table (LUT) Logic
(‘‘Truth Table In A Box’’)
A
LUT F
B

PROGRAM
BITS (function)
P3 P2 P1 P0

A
SOP
F
TERMS
B

Small-scale logic expression minimisation futile, no optimisation gained.

Every possible function of n-inputs (value of n is fixed by designer of FPGA
cell/chip) can be implemented at the same cost (size, speed).

16
ELEE08015 Digital System Design 2 Design Synthesis I
Simplified FPGA Architecture: Look-Up Table (LUT) Logic

17
ELEE08015 Digital System Design 2 Design Synthesis I
Simplified FPGA Architecture: The Logic Cell

CODEWORD of configuration MEMORY BITS P{j, k, l, m, n} drives the

multiplexer control inputs, so routing the input and output signals
to/from/between the cell’s combinational and sequential gates
This configurable signal routing inside each cell gives each physically identical
logic cell many alternative arrangements of LUT and D-FF
D-FF PRESET/CLEAR programmable to common initialisation signal for state
machine structures

18
ELEE08015 Digital System Design 2 Design Synthesis I
Simplified FPGA Architecture: The Logic Cell

1: Program codeword P = 010** : F = SoP{A,B,C,D,E}, (simple combinational function)

2: Program codeword P = *01** : F = A(t-1), (simple FLIP-FLOP)
3: Program codeword P = 011** : F = SoP{A,B,C,D,E}(t-1), (CLASS-1 FSM structure) 4:
4: Program codeword P = *00** : F = A (more useful than you might first think)
5: Program codeword P = 111** : F = FSM{A,B,C,D} (CLASS-3 FSM structure)

19
ELEE08015 Digital System Design 2 Design Synthesis I
Simplified FPGA Architecture: Programmable Interconnect

SWT
BOX

Interconnect architecture complex; in essence a mesh of "wire" segments

linked by "switches". The switches are programmed as in logic cells.
Certain critical signals, e.g. Clock, have DEDICATED INTERCONNECT

Implementation attempting to pass too many signals to/from/through small

region of chip results in ROUTING CONGESTION or ROUTING
FAILURE
Cannot add more wire as in ASIC, but can use logic cell as wire:
P = *00**: F =A on previous slide,
or change parameters in SYNTHESIS process to implement in different
style (see following FSM examples)

20
ELEE08015 Digital System Design 2 Design Synthesis I
Simplified FPGA Architecture: Programmable Interconnect

Single logic cell more complex than simple NAND or D-FF, but too small for
whole solution to most non-trivial problems
• Most commercial cell designs incorporate only one or two flip-flops and not
usually more than five or six inputs and two outputs
Hence PLACE logic across cells AND ROUTE signals between them to
compose more complex structures

21
ELEE08015 Digital System Design 2 Design Synthesis I
Simplified FPGA Architecture: Programmable Interconnect

FPGA gates and wiring pre-fabricated, but electrically configurable

(programmable).
SIGNAL ROUTING as important as LOGIC PLACEMENT in construction of a
good implementation.
SYNTHESIS process must match LOGIC DENSITY and INTERCONNECT
DENSITY of implementation to physically fixed FPGA resources for efficient
chip utilisation.
The Place-and-Route process, part of synthesis, is extremely costly in
computation. Automated identification of absolute best solution is
impossible (within current estimated lifetime of Universe).
designer knowledge and use of synthesis parameters and effects can have
significant impact on implementation viability and performance.

22
ELEE08015 Digital System Design 2 Design Synthesis I
Synthesis Parameters - ASIC vs FPGA - Simple Summary

FPGA: Combinational functions: LUT FAN-IN limit: below limit, complexity COST-FREE, BUT
if function doesn’t fit in single LUT then at least 3 cells needed + extra interconnect
EXPENSIVE
Flip-flops cheap (1 in every cell) if used, expensive if wasted (not used).
??? replace combinational logic with flip-flops !!! yes, but not directly...
Interconnect cheap up to threshold density, then very expensive: routing congestion -
use cells as wire: F = A (!!!), or leave cells unused (costly)
Field upgrade possible, allowing post-release design improvement/correction (shorter time
to market).
ASIC: Combinational logic may share terms (factorisation): high fan-in functions CHEAP in
area, but slow. cost changes smooth, but finding optimum expensive.
Flip-flops more expensive than combinational functions:
??? replace flip-flops with combinational logic !!! yes, but not directly...
Can trade-off interconnect area cost with logic density, at any scale: interconnect cost
and difficult routing problems less frequent than FPGA.
Errors found post-fabrication very costly: longer time to market, but low cost per unit.

23
ELEE08015 Digital System Design 2 Design Synthesis I
6.2 Design Synthesis I: State Code Design
FSM State Encoding: The State-Code (State Map)

State-Code translates (ASM chart) state structure (describing behaviour) to

Boolean logic structure (gates) via codeword flow structure (RTL)
EACH CODEWORD BIT CORRESPONDS TO ONE STATE-REGISTER FLIP-FLOP

2
ELEE08015 Digital System Design 2 Design Synthesis I
... PREVIEW
State Code Design and The Transition Table
STATE CODE DESIGN STYLE:
choice of style guided by fabric properties and technical/commercial performance targets
Within EACH STYLE, MANY DIFFERENT (unique) CODE DESIGNS possible
EACH UNIQUE design of STATE CODE gives DIFFERENT PHYSICAL structure and
TECHNICAL performance, but IDENTICAL ALGORITHMIC behaviour to others

CODE DENSITY directly affects number of flip-flops, one per codeword bit - indirectly affects
combinational logic complexity (FLIP-FLOP <=> NAND GATE TRADE-OFF, ASIC vs FPGA)

Three state encoding styles will be examined:

• Unit-Distance (high or low density: free choice)
• 1-Hot (always low density)
• Direct State-Output Map (high or low density: related to output function)

THE TRANSITION TABLE:

DERIVED AUTOMATICALLY from Algorithmic Behaviour (ASM Chart) using the State Code
Origin of Boolean functions for Next-State and Output logic implementation

3
ELEE08015 Digital System Design 2 Design Synthesis I
The State-Code - Choice of Style
Consider three styles for generating the state-code (others possible):
• Unit-Distance (UD)
• 1-Hot (1H)
• Direct State-Output Map (DSOM)
CHOICE of style GUIDED BY THE SYNTHESIS PARAMETERS seen earlier
Particular properties of each style/scheme do not predict exact technical
performance outcomes, but bias physical performance in particular directions
MANY DIFFERENT CODES possible, in same or different style, giving
MANY DIFFERENT CIRCUITS, all with
Identical behaviour but different physical properties
• This stage of synthesis gives most opportunity for optimising use of the fabric.
Can generate and evaluate several codes (design time cost), but exhaustive search
for best is impractical. No analytical evaluation process known.
Mixed-Styles and others not studied here are possible

4
ELEE08015 Digital System Design 2 Design Synthesis I
The State-Code - Effect of Density
Density affects number of flip-flops in circuit: one FF per codeword bit

In some state-code styles, density can be made high or low, according to design
choice in code construction details
Dense codes generally lead to combinational logic with high fan-in (many inputs
combined to each output). This may lead to poor FPGA logic cell utilisation, but
may give efficient combinational gate area use in ASIC

Flip-flops tend to be plentiful on FPGA: reducing code density (increasing sparsity)

does not necessarily increase FPGA fabric cost
Sparse (low-density) codes may result in simple combinatorial functions, leading to
low delay (high speed) in both FPGA and ASIC
Sparse codes may give simple interconnect structure, simplifying interconnect (wire)
routing problem (especially important on FPGA)

Dense codes may ease clock energy consumption in circuits with a very high
number of states (fewer flip-flops to be driven by clock signal)

5
ELEE08015 Digital System Design 2 Design Synthesis I
State Code Style: Unit Distance
Key property: sequentially adjacent codewords differ in only one bit.
Recall Gray, Johnson and thermometer codes.
Natural sequence defined by state transition sequence, visible on ASM chart
Single state-register bit change per state transition implies low signal switching
activity, hence potential for low energy.
Synthesis of glitch-free output mapping logic made easier.
Can be designed with high or low density (e.g. Gray vs. thermometer), so can be
optimised for either ASIC or FPGA.
EXACT unit-distance for ALL transitions is not always (easily) possible, and may
not be essential - e.g. for power consumption benefit.
If exact unit-distance is required, it may be achieved by duplicating certain states
(two states, different state codes, same behaviour), or by adjustments to
behavioural description (addition of extra "link" states).
A KARNAUGH MAP, or similar tool which displays codewords in unit-distance
adjacency, assists construction of such codes.

6
ELEE08015 Digital System Design 2 Design Synthesis I
Unit-Distance Style: Example
01 00 10
EAGER GRUMPY DOZY S1 S 0
LOOK, RUN LOOK LOOK STATE STAT E
NAME CODEW RD
0 1 0 S1 S0
COLD && WET COLD 11
ASLEEP
1 EAGER 0 1
1 0 GRUMPY 0 0
COLD

1 DOZY 1 0
WET

0 ASLEEP 1 1
S
S
0 0 1
1

EAGER adjacent to: GRUMPY ASLEEP 0 GRUMPY EAGER

GRUMPY adjacent to: EAGER DOZY
DOZY adjacent to: ASLEEP GRUMPY 1 DOZY ASLEEP
ASLEEP adjacent to: EAGER GRUMPY DOZY

One distance-2 state transition: asleep -> grumpy.

• Odd-number state rings:
— accept imperfection
— duplicate state(s)
— add link state(s)

7
ELEE08015 Digital System Design 2 Design Synthesis I
Unit-Distance Style: Example

(unfinished) illustration of state duplication used to achieve unit-distance coding style

8
ELEE08015 Digital System Design 2 Design Synthesis I
State Code Style: 1-Hot
Key property: one bit per state, each codeword has one bit true ("hot") and all
others false.

A sparse (low-density) code. See previous notes on code density.

As with all codes where some available codewords are not assigned to states in the
FSM, the consequences of an invalid codeword appearing in the state register must
be addressed (see later).

The 1-hot code structure makes the identification of an invalid codeword

straightforward (see exercise question), so may be a good choice for high reliability
applications.

PARTIAL DECODING of the state register: e.g. treating 000100 as *1,

greatly simplifies the combinational functions for next-state logic and output-
mapping logic.

9
ELEE08015 Digital System Design 2 Design Synthesis I
1-Hot Style: Example
0001 0010 0100 S3 S2 S1S0
EAGER GRUMPY DOZY
LOOK, RUN LOOK LOOK STATE STATE
NAME CODEWORD
0 1 0
1000
S3 S2 S1 S 0
COLD && WET COLD
ASLEEP
1 EAGER 0 0 0 1
1 0 GRUMPY 0 0 1 0
COLD

1 DOZY 0 1 0 0
WET

0 ASLEEP 1 0 0 0

Sparse code: Many potential codewords not used to represent valid FSM states.

Explicit circuit-level initialisation essential

(for ANY code with unused codewords)
unless logic-level structure can be assured self-starting.

10
ELEE08015 Digital System Design 2 Design Synthesis I
State Code Style: Direct State-Output Map
Key property: OUTPUT CODEWORD is a FIELD within STATE CODEWORD,
so no additional logic is required for generation of the output signals.
Starting point for creating code is list of output codewords for each state. If all the
output codewords are unique, then these may be used as the state codewords,
without modification. Otherwise, extra bits must be added to each state codeword,
and given different values for the states where the output codewords are identical.
All outputs taken directly from (clocked) flip-flops, so Direct State-Output Mapping
can be particularly useful where output signal delay or output signal skew (synthesis
performance parameter) must be tightly controlled
Depending on the application, it may be sufficient to direct-map just a subset of
the output signals.
Direct State-Output mapping may arise naturally in conjunction with other code
styles, according to the state-codeword/output-codeword relationships and specific
code design.

11
ELEE08015 Digital System Design 2 Design Synthesis I
Direct State-Output Map Style: Example
*11 010 110
EAGER GRUMPY DOZY S2 S1S0
LOOK, RUN LOOK LOOK

0 1 0
COLD && WET COLD *00
ASLEEP
1

1 0
COLD

1
WET

0
RUN direct mapped to S 0
LOOK direct mapped to S 1

State codeword bit S2 is added (making the code sparse) to distinguish states GRUMPY
and DOZY, which do not differ in S0 and S1 due to the direct mapping of those bits to
RUN and LOOK (o/p same in both states)
The use of DON’T CARE for S2 in EAGER and ASLEEP indicates a FREE CHOICE of
1/0 to a later stage of synthesis (increasing potential for optimisation).
It DOES NOT indicate multiple state codewords per state

12
ELEE08015 Digital System Design 2 Design Synthesis I
State Code Style: Summary of Examples
STATE UNIT DISTANCE STATE 1−HOT STATE STATE−OUTP T
NAME CODEWORD NAME CODEWORD NAME CODEWOR D
S1 S0 S S2 S1 S S2 S1 S0
0

EAGER 0 1 EAGER 0 0 0 1 EAGER 1 1

*
GRUMPY 0 0 GRUMPY 0 0 1 0 GRUMPY 0 1 0

DOZY 1 0 DOZY 0 1 0 0 DOZY 1 1 0

ASLEEP 1 1 ASLEEP 1 0 0 0 ASLEEP * 0 0

EAGER GRUMPY DOZY

LOOK, RUN LOOK LOOK

0 1 0
THREE codes, derived from COLD && WET COLD
ASLEEP

ONE behaviour (ASM Chart), 1

COLD
0

imply: 1
WET

Three DIFFERENT circuits: 0

Each circuit different in physical size, speed, and energy PERFORMANCE

Many other specific codes possible in these, and other, styles.

13
ELEE08015 Digital System Design 2 Design Synthesis I
Design Flow: Linking Design Views and Processes
BEHAVIOURAL LOGICAL
REQUIREMENTS STRUCTURE

SYNTHESIS PHYSICAL FABRIC

BEHAVIOURAL
PARAMETERS STRUCTURE
STRUCTURE

STATE−CODE
MAP

TRANSITION TRUTH TABLES LOGIC FUNCTION PHYSICAL GATE PHYSICAL GATE PHYSICAL
TABLE N/S + O/P LOGIC OPTIMISATION STRUCTURE PLACE AND ROUTE FABRICATION

STATE INPUT NEXT STATE OUTPUT

S 1 S 0
A B S+S+1 0
YZ

STATE ENCODING 0 0 0 0 0 1 0 1
0 0 0 1 0 1 0 1
STATE STATE 0 0 1 0 0 0 0 1
NAME CODEWORD
0 0 1 1 0 0 0 1
WILMA 01010011100

+ =>
0 1 0 0 1 0 0 1
FRED 10110011101 0 1 0 1 1 0 0 1
PEBBLE 00010010101 0 1 1 0 1 0 0 1
0 1 1 1 1 0 0 1
BETTY 00110111101 1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 0
BARNEY 10101101101
1 0 1 0 1 1 0 0
DINO 10100000001 1 0 1 1 0 0 0 0

Fourth stage: Construct TRANSITION TABLE from the ASM Chart link paths
and the State Code Table
This is a completely automated process - no design input required

14
ELEE08015 Digital System Design 2 Design Synthesis I
Transition Table Fields
STATE INPUT NEXT STATE OUTPUT CURRENT−STATE
+ + Y Z
CODEWORD
S1 S 0 A B S1 S0

0 0 0 0 0 1 0 1 NEXT−STATE STATE
NEXT−STATE OUTPUT MAPPING
0 0 0 1 0 1 0 1 LOGIC CODEWORD REGISTER LOGIC OUTPUT
0 0 1 0 0 0 0 1 INPUT
COMBINATIONAL MEMORY COMBINATIONAL
0 0 1 1 0 0 0 1 GATES GATES GATES
0 1 0 0 1 0 0 1
0 1 0 1 1 0 0 1
0 1 1 0 1 0 0 1 CLOCK
0 1 1 1 1 0 0 1
1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 1 1 0 0
1 0 1 1 0 0 0 0
1 1 0 0 1 1 1 1
1 1 0 1 1 1 1 1
1 1 1 0 1 1 1 1
1 1 1 1 0 0 1 1

The four fields of the transition table reflect

the codeword flow (RTL) structure
The individual next-state codeword bits are calculated in the next-state logic,
from the input (class 3 and 4) and state codewords (all classes).
The output codeword bits are calculated in the output-mapping logic, from
the input (class 4) and state codewords (all classes).

15
ELEE08015 Digital System Design 2 Design Synthesis I
The Transition Table
STATE INPUT NEXT STATE OUTPUT
STATE STATE
EAGER GRUMPY DOZY NAME CODE COLD WET + + RUN LOOK
LOOK, RUN LOOK LOOK S 1 S 0
S1 S 0
S 1 S
0
0 1 0
0 0 0 0 0 1 0 1
COLD && WET COLD 0 0 0 1 0 1 0 1
ASLEEP EAGER 1 1
0 0 1 0 0 0 0 1
1 0 0 1 1 0 1
0 0
GRUMPY 0 0
1 0 0 1 0 0 1 0 0 1
COLD 0 1 0 1 1 0 0 1
DOZY 0 1
0 1 1 0 1 0 0 1
1
WET ASLEEP 1 0 0 1 1 1 1 0 0 1
1 0 0 0 1 0 0 0
0 1 0 0 1 1 0 0 0
1 0 1 0 1 1 0 0
STATE−CODE MAP
ASM CHART (BEHAVIOURAL STRUCTURE) 1 0 1 1 0 0 0 0
1 1 0 0 1 1 1 1
1 1 0 1 1 1 1 1
INPUT, STATE, NEXT−STATE and OUTPUT codewords 1
1
1
1
1
1
0
1
1
0
1
0
1
1
1
1
combine to describe the
TRANSITION TABLE (LOGIC STRUCTURE)
FSM STRUCTURE in BOOLEAN LOGIC

For each link path in the ASM Chart, one row is entered into the
transition table. Each row has two principal fields:
• Input data: concatenated STATE and INPUT codewords
— Class-2: there is no input codeword.
• Output data: concatenated NEXT-STATE and OUTPUT codewords
— Class-3: output codeword not dependent on input codeword (only
state)

16
ELEE08015 Digital System Design 2 Design Synthesis I
The Transition Table
STATE STATE STATE INPUT NEXT STATE OUTPUT
EAGER GRUMPY DOZY + + RUN LOOK
NAME CODE S S COLD WET S S
LOOK, RUN LOOK LOOK 1 0 1 0
S S
1 0 0 0 0 * 0 1 0 1
0 1 0
COLD && WET COLD
ASLEEP EAGER 1 1
0 0 1 * 0 0 0 1

1
0 1 * * 1 0 0 1
GRUMPY 0 0 1 0 0 * 1 0 0 0
1 0 1 0 1 0 1 1 0 0
COLD
DOZY 0 1 1 0 1 1 0 0 0 0
1
WET ASLEEP 1 0 1 1 0 * 1 1 1 1
1 1 1 0 1 1 1 1
0
1 1 1 1 0 0 1 1
STATE−CODE MAP
BEHAVIOURAL STRUCTURE TRANSITION TABLE

Where ASM decision trees (diamond clusters) have few alternate outcomes,
using don’t-care symbol (*) makes the transition table more compact.
Essentially different from a truth table: during any given clock period, only
the row(s) corresponding to the (single) current state are relevant.
During any given clock period, in a current-state row, the next-state codeword
shows which row(s) of the table will describe external input/output relation
during the following clock period.

17
ELEE08015 Digital System Design 2 Design Synthesis I
7.1 Design Synthesis II:
Timing consideration and initialisation
Digital System Technical Performance
SIMPLIFIED three-way categorisation of technical performance:
• POWER
— or a more appropriate "energy per unit result" measure
• AREA
— ASIC: literal die size in square millimetres
— FPGA: cell utilisation (% chip active) or number of chips
• SPEED
— THROUGHPUT: result per second (recall class-1 FSM)
LATENCY: total delay in production of single result unit
—
NOT SIMPLE to control these parameters independently
OFTEN a trade-off (balance) or one critical (dominant)
Commercial targets may also have indirect influence
ALL THREE (and others) ARE IMPORTANT performance
measures, but we shall just focus on speed (which is sometimes what
people mean when they just say "performance")

2
ELEE08015 Digital System Design 2 Design Synthesis II
Speed: Propagation Delay Prediction/Calculation
Synthesis uses MODELS to predict signal delay through network of logic gates.
Different complexity of models available — accuracy vs. computational effort
• FABRICATION PROCESS MEASUREMENTS and MODELLING:
Used to model individual transistors and generate parameters for simpler models
- measure test structures and calculate complex integrals over device geometry: extract
parameters: gm Rds Cgg Cdd &c., under various operating conditions, to use in
simpler models. Suitable only for individual transistors or very simple gate structures
• TRANSISTOR-LEVEL MODELLING (e.g. SPICE)
Used to model individual gates or critical simple gate networks
- Uses gm/Rds/Cgg/Cdd/... derived above for analogue circuit model of interconnect and
gate. Computationally expensive for even a few gates. Usually used for worst-case
modelling of whole gates and calculation of parameters for simpler models: tR tF tPD Ci

• SWITCH-LEVEL SIMULATION
Used for most interconnect and gate network modelling
- Take tPD value (above) defined at standard load, apply simple linear adjustment for
interconnect and gate-input (fan-out) LOAD CAPACITANCE
Computationally simple enough for effective (re-)SIMULATION DURING SYNTHESIS,
but may (should!) be pessimistic - WORST-CASE MODELLING.

3
ELEE08015 Digital System Design 2 Design Synthesis II
Propagation Delay Model for CMOS Logic Gates
+Vdd +Vdd

R_pmos
R

R_nmos
50%
C_gg C_dd C

−Vss −Vss t = 0.7 R C

−Vss −Vss −Vss −Vss PD

transistor circuit switch+parasitic equivalent simplified model model step response

R_nmos, R_pmos: resistance of conducting MOS transistor drain-source channel

C_dd: capacitance of MOS transistor channel (physical size)
C_gg: capacitance of MOS transistor-gate (gate/insulator/conducting channel)
Resulting model is RC network driven by ideal switches to +/- supply rails RC
model +ve step response V = Vdd(1 - exp(-t/RC)) [C = C_dd + (N x C_gg)]

0.5 = exp(-tPD/RC) solve for time to reach 50% Vdd: tPD

GATE PROPAGATION DELAY INCREASES WITH FAN-OUT (number of other
gate inputs, or other capacitive load, connected to the output)

4
ELEE08015 Digital System Design 2 Design Synthesis II
Propagation Delay Models for Interconnect (‘‘wire’’)
• On-Chip SHORT INTERCONNECT:
Essentially zero resistance, but significant CAPACITANCE
Add extra capacitance to output of logic gate model: tPD of gate increases
• On-Chip LONG INTERCONNECT:
Significant RESISTANCE (+routing switches in FPGA) with CAPACITANCE
Use Resistance-Capacitance model for separate interconnect tPD parameter:
Rwire

50%
Cwire

−Vss −Vss −Vss t = 0.7 R C

circuit (!) simplified model model step response

• Off-Chip (... and some on-chip) LONG INTERCONNECT:

Significant INDUCTANCE as well as RESISTANCE and CAPACITANCE: Use
complex RLC or electromagnetic model: predicts interconnect tPD value and
ALSO edge distortion/reflexion effects: very significant for CLOCK signal
• CLOCK: simple signal, complex distribution problem: separate interconnect

5
ELEE08015 Digital System Design 2 Design Synthesis II
System-Critical Interconnect Delay
CLOCK SKEW
Clock Skew: DIFFERENCE IN ARRIVAL TIME OF SAME CLOCK EDGE AT INDIVIDUAL FLIP-FLOPS

Absolute delay value from clock source to any flip-flop not usually a significant
concern, but clock skew can be a major concern in medium and large systems

A B
FF5 FF1
DQ DQ DQ

CK CK CK DQ

t5 t1 t3 CK

DQ t4
CLOCK t0 CK

MAXIMUM DIFFERENCE in clock interconnect delay (clock skew tcs) in figure above
is t5 -t1. CLOCK EDGES arrive tcs later at FF5 than at FF1.
A)Q-FF5 data signal has tcs less time to reach D-FF1 before next clock edge:
this situation makes clock skew equivalent to extra data propagation delay
B)Q-FF1 data signal to D-FF5: FF5 MAY NEVER capture input correctly...
Q-FF1 data change starts before completion of D-FF5 hold-time

6
ELEE08015 Digital System Design 2 Design Synthesis II
... recapitulation
Combinational Gate Propagation Delay: Data I/P to Data O/P

VIH
50%

VIL VI VO
time
VOH
50%
tPD or td
VOL
time
tPD tPD

CMOS Propagation Delay Strongly Affected by Capacitance on Output

A CMOS gate input, or interconnect, looks like a capacitor

Hence, Increased Fan-Out Increases Propagation Delay

7
ELEE08015 Digital System Design 2 Design Synthesis II
... recapitulation
Flip-Flop Propagation Delay: CLOCK Change to Data O/P Change
DANGER ZONE
input data input data (D) input data
may change transitions forbidden may change

D Q
tsu Ck tPD
t su th
th
t PD

time zero reference

All Time Values Referred To/From CLOCK Signal Active Edge

Data Input Value MUST NOT Change in Set-Up <-> Hold Zone
th (or tsu) Can Have Negative Value, but NOT tPD

8
ELEE08015 Digital System Design 2 Design Synthesis II
Synthesising FSM Circuitry — Timing Constraints
SYNCHRONOUS DESIGN: every data signal starts from a flip-flop, passes through
combinational logic and/or interconnect, arrives at a flip-flop.
The flip-flops ensure that TIME (re-)STARTS AT each active CLOCK EDGE:

(1) this edge may be slightly late, due to clock skew at the source flip-flop
(2) the data signal must propagate to the source flip-flop output, then:
(3) propagate through interconnect to a combinational gate input, then:
(4) propagate through the combinational gate, then:
... (2) and (3) may happen any number of times, from zero upward
(4) propagate through interconnect to a flip-flop input, then:
(5) remain steady for no less than the flop-flop setup time, before:
(6) the NEXT clock edge arrives at the destination flip-flop, which:
(7) may happen slightly early (skew again).

9
ELEE08015 Digital System Design 2 Design Synthesis II
Timing Constraints — Calculation and Application
MINIMUM CLOCK SIGNAL PERIOD governed by the WORST-CASE possible
combination of time values for getting any data signal from a flip-flop o/p to the
next flip-flop i/p
Time parameter values obtained by measurements and/or modelling.
Increased accuracy of calculation brings greatly increased computational
complexity — time/effort required to get result.
Use gross approximations to estimate timing properties at very abstract
(high-level) design description layers
General use of moderate accuracy models/calculations in early stage(s) of
synthesis process — to RTL or gate-layer.
Selective use of high-accuracy at lowest layer(s) IF/WHEN most time-critical
sub-section of design is identified AND can not readily meet target by
ALTERNATIVE SYNTHESIS approach.
ALWAYS making calculated result WORST-CASE (pessimistic)

10
ELEE08015 Digital System Design 2 Design Synthesis II
Class-2 FSM Clock Period
Budget

Critical path (generate next-state codeword) total PROPAGATION delay:

tPD-t = tPD-sr + tPD-is + tPD-ns
Next-state codeword MUST be ready tsu BEFORE end of clock cycle:
t > t
ck +t PD-t su

State register clock skew equivalent to codeword delay (assume worst-case)

tck ≥ tPD-t + tsu + tcs
Therefore MINIMUM clock PERIOD (invert for maximum clock frequency):
tck = tPD-sr + tPD-is + tPD-ns + tsu + tcs

11
ELEE08015 Digital System Design 2 Design Synthesis II
Class-3 FSM Clock Period Budget
t
STATE−LOGIC INTERCONNECT: TOTAL PROPAGATION DELAY: PD−is

O/P MAPPING LOGIC NEXT−STATE LOGIC STATE REGISTER 2

STATE REGISTER 1
W ORST−CASE TOTAL t
GATE DELAY PD−nsi
t t t t
PD−sr t PD−ie t su PD−sr
PD−om1 PD−nse
FSM to FSM INTERCONNECT
EXTERNAL DELAY PATH
INTERNAL DELAY PATH
CLOCK SKEW t CLOCK PERIOD t
cs ck

tPD-t2 = tPD-sr + tPD-is + tPD-nsi (internal next-state path, as for class-2)

tPD-t1 = tPD-sr + tPD-om1 + tPD-ie + tPD-nse (external FSM-FSM path, includes OML)
The following must hold for all paths including longest delay path:
tck - tcs - tsu > tPD-ti (where i is the index of the path and clock skew across ALL FF)
Therefore MINIMUM clock PERIOD:
tck = MAX { tPD-t1+ tsu1 , tPD-t2 + tsu2 } + tcs
Note that setup times can be different for different FFs as well. The minimum
clock period can be then inverted to calculate the maximum frequency.
Balance of delay between n-s (next-state) logic and o-m (output m apping)
logic may affect overall maximum speed of system (see synthesis choices).
12
ELEE08015 Digital System Design 2 Design Synthesis II
FSM Clock Period Budget - Hold Time

Flip-Flop data input must remain stable for minimum period th AFTER active
clock edge, as well as being stable for set-up period before edge, so new
codeword must arrive neither too late, nor too early.
Not usually troublesome, unless total propagation delay very small (shift-
registers) or clock skew large.
tPD-t - tcs > th N.B: NO RELATION to clock period (tck)
CANNOT FIX hold-time problem by changing clock period
must REDUCE clock skew or ADD EXTRA DELAY to problem data signal:
Note that here MINIMUM tPD value is the worst-case for hold time
calculations.

13
ELEE08015 Digital System Design 2 Design Synthesis II
Gate-Level Synthesis: Logic Function Optimisation
• Boolean algebraic transforms, term minimisation (K-map), and methods
not covered in this course may be applied to the Truth Tables, either
individually or jointly (common-term sharing), to meet performance
targets
• The presence of any "don’t care" conditions in the Truth Tables may be
exploited at this stage. This includes "partial decoding" of the state
codewords produced by sparse state-encoding styles, whereby the
evaluation of just one or a few key bits of the codeword is sufficient to
identify the state, implicitly making other bits "don’t care"
• For some fabrics and/or applications, specific optimisations may be weak
or useless, but would increase design time (commercial cost)
• For some fabrics certain transformations would be undone by later,
fabric structure specific processing, making futile the use of those
transforms
• As so often in digital system design, the engineer’s role is not to carry out the
brute effort of processing, but to apply both specific knowledge and heuristic
insight, to select or reject processing options available from the CAD tool
chest, guiding the force applied by the tools to give best effect

14
ELEE08015 Digital System Design 2 Design Synthesis II
Gate-Level Synthesis: Map Logic to Physical Gate Structure

We have seen how in an ASIC the 8-input AND function may usefully be re-
mapped into a NAND/NOR cascade of lower fan-in gates.

For an FPGA logic cell employing LUT combinational logic, the fan-in limit is
critical and the Boolean function complexity otherwise irrelevant.

By this stage, the balance of combinational logic to flip-flops has been almost
entirely fixed by the state encoding.

Product development time limits and human frailty increasingly require that
those who have acquired such skill and knowledge produce not end-product,
but CAD tools for other engineers to use, with caution and higher-level insight
into a solution’s structure.

15
ELEE08015 Digital System Design 2 Design Synthesis II
Gate-Level Synthesis: Physical Gate Place and Route
or
Why Is Routing Expensive ?

The problem of finding a good logical structure for a Boolean function may be challenging,
but it is trivial in comparison to the difficulty of working out how to wire together a network of
such functions, at the level of complexity quite common in current applications.

The archetype of this problem is the "travelling salesman" problem, which has been studied
for decades, perhaps centuries, and continues to sap the will to live of talented people.

Lacking much in the way of analytic or systematic methods for this task, logic circuit
designers typically fall back on the systematically-minded digital systems engineers: going
with random chance.

16
ELEE08015 Digital System Design 2 Design Synthesis II
Gate-Level Synthesis: Physical Gate Place and Route
or
Why Is Routing Expensive ?
• Designers (or their synthesis tools) scatter the logic in an arbitrary pattern across the
fabric, then try to connect it all together with wires sent off in initially random directions.
Often there will be heuristic guidance too, based on such measures as the distance to be
covered by a wire, or the total number of gate inputs driven by it.

• The measures used are typically easy to calculate, but may have only indirect relevance
to the desired objective.

• Most of these random attempts lead to dead-ends, at which point a small (...or large)
region of the interconnect and/or logic is ripped up and placed in a different (arbitrary)
arrangement and more random routing attempts are made.

• Each place-and-route episode which actually manages to interconnect all the logic within
some time limit is measured for goodness of result and stored for comparison to other
candidate solutions.

• This process continues until a solution which can be passed off as acceptable turns up, or
the engineer finds a new job, or the world as we know it comes to an end.

17
ELEE08015 Digital System Design 2 Design Synthesis II
Why Is FIRST State/Codeword Important?
Most behaviour in form of inter-linked LOOPS: no special start/end
• Can get TO any state FROM any state.

BUT WHAT IF
circuitry can represent state(s) not shown in description of behaviour?
• CODEWORDS represent STATES:
• BINARY codewords come in sets of 2n
• Even dense codes likely to have a few unused codewords
— if unused codeword appears in state register, what happens next?

18
ELEE08015 Digital System Design 2 Design Synthesis II
Why Is FIRST State/Codeword Important?
Modular design: Linked FSM:

SYSTEM behaviour requires different machines to be in corresponding states

• State correspondence maintained by exchange of signals
BUT how is correspondence established in the first place?
• could START EACH FSM with specific codeword in state register, but
STATE REGISTER INITIAL CODEWORD IS FUNCTION OF FABRIC/ENVIRONMENT
• layered system design approach specifically intended to
isolate high-level (state) design from low-level (fabric) factors

19
ELEE08015 Digital System Design 2 Design Synthesis II
Why Is FIRST State/Codeword Important?
Non-Loop Behaviour:

Some applications may require non-repeating activity to be performed

before normal repetitive behaviour is begun
• Because that is what the application requires (specification)
• Because the FSM must check/modify its environment before it can
operate correctly (implementation)

20
ELEE08015 Digital System Design 2 Design Synthesis II
FSM Initialisation
When May Initialisation Be Required?
• Shortly After Power is First Applied
• After Power is Lost and Then Restored - Sometimes
• When An Error in Behaviour/Operation is Found - Sometimes
• Sometimes to End a Phase of Active Operation

Different Degrees of Initialisation May Be Required

• Total Loss of State (Information) May Be Undesirable (Fault Identification)
• Total Loss of State (Information) May Be Desired (Security)

None of the above situations is part of the normal (algorithmic) sequence of

state changes, so can not be described using the sequential (synchronous)
elements of high-level description languages
ASM Chart language can only describe pure sequence
More complex behavioural languages may capture asynchronous events,
such as initialisation, and pass them down through synthesis along with the
pure sequence behaviour

21
ELEE08015 Digital System Design 2 Design Synthesis II
FSM Initialisation
Natural Initial Logical Condition of Flip-Flops (State Register) Unpredictable, SO:
1 Provide Special Circuitry (Fabric) to Identify Need and Generate
Initialisation Codeword for State Register (preset/clear/reset)
— This requires co-ordination between behaviour/synthesis and
design/use of initialisation fabric
— For example: Flip-Flop Circuit RESET (Clear/Preset) Signal can
control the initial state of the State Register (Fabric) to Match
State Code Assignment of the desired initial State (Behaviour)

2 Ensure FSM Behaves Correctly WHICHEVER Random State Codeword

Appears Initially in the State Register (self-starting)
— Requires no co-ordination between behaviour/synthesis and fabric, but
places extra constraints on behaviour - not always possible
— They can be done by extending the design of ASM chart to also include all
the unused states such that, for example, a random start in any unused state
goes directly to the desired initial state in the next clock cycle.

22
ELEE08015 Digital System Design 2 Design Synthesis II

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