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Assignment - 2 and CIE2 Portion Advanced VLSI - 24 - 25

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82 views

Assignment - 2 and CIE2 Portion Advanced VLSI - 24 - 25

Uploaded by

ranju18102002
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Jain College of Engineering, Belagavi

Department of Electronics and Communication Engineering

Assignment - II
Semester: VII(A, B, and C) Date: 11/11/2024
Subject: Advanced VLSI Sub code: 21EC71
Q. Questions Course PO Bloom’s
No. Outcome Cognitive
Level
1 Explain about the following: Goals and objectives of 1.Floor CO2 & 1 L2
planning 2. Placement and 3. Routing CO3

2 Explain the global routing methods in an ASIC physical design CO2 & 1 L2
CO3
3 Explain global routing between blocks with neat diagram CO2 & 1 L2
CO3
4 Explain the approaches of minimizing delay in circuit placement CO2 & 1 L2
CO3
5 Explain the following placement algorithms: 1. Constructive CO2 & 1 L2
placement 2. Iterative placement improvement CO3

6 Explain the following in ASIC floor plan 1. Clock planning 2. CO2 & 1 L2
Power planning CO3

7 Explain the concept of measurement of delay in floor planning CO2 & 1 L2


CO3
8 Explain the goals and objectives of each steps in ASIC physical CO2 & 1 L2
design CO3

9 With neat diagram, explain min-cut placement algorithm CO2 & 1 L2


CO3
10 Explain the verification process of system verilog CO5 1 L2

11 Explain the different phases of simulation CO5 1 L2


12 Explain the different types of array methods used in unpacked CO5 1 L2
arrays
13 Discuss the guidelines associated to choose a storage type CO5 1 L2
14 Explain the factors in randomizing the stimulus to design CO5 1 L2

15 Describe the various array methods with examples CO5 1 L2

16 Write a short note on various user defined data types with examples CO5 1 L2

17 Explain the constants and strings in system verilog with examples CO5 1 L2
Jain College of Engineering, Belagavi
Department of Electronics and Communication Engineering

*C0: Course Outcomes


CO2: Describe the concepts of ASIC design methodology
CO3: Create floor plan including partition and routing with the use of CAD algorithms
CO5: Learn verification basics and System Verilog
PO: Program Outcomes
PO1: Engineering Knowledge

Prepared By CIE moderation commitee Approved By HOD


Signature: Signature: Signature:
Name: SBH/NRA Name: Dr. HPR/RSP Name:Prof. V.R.Bagali
Jain College of Engineering, Belagavi
Department of Electronics and Communication Engineering

PORTION FOR CIE 2

Module 2:
Floor planning and placement: Goals and objectives, Measurement of delay in Floor planning,
Floor planning tools, Channel definition, I/O and Power planning and Clock planning. Placement:
Goals and Objectives, Min-cut Placement algorithm, Iterative Placement Improvement, Time
driven placement methods, Physical Design Flow.
Routing: Global Routing: Goals and objectives, Global Routing Methods, Global routing between
blocks, Back annotation.

Module 3:
Verification Guidelines: The verification process, basic test bench functionality, directed testing,
methodology basics, constrained random stimulus, randomization, functional coverage, test bench
components, layered testbench.
Data Types: Built in Data types, fixed and dynamic arrays, Queues, associative arrays, linked lists,
array methods, choosing a type, creating new types with type def, creating user defined structures,
type conversion, Enumerated types, constants and strings, Expression width.

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