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21EC71 - Module 1 5

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25 views

21EC71 - Module 1 5

Uploaded by

dhanushvgowda2803
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Multipliers

9/4/20XX Presentation Title 57


Wallace tree Multiplier

• collapse the chain of adders a0-


f5 (5 adder delays) to the
Wallace tree consisting of
adders 5.1-5.4
• At each stage we have the
following three choices:
• (1) sum three outputs using a full
'adder (denoted by a box
enclosing three dots),
• (2) sum two outputs using a half
adder (a box with two dots)
• (3) pass the outputs directly to
the next stage.

9/4/20XX Presentation Title 58


• The object is to choose (1), (2), or (3) at each stage to
maximize the performance of the multiplier.
• In tree-based multipliers there are two ways to do this-
working forward and working backward.
• In a Wallace-tree multiplier we work forward from the
multiplier inputs, compressing the number of signals to be
added at each stage.

9/4/20XX Presentation Title 59


9/4/20XX Presentation Title 60
Dadda multiplier

• In a Dadda
multiplier we
work
backward
from the
final
product.

9/4/20XX Presentation Title 61


Ferrari–Stefanelli Multipliers

• Nests multipliers-
the 2-bit
submultipliers
reduce the number
of partial products

9/4/20XX Presentation Title 62


Deciding between parallel multiplier
architectures

• Wallace-tree multiplier is more suited to full-custom layout.


but is slightly larger than a Dadda multiplier-both are less
regular than an array multiplier. For cell-based ASICs, a
Dadda multiplier is smaller than a Wallace-tree multiplier.
• The overall multiplier speed does depend on the size and
architecture of the final CPA, but this may be optimized
independently of the CSA array. This means a Dadda
multiplier is always at least as fast as the Wallace-tree
version.
9/4/20XX Presentation Title 63
Deciding between parallel multiplier
architectures

• The low-order bits of any parallel multiplier settle first and


can be added in the CPA before the remaining bits settle.
This allows multiplication and the final addition to be
overlapped in time.
• Any of the parallel multiplier architectures may be
pipelined. We may also use a variably pipelined approach
that tailors the register locations to the size of the multiplier.

9/4/20XX Presentation Title 64


Deciding between parallel multiplier
architectures

• Using appropriate counters increases the stage


compression and permits the size of the stages to be
tuned. There is a trade-off in using these counters between
the speed and size of the logic cells and the delay as well
as area of the interconnect.
• Power dissipation is reduced by the tree -based structures,
The simplified carry-save logic produces fewer signal
transitions and the tree structures produce fewer glitches
than a chain.
9/4/20XX Presentation Title 65
I/O Cells

• A three-stage bidirectional output buffer.


• When the output enable, OE, is ‘1’ the
output section is enabled and drives the
I/O pad.
• When OE is ‘0’ the output buffer is placed
in a high-impedance state.
• This allows multiple drivers to be connected
on a bus- CONTENTION- A Bus Keeper

9/4/20XX Presentation Title 66

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