CSE 211

Microprocessors
and Applications

Lecture 2
Assembly
Programming
Outline
▪ Introduction.
▪ Intel 8086
Microprocessors.
▪ Assembly Language
Programming.
▪ Program Segments.
▪ Addressing Modes.
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Microprocessor-Based Microcomputer

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Memory (RAM & ROM)

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RAM Read & Write Operations

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Brief History of the Computers

▪ 1946: The first generation of Computer ENIAC was started to be

used based on the vacuum tube technology.
▪ 1958: The first transistorized computer TRADIC was announced by
IBM.
▪ 1959: The first IC (integrated circuit) was invented.
▪ 1960s: ICs were started to be used in CPU boards.
▪ 1970s: Entire CPU was put in a single chip. 1971 the first
microprocessor of Intel 4004 (4-bit data bus and 2300 transistors).
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Brief History of the Computers
▪ 1974: Motorolla 6800 is introduced with 8-bit data bus and 16-bit
address bus.
▪ Late 1970s: Intel 8080/85 appeared with 8-bit data bus and 16-bit
address bus, and it used from traffic light controllers to homemade
computers.
▪ 1978: Intel 8086 is produced with 16-bit data bus and 20-bit
address bus.
▪ 1981: First PC was introduced by IBM with Intel 8088
microprocessor. Apple Macintosh computers started to use 68000
series of microprocessors.
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Evolution of Intel 80x86 Microprocessors

Evolution of Intel 80x86 Microprocessors [ Link ]

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Intel 8086 Microprocessor

▪ The 8086 Microprocessor is a 16-bit CPU.

▪ It operates in single processor or multiprocessor
configurations.
▪ Some of the pins serve a particular function in minimum
mode and others function in maximum mode
configuration.
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Intel 8086 Architecture

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Intel 8086 Pin Diagram

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Registers of 8086 Microprocessor
▪ AX is used for the accumulator, BX is used for base addressing, CX
is used for counter loop operations, DX is used to point out data
in I/O operations.

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Registers of 8086 Microprocessor

▪ [Link1]

▪ [ALU]

▪ [SEG REGs]

▪ [FLAGs]

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Assembly Language Programming

▪ Machine Language:

➢ Programs consist of 0s and 1s are called machine language.

➢ Assembly Language provides mnemonics for machine code

instructions.

➢ Mnemonics refer to codes and abbreviations to make it

easier for the users to remember.

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Assembly Language Programming

▪ Low/High Level Languages:

➢ Assembly Language is a low-level language. It deals directly
with the internal structure of CPU.
➢ The Assembler translates an assembly language program into
machine code.
➢ In high-level languages, the programmer does not have to be
concerned with internal details of the CPU.
➢ Compilers translate the program into machine code.
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MOV Instruction
Example - (8 bits):
MOV CL,55H ;move 55H into register CL
MOV DL,CL ;move/copy the contents of CL into DL (now DL=CL=55H)
MOV BH,DL ;move/copy the contents of DL into BH (now DL=BH=55H)
MOV AH,BH ;move/copy the contents of BH into AH (now AH=BH=55H)

Example - (16 bits):

MOV CX,468FH ;move 468FH into CX (now CH =46 , CL=8F)
MOV AX,CX ;move/copy the contents of CX into AX (now AX=CX=468FH)
MOV BX,AX ;now BX=AX=468FH
MOV DX,BX ;now DX=BX=468FH
MOV DI,AX ;now DI=AX=468FH
MOV SI,DI ;now SI=DI=468FH
MOV DS,SI ;now DS=SI=468FH
MOV BP,DS ;now BP=DS=468FH

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MOV Instruction
Rules regarding MOV instruction:
❖ Data can be moved among all registers except the flag register. There are
other ways to load the flag registers (to be studied later).
❖ Source and destination registers have to match in size.
❖ Data can be moved among all registers (except flag reg.) but data can be
moved directly into nonsegment registers only. You can’t move data
segment registers directly.
Examples:
MOV BX,14AFH ;move 14AFH into BX (legal)
MOV SI,2345H ;move 2345H into SI (legal)
MOV DI,2233H ;move 2233H into DI (legal)
MOV CS,2A3FH ;move 2A3FH into CS (illegal)
MOV DS,CS ;move the content of CS into DS (illegal)
MOV FR,BX ;move the content of BX into FR (illegal)
MOV DS,14AFH ;move 14AFH into DS (illegal)
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MOV Instruction

▪ Important points

❖ Data values cannot be loaded directly into (DS,SS and ES)

MOV AX,1234H ; load 1234H into AX
MOV SS,AX ; load the value in AX into SS

❖ Sizes of the values:

MOV BX, 2H ; BX=0002H, BL:02H, BH:00H
MOV AL, 123H ; illegal (larger than 1 byte)
MOV AX, 3AFF21H ; illegal (larger than 2 bytes)

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ADD Instruction
ADD destination, source; dest = dest + source
mnemonic operands

Example:
MOV AL,24H ; move 24H into AL
MOV DL,11H ; move 11H into DL
ADD AL,DL ; AL=AL+DL (AL=35H)(DL =11H)

MOV CH,24H ; move 24H into CH

MOV BL,11H ; move 11H into BL
ADD CH,BL ; CH=CH+BL (CH=35H)

MOV CH,24H ; load one operand into CH

ADD CH,11H ; add the second operand to CH (CH=35H)

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 ADD Instruction
ADD destination, source; dest = dest + source
mnemonic operands

❖ If destination register is followed by an immediate data as the source, it is called

the immediate operand.
MOV CH, 24H
ADD CH, 11H
❖ 8-bit registers can hold FFH (255) as the maximum value. Addition of larger
numbers can be performed by the 16-bit nonsegment registers.
MOV AX, 34EH
MOV DX, 6A5H
ADD DX, AX ; DX=DX+AX (DX=9F3H)
MOV CX, 34EH
ADD CX, 6A5H ; CX=34EH+6A5=9F3H

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Program Segments (8086 Real Mode)

▪ A segment is an area of memory that includes up to 64K bytes

and begins an address evenly divisible by 16 (such an address
ends in 0 H).
▪ Assembly Language Program consists of three segments:
❖ Code segment: contains the program code (instructions)
❖ Data segment: used to store data to be processed by the
program.
❖ Stack segment: used to store information temporarily.
❖ Extra segment: used to store information temporarily.
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Logical and Physical Addresses (8086 Real Mode)

▪ Physical Address is the 20-bit address that actually put on the address bus
(in 8086).
❖ Has a range of 00000H - FFFFFH
▪ Segment Address is a 16-bit address of the segment block. Each segment is
a block of 64 KB of memory space.
▪ Offset Address is a location within 64K byte segment range.
❖ Has a range of 0000H - FFFFH
▪ Logical Address consists of segment address and offset address.

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Program Segments (8086 Real Mode)

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Program Segments (8086 Real Mode)

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Program Segments (8086 Real Mode)

▪ Addressing in Code Segment:

To execute a program, the 8086 fetches the instructions from the code segment.
The logical address of an instruction consists CS (Code Segment) and IP (instruction
pointer).
Logical Address in Code segment is represented by using segment address in CS
register and Offset Address in IP register as follows:

CS:IP (16-bit CS and 16-bit IP making total of 32 bits)

Example: If CS register contains 2500H and IP register contains 95F3H. What is the
Logical Adress in the code segment?
CS:IP → 2500:95F3 (default in adressing is hex. You don’t need H)

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Program Segments (8086 Real Mode)
Physical Address is generated by shifting the CS one hex digit to the left and
adding IP. Physical address is 20-bit address which can be generated by using a
logical address as follows.
1. Start with CS.
2. Shift left CS (insert 0 as the Least significant digit).
3. Add IP.
Example: If CS register contains 1980 H and IP register contains 78FE H. What is the
Physical Adress in the code segment (in real mode)?
Logical address: CS:IP → 1980:78FE
1. Start with CS 1980
2. Shift left CS 19800
3. Add IP 78FE (19800 + 78FE = 210FE)
Physical address: The microprocessor will retrieve the instruction from the memory
locations starting from 210FE (20-bit address).
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Program Segments (8086 Real Mode)

Example: If CS = 24F6H and IP = 634AH, determine (in real mode):

a) The logical address
b) The offset address
c) The physical address
d) The lower range of the code segment
e) The upper range of the code segment

Solution:
a) The logical address is; 24F6:634A
b) The offset address is; 634A
c) The Physical address is; 24F60 + 634A = 2B2AA
d) The lower range of the code segment: 24F6:0000 → 24F60 + 0000 = 24F60
e) The upper range of the code segment: 24F6:FFFF → 24F60 + FFFF = 34F5F
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 Program Segments (8086 Real Mode)

▪ Addressing in Data Segment

▪ The area of memory allocated strictly for data is called data segment.
▪ Data segment contains variables containing single values and arrays of values,
where code segment only contain program instructions.
▪ Logical Address in Data Segment is represented by using segment address in DS
register and Offset Address in BX, SI or DI registers.
DS:BX
DS:SI
DS:DI
▪ At any time three locations in the data segment are pointed with DS:BX, DS:SI
and DS:DI respectively.

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Program Segments (8086 Real Mode)

Example: If DS = 7FA2H and the offset is 438EH, determine (in real mode) :
a) The physical address
b) The lower range of the data segment
c) The upper range of the data segment
d) Show the logical address

Solution:
a) The Physical address is: 7FA20 + 438E = 83DAE
b) The lower range: 7FA20 + 0000 = 7FA20
c) The upper range: 7FA20 + FFFF = 8FA1F
d) The logical address is: 7FA2:438E
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Program Segments (8086 Real Mode)
• Addressing in Data Segment
Why do we use data segment?
Assume that a program is needed to add 5 bytes of data (25H, 12H, 15H,1FH and 2BH)
One way: MOV AL, 00H ; initialize AL
ADD AL, 25H
ADD AL, 12H
ADD AL, 15H code and data are mixed
ADD AL, 1FH (bad programming practice)
ADD AL, 2BH ; AL=25+12+15+1F+2B

Better way: Assume that the Data segment contains the array of bytes starting from
offset address 0200H.
MOV AL, 0 ; clear AL
ADD AL, [0200] ; add the contents of DS:200 to AL
ADD AL, [0201] ; add the contents of DS:201 to AL code and data are separated
ADD AL, [0202] ; add the contents of DS:202 to AL (good programming practice)
ADD AL, [0203] ; add the contents of DS:203 to AL
ADD AL, [0204] ; add the contents of DS:204 to AL
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Program Segments (8086 Real Mode)

• Little Endian Convention:

Given 8-bit (1-byte) data, bytes are stored one after the other in the memory. However,
given16-bit (2-bytes) of data how are date stored?

Example: MOV AX, 35F3H ; load 35F3H into AX

MOV [1500], AX ; copy contents of AX to offset 1500H
In such a case the low byte goes to the low memory location and high byte goes to the
high memory location.
DS:1500 = F3 DS:1501 = 35

This convention is called little endian convention: This convention is used by Intel.

Big Endian Convention is the opposite, where the high byte goes to the low address and
low byte goes to the high address. Motorola microprocessor uses this convention.

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 Program Segments (8086 Real Mode)

• Logical vs. physical address of the stack:

▪ Calculating the physical address for the stack, the same principle is applied as was
used for the code and data segments.
▪ Physical address depends on the value of stack segment (SS) register and the stack
pointer (SP).
Example: If SS = 3500H and SP = FFFEH:
a) Calculate the physical address: 35000 + FFFE = 44FFE
b) Calculate the lower range of the stack: 35000 + 0000 = 35000
c) Calculate the upper range of the stack segment: 35000 + FFFF = 44FFF
d) Show the logical address of the stack: 3500:FFFE

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Flag Register EMU8086 Tutorial – Page 20

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 Flag Register
CF, the Carry Flag: This flag is set whenever there is a carry out, either from d7 after an 8-bit
operation, or from d15 after a 16-bit data operation.
PF, the Parity Flag: After certain operations, the parity of the result’s low-order byte is checked. If the
byte has an even number of 1s, the parity flag is set to 1; otherwise, it is cleared.
AF, the Auxiliary Carry Flag: If there is a carry from d3 to d4 of an operation this bit is set to 1,
otherwise cleared (set to 0).
ZF, the Zero Flag: The ZF is set to 1 if the result of the arithmetic or logical operation is zero,
otherwise, it is cleared (set to 0).
SF, the Sign Flag: MSB is used as the sign bit of the binary representation of the signed numbers.
After arithmetic or logical operations the MSB is copied into SF to indicate the sign of the result.
TF, the Trap Flag: When this flag is set it allows the program to single step, meaning to execute one
instruction at a time. Used for debugging purposes.
IF, Interrupt Enable Flag: This bit is set or cleared to enable or disable only the external interrupt
requests.
DF, the Direction Flag: This bit is used to control the direction of the string operations.
OF, the Overflow Flag: This flag is set whenever the result of a signed number operation is too large,
causing the high-order bit to overflow into the sign bit.
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 Flag Register
• The Flag Register (FR) and bit fields:
• The Flag register is a 16-bit register sometimes referred as the status register. Although
the register is 16-bit. Not all the bits are used.
• Conditional flags: 6 of the flags are called the conditional flags, meaning that they
indicate some condition that resulted after an instruction was executed. These 6 are:
CF, PF, AF, ZF, SF, and OF.

• The 16 bits of the flag registers:

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 Flag Register
• Manipulating the Flag Register:
• There are two instructions that can be used to use/change the content of
the flag register.

• PUSHF Instruction:
PUSHF ; Copy the flag register into stack
SP register is decremented by 2

Example: Copy the content of the flag register into register AX.
PUSHF ; copy the content of Flag register into the stack.
POP AX ; copy from the stack into AX

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 Flag Register
• Manipulating the Flag Register:
• There are two instructions that can be used to use/change the content of
the flag register.

• POPF Instruction:

POPF ; Copy from the stack into the flag register

SP register is incremented by 2

Example: Clear the flag bits. (Make the flag bits to be all 0)
MOV AX, 0000H
PUSH AX ; now top of the stack contains 16-bit 0.
POPF ; copy the content of stack into flag register.
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Flag Register
• Flag Register and ADD instruction
• The flag bits affected by the ADD instructions are: CF, PF, AF, ZF, SF and OF. The OF will
be studied later.
• Example: Show how the flag register is affected by the addition of 38H and 2FH.

Solution: MOV BH, 38H ; BH = 38 H

ADD BH, 2FH ; BH = B H + 2F = 38 + 2F = 67 H
38 0011 1000
+ 2F + 0010 0111
67 01100111
CF = 0 since there is no carry beyond d7
PF = 0 since there is odd number of 1`s in the result
AF = 0 since there is no carry from d3 to d4
ZF = 0 since the result is not zero
SF = 0 since d7 of the result is positive
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 Flag Register
• Flag Register and ADD instruction
• The flag bits affected by the ADD instructions are: CF, PF, AF, ZF, SF and OF. The OF will be
studied later.
• Example: Show how the flag register is affected by the following addition.
Solution: MOV AX, 34F5H ; AX = 34F5 H
ADD AX, 95EBH ; AX = CAE0 H
34F5 0011 0100 1111 0101
+ 95EB 1001 0101 1110 1011
CAE0 1100 1010 1110 0000
CF = 0 since there is no carry beyond d15
PF = 0 since there is odd number of 1s in the lower byte
AF = 1 since there is a carry from d3 to d4
ZF = 0 since the result is not zero
SF = 1 since d15 of the result is 1
• Note that the MOV instruction has no effect on the flags.
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 Flag Register
• Use of zero flag for looping:
• Zero flag is used to implement the program loops. Loop refers to a set of instructions
that is repeated a number of times.

• The following example shows the implementation of the loop concept in the program
which adds 5 bytes of data. Assume that the beginning address of the array of 5 bytes
starts from offset address 0200H in the data segment.

• Example: MOV CX,05 ; CX holds the loop count (counter)

MOV BX,0200H ; BX holds the offset data address
MOV AL,00 ; initialize AL
ADD_LP: ADD AL,[BX] ; add the next byte to AL
INC BX ; increment the data pointer
DEC CX ; decrement the loop counter
JNZ ADD_LP ; jump to the next iteration if the counter not zero

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Addressing Modes
• The CPU can access operands (data) in various ways, called addressing modes.
In 80x86, there are 7 addressing modes:
1. register.
2. immediate.
3. direct.
4. register indirect.
5. based relative.
6. indexed relative.
7. based indexed relative.
1. Register addressing mode:
❖ involves the use of registers
❖ memory is not accessed, so faster
❖ source and destination registers must match in size.
Example: MOV BX,DX ; possible
MOV ES,AX ; possible
ADD AL,BH ; possible
MOV AL,CX ; not possible
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Addressing Modes
2. Immediate addressing mode:
❖ source operand is a constant
❖ possible in all registers except segment , instruction pointer, and flag registers.

Ex: MOV BX,1234H ; move hex value 1234H into BX

MOV CX,223 ; load the decimal value 625 into CX
ADD AL,40H ; AL=AL+33H
Ex: MOV DS,1234H ; illegal

3. Direct addressing mode:

❖ address of the data in memory comes immediately after the instruction operand is a constant
❖ The address is the offset address. The offset address is put in a rectangular bracket❖
Ex: MOV DL,[2400] ; move contents of DS:2400H into DL

Ex: Find the physical address of the memory location and its content after the execution of the
following operation. Assume DS = 1512H
MOV AL,99H ; Physical address of DS:3518 => 15120+3518=18638H
MOV [3518],AL ; The memory location 18638H will contain the value 99H

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Addressing Modes
4. Register indirect addressing mode:
❖ The address of the memory location where the operand resides is held
by a register.
❖ SI, DI and BX registers are used as the pointers to hold the offset
addresses.
❖ They must be combined with DS to generate the 20-bit physical address

Ex: MOV AL, [BX] ; moves into AL the contents of the memory location pointed to by DS:BX

Ex: MOV CL, [SI] ; move contents of DS:SI into CL

MOV [DI], AH ; move the contents of AH into DS:DI

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MOV Instruction EMU8086 Tutorial – Page 6

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MOV Instruction

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Assembly Program Structure

Write an 8086-assembly

program to add a data byte

located at offset A1 to

another data byte available

at offset A2, and store the

result at offset RES.

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Textbook

▪ Brey, Barry B. , The Intel microprocessors 8086/8088,

80186/80188, 80286, 80386, 80486, Pentium, Pentium
Pro processor, Pentium II, Pentium III, Pentium 4, and
Core2 with 64-bit extensions: Architecture,
Programming, and Interfacing , 8th Ed.

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