A Survey of Graph Neural Networks

for Electronic Design Automation

Daniela Sánchez Lopera ∗‡ , Lorenzo Servadei ∗ , Gamze Naz Kiprit ∗‡ ,
Souvik Hazra∗ , Robert Wille† , Wolfgang Ecker∗‡
∗ Infineon Technologies AG, Germany, † Johannes Kepler University Linz, Austria,
‡ Technical University of Munich, Germany

Abstract—Driven by Moore’s law, the chip design complexity can be conducted by ML while optimizing PPA. Finally,
is steadily increasing. Electronic Design Automation (EDA) has Reinforcement Learning (RL) explores the design space, learns
been able to cope with the challenging very large-scale integra- policies, and executes transformations to get optimal designs
tion process, assuring scalability, reliability, and proper time-
to-market. However, EDA approaches are time and resource- envisioning the future with an “AI-assisted Design Flow”.
demanding, and they often do not guarantee optimal solutions. One enabling factor for using ML in EDA is the huge
To alleviate these, Machine Learning (ML) has been incorporated amount of data that is generated by the EDA tools along
into many stages of the design flow, such as in placement the design process. To apply ML over such data, these
and routing. Many solutions employ Euclidean data and ML have to be pre-processed and labeled. Existing solutions
techniques without considering that many EDA objects are
represented naturally as graphs. The trending Graph Neural use such data as Euclidean data, i.e. representing them in
Networks are an opportunity to solve EDA problems directly a 2-D Euclidean space, allowing the use of ML methods
using graph structures for circuits, intermediate RTLs, and such as Convolutional Neural Networks (CNNs). However,
netlists. In this paper, we present a comprehensive review of the the trending neural network framework for graphs called
existing works linking the EDA flow for chip design and Graph Graph Neural Networks (GNNs) has shown a significant im-
Neural Networks.
Index Terms—Electronic Design Automation, Very Large-scale provement in dealing with data whose structure is intuitively
Integration, Machine Learning, Register-Transfer Level, Graph a graph. Even though GNNs appeared already in 2005, their
Neural Networks recent combination with Deep Learning (DL) operations like
convolution and pooling has drawn significant attention in
I. I NTRODUCTION fields such as molecular graphs [2], recommendation sys-
Over time, the chip design flow has incorporated multiple tems [3], and traffic prediction [4].
software tools to synthesize, simulate, test, and verify different In EDA, the most natural representation of circuits, inter-
electronic designs efficiently and reliably. The compendium of mediate RTL, netlists, and layouts are graphs. Thus, in the last
those tools is called Electronic Design Automation (EDA). two years, few studies have recognized this opportunity and
Those tools automatize the chip design flow sketched in have incorporated the usage of GNNs to solve EDA problems.
Figure 1. Nevertheless, the flow is sequential and time- This survey gives a comprehensive review of some recent
demanding. Often, the design has to be verified and tested to studies using GNNs in different stages of the EDA flow. It
ensure correctness, reliability, and objective closure. But only first provides background on both fields and, successively,
during physical verification and signoff, and testing, the quality a list of the seminal related works. The rest of this survey
of the design in terms of Power, Performance, and Area (PPA) is organized as follows: In Section II, we briefly review the
can be measured. Corrective modifications in intermediate EDA flow and background concepts. In Section III, we provide
steps are often needed, and they result in multiple iterations of a more detailed explanation of the different types of GNNs.
the design flow. Thus, estimations of PPA in earlier stages of In Section IV, we discuss different studies applied to EDA.
the design would reduce the required iterations, increase the Finally, Section V concludes by briefly mentioning some open
reliability of the design while going deeper on the flow, and challenges and future directions.
finally, improve the Quality of Results (QoR).
In the last years, design complexity driven by Moore’s II. BACKGROUND AND D EFINITION
law has increased. Chip capacity has been doubling around In this section, we briefly review background concepts
every two years, which translates into increasing efforts for related to EDA flow, graphs and GNNs.
the design and verification of even more diversified chips.
EDA tools have aimed at coping with the new challenges and A. Electronic Design Automation
provided automated solutions for Very Large-Scale Integration The progress in EDA tools and design methods, and the
(VLSI). EDA tools commonly face NP-complete problems, use of different levels of abstractions on the design flow
which Machine Learning (ML) methods could solve better and have improved the hardware design productivity. Figure 1
faster. Thus, ML has been integrated into EDA, specially to sketches the stages of a modern chip design process. The
logic synthesis, placement, routing, testing and verification [1]. flow starts with the chip specification modeling the desired
In [1], four main areas of action were recognized. First, ML is application. The architecture analysis and prototype of the
used to predict optimal configurations for traditional methods. design represent the design as a collection of interacting
Second, ML learns features of models and their performances modules such as processors, memories, and buses. In the
to predict the behavior of unseen designs without running the functional and logical design, the behavioral description of
costly step of synthesis. Moreover, design space exploration those modules is mapped to Register Transfer Level (RTL)
978-1-6654-3166-8/21/$31.00 ©2021 IEEE blocks using Hardware Description Languagess (HDLs) such
 Functional
Architectural Logic Physical
and Logic Fabrication Packaging
Design Synthesis Design
Design

// module.v

module switch(input1, clk);

System CPU Mem always @(posedge clk)
begin

Specification Bus
if (input1==1) begin
...
end
else if
...
I/O ASIC end
end
endmodule

Fig. 1. Chip Design Flow

as Verilog. Nowadays, the transition from system specification or real-value, the graph is called weighted, and the matrix
to RTL can be done in different ways. For instance, using A will have real-values as entries. Multiplex graphs can be
High-level Synthesis (HLS), which provides an automatic decomposed into layers, and the relation between each layer
conversion from C/C++/System-C specifications to HDL, or and the belonging nodes are additional intra-layer edges.
using hardware design frameworks such as MetaRTL [5]. Graphs can also be homogeneous or heterogeneous. In the
Logic synthesis maps the RTL blocks in HDL to a combi- former, all nodes and edges have the same type. In the latter,
nation of gates selected from a given technology library while nodes have different types and their attributes may be of
optimizing the design for different objectives. Normally, this distinct types too (e.g. text or images) [6].
optimization involves a trade-off between timing closure, and
area and power consumption. C. Shallow Embeddings Methods
In physical synthesis, four main steps are executed: floor- The traditional approach for processing graph-structured
planning, placement, clock insertion, and routing. First, main data is to use shallow embedding methods. These aim to
RTL blocks of the chip and ports are assigned to regions of decompose the node information into low-dimensional em-
the layout. Second, the gates of the resulting logic netlists are bedding vectors that consider the position of the nodes in
placed to specific locations of the chip. Finally, the wires for the graph and the structure of the neighborhood [6]. One
clock signals and for connecting the gates are added. These of the best-known graph embedding techniques is Random
steps are executed targeting better area utilization, timing Walk [7]. In this technique, given a starting point within
performance, and routability while considering design rules. a graph, a random neighbor point is selected. As a second
Since errors in the design cost time and resources, verifi- step, a neighbor of the randomly selected point is chosen
cation is a fundamental step of the flow and is executed after again. This, in a recursive fashion. This generates a random
functional and physical design. After verification and signoff, sequence of points, namely the random walk. DeepWalk [8]
the design goes through the manufacturing flow: fabrication, and Node2vec [9] are well-known graph embedding methods
packaging, and final testing. that are based on random walks. Although these methods
Even though the flow is highly automated, it encounters have achieved groundbreaking success, they are transductive,
some drawbacks: (1) It relies on the hardware designer’s i.e. they learn a unique embedding vector per node. Thus,
expertise to select proper configurations, (2) Design space they have two main limitations: They are computationally
exploration is limited and time-demanding, (3) Corrections in expensive in large graphs, and they cannot deal with unseen
the design would reinitialize the flow, (4) There is no early nodes. Moreover, they do not consider node features that could
analysis or predictability of the results. provide information during the encoding [6].

B. Graphs D. Graph Neural Networks

a) Definition I (Graphs): A graph is a data structure for To overcome the limitations of the shallow methods, a novel
representing interactions between related objects. Mathemat- Neural Network (NN) called GNN was introduced in [10].
ically, it is as a tuple G = (V, E), where V is the set of GNNs are a framework for NNs, that operate directly on
nodes and E, the set of edges. The edges are defined as the data structured as graphs, without losing structural and feature
connection between nodes, e.g. for the nodes u, v ∈ V , the information [10]. Originally, GNNs were formulated as a type
edge is represented as eu,v ∈ E. The neighborhood of a node of Recurrent Neural Networks (RNNs) trained by a version of
N (v) is defined as N (v) = u ∈ V |(u, v) ∈ E. A graph can backpropagation through time [11].
Having an input graph, a GNN aims to learn the embedding
be represented then as a list of nodes and edges. But a more
vectors per node, defined as hu ∀u ∈ V , which encodes the
convenient representation is through an adjacency matrix A
neighborhood information of each node [12]. The message
defined as Au,v = 1 if eu,v ∈ E, otherwise Au,v = 0. The
passing between nodes is assumed as the most generic GNN
degree of a node is the number of nodes D incident to a node
P layer [11]. Through the message passing updates determined
u, mathematically it can be defined as Du = v∈V Au,v [6].
by the graph structure, the edge embeddings he(u,v) are ob-
A graph with n nodes and m edges may have node and
edge features of dimension d and c respectively, i.e. the node tained using Equation 1.
features are X, where X ∈ Rn×d and the edge features Xe , he(u,v) = φ(hu , hv , xe(u,v) ), (1)
where Xe ∈ Rm×c [6].
b) Definition II (Types of Graphs): Graphs are classified where φ(·) is an arbitrary, non-linear, differentiable function
into different classes. If the direction of the edges matter, that aggregates its inputs, and xe(u,v) the initial edge feature
the graph is directed and the adjacency matrix A will be vector. After the edge representation is obtained, and defining
symmetric. If the edges do not have a direction, the graph x(u) as the feature vector for the starting node, the node
is undirected. In case the edges are represented with a cost representation is updated as in Equation 2.
 EDA Featured and Labelled Graphs GNNs Embedding Representation ML Task
x_u
h_u Node:
u u
Circuits Classification,
e_uj
Netlists Regression
x_v e_uz RecGNN
h_*
v ConvGNN v h_v Edge:
GAE
Spatial-temporal Classification,
Tools z z Link Prediction
Labels
Graph:
y y Classification

Fig. 2. End-to-End flow using EDA objects as graphs. Feature nodes x and ground truth labels (e.g. red and green flags) are collected using EDA tools. One
of the GNNs flavors extracts node embeddings h, which are the inputs to other ML methods for classification or regression at node, graph, or edge level.

0 X high-level embeddings of the nodes by aggregating the features

hu = φ(hu , he(v,u) , xu ) (2) of the central node and the neighbor nodes. Mathematically,
v∈N (u) this is expressed as in Equation 4.
 X 
The graph embeddings learned by GNNs can be used as 1
h(l+1)
u = φ h (l)
W (l)
, (4)
inputs to other ML models building an end-to-end framework c(u,v) v
v∈N (u)
depicted in Figure 2. There are three levels of tasks for such p p
a framework: Node, edge, and graph [12]. In the node-level where c(u,v) = |N (u)| |N (v)| is the normalization con-
tasks, all nodes are labeled so that a regression or classification stant of the edge eu,v , W is a learnable weight matrix,
of the nodes is possible. In edge-level tasks, the goal is to l ∈ {1, ..., L} with L being the number of layers, and φ is the
classify edges or predict the link between two nodes. Finally, non-linear activation function [12]. Even though GCN are very
in graph-level tasks, the entire graph is labeled and a NN, powerful in generating low-dimensional embeddings of large
combined with pooling and readout operations, can classify graphs, they are transductive, i.e. all possible nodes have to
new unseen graphs. Moreover, the learning tasks of GNNs can be present during training. To alleviate this, GraphSAGE [15]
be transductive or inductive. In the former, the GNN learns proposes an inductive framework that generalizes to unseen
the embedding vectors per each node in the training graphs. nodes. It utilizes an update rule which is similar to Equation 4,
Thus, during inference, it cannot generalize to new nodes. On by defining c(u,v) = |N (u)|.
the contrary, an inductive GNN learns the aggregation function GraphSAGE uses a fixed-size neighborhood of the nodes,
that combines the node’s neighborhood features to get the which can limit the network performance during inference.
embedding vectors [12]. To solve this, Graph Attention Networks (GATs) [16] were
introduced. A GAT computes each node embeddings by going
III. C LASSIFICATION OF GNN S through all the neighbors using the self-attention mechanism
GNNs are divided into four types [12]. In this section, we presented in [17]. Mathematically, this node embedding pro-
review them and describe their core ideas. cess can be expressed as in Equation 5.
!
A. Recurrent Graph Neural Networks (l+1)
X (l)
(l)
hu =φ α(u,v) zv , (5)
Recurrent Graph Neural Networks (RecGNNs) [13] process v∈N (u)
the node information recurrently by assuming that the nodes
exchange information with their neighbors until a stable point (l) (l)
where zu = W(l) hu , and α(u,v) is the normalized attention
is reached. RecGNNs define the node aggregation function as score of the node v to u calculated by the l-th attention mecha-
in Equation 3. nism. The main benefit of GAT is not only the consideration of
X the entire neighborhood of each node but also the increasing
htu = φ(xu , xe(u,v) , xv , h(t−1)
v ), (3) model’s expressiveness that comes with the specification of
v∈N (u) different relevance scores of each edge for a given node.
where φ(·) is a non-linear differentiable recurrent function. C. Graph Autoenconders
In [13], the proposed architecture is a RNN where the con- Graph Autoencoders (GAEs) belong to the family of un-
nections between the neurons are classified into internal and supervised frameworks and are used for graph-based repre-
external connections. While the first refer to the internal sentation learning and graph generation [12]. In both tasks,
connections within units of the network, the external ones refer an encoder is employed to extract node embeddings of a
to the edges of the processed graph. graph, followed by the reconstruction of new graphs from
B. Convolutional Graph Neural Networks corresponding latent or embedding vectors. For representation
learning, graph structural information is reconstructed as an
Convolutional Graph Neural Networks (ConvGNNs) are a adjacency matrix. In the case of graph generation, the process
generalization of CNNs to graph data and are divided into might involve a step-wise generation of the nodes and edges,
spectral, and spatial approaches. The spectral approaches are or output the entire graph at once.
based on the Laplacian’s eigenbasis, which differs depending
on the graph structure. Spatial approaches, however, are based D. Spatial–Temporal Graph Neural Networks
on the spatial structure of the graph, i.e. they work on Spatial-Temporal Graph Neural Networks (STGNNs) aim
spatially close neighbors [12]. In [14], a spectral approach for at capturing underlying spatial and temporal relation simul-
performing the convolution operations on graph structures has taneously [12]. The spatial relation is captured by using
been presented. This is named Graph Convolutional Networks graph convolutions, and the temporal relation is modeled by
(GCNs). The main principle of this approach is to extract the employing RNN blocks.
 IV. A PPLICATION TO EDA the same device. D-SAGE leverages GraphSAGE to support
These two seminal papers [18], [19] highlight the important directed graphs and distinguish between successors SU (u) and
link between EDA tasks and GNNs. predecessors P R(u) of a node u. To that end, Equation 4 is
The first study to recognize the high potential of GNNs split over SU (u) and P R(u), and finally, the successors and
in EDA is [18]. They stated that graph structures are the predecessors embeddings are concatenated as in Equation 6.
most intuitive way to represent Boolean functions, netlists, and  
(l+1) (l+1)
layouts, which are the main focus of the EDA flow. They see h(l+1)
u = φ hu,P R , hu,SU (6)
GNNs as an opportunity for EDA to improve the QoRs and to
replace the used traditional shallow methods or mathematical Using the graph embeddings, D-SAGE solves two end-to-
optimization techniques. The paper lists related studies that end tasks: Binary node classification, to predict which nodes
have been applying analytical and heuristic approaches and are mapped to which device, and binary edge classification,
shallow methods to EDA. Finally, they introduced spectral- to cluster nodes mapped into the same device. D-SAGE
based and spatial-based GNNs and presented only two cases outperforms HLS tools in node classification, edge prediction,
of study: Test point insertion and timing model selection. and also in operation delay estimation across all data paths.
In [19], a review of CNNs as well as GNNs used in the
EDA flow was presented. They stated that ML could improve B. Verification and Signoff
the QoRs during the chip design flow by predicting important Verification is done to check the functionality of the design
metrics in different phases such as design space exploration, after functional, logic, and physical design. Especially before
power analysis, physical design, and analog design. Similar fabrication, the correctness of the design has to be assured.
to [18], they envisioned the use of Deep Reinforcement In the signoff step, a set of verification steps is executed to
Learning (DRL) to solve combinatorial optimization problems formally verify the functionality but also design closure, signal
in EDA, similarly to what is done in [20]. integrity, lifetime checks, etc. The design closure is determined
In [18] and [19], the motivation of incorporating the trend- in terms of PPA. Negative results in this step translate into
ing GNNs into the EDA flow is clear. However, they did not going backward on the flow and increasing the time-to-market
exclusively center on both areas. [18] focuses also on existing of the chip. Therefore, early, accurate and fast estimations of
applications using traditional shallow methods. On the other those constraints could accelerate the design process.
hand, [19] reviews the use of CNNs and GNNs. Moreover, [19] For instance, the power integrity signoff requires power
compares the applications from an EDA perspective, without analysis of the design. For this, vector-based methods are
revealing the details of the GNN concepts behind. preferred because of their accuracy, but they require gate-level
Considering the drawbacks of the above-mentioned work, simulations, that are time-demanding and replaced in practice
this survey gives a background and a review of recent im- by Switching Activity Estimators (SAEs). SAEs are fast but
portant studies applying GNNs to the EDA field. To clarify not accurate. In [22], an alternative method based on GNN
the link between both areas, the review of these studies is is proposed using toggle rates as inputs and improving the
organized according to their corresponding stages in the design prediction accuracy. To that end, they built a graph based on
flow. Table I lists the studies considered in this review. the netlist, where single-output components are the nodes. The
edges are defined as the connection between gates. From the
A. Logic Synthesis RTL simulations, input and register toggle rates are taken as
During logic synthesis, the RTL blocks describing the feature nodes, which are encoded in a 4-D vector. Finally, the
hardware design are mapped to logic cells from a technology predicted toggle rates per gate are evaluated against the ground
library. This mapping must meet the timing constraints to truth labels obtained by the gate-level simulation. Intuitively,
operate at the desired clock rate while considering area and the toggle rates are expected to propagate from one level to
power. Therefore, synthesis is a complex optimization problem the next one. Therefore, they proposed GRANNITE [22], a
where ML can be applied. For instance, providing earlier sequential and inductive version of a GCN, in which the node
QoR predictions to avoid multiple runs of the time-demanding embeddings are not calculated in parallel but sequentially.
synthesis step. Using the node embeddings, GRANNITE predicts average
To predict a more accurate delay for Field Programmable toggle rates from RTL simulations in few seconds with more
Gate Array (FPGA) blocks, [21] proposes to learn the mapping accuracy than classical SAEs.
and clustering patterns of arithmetic operations in FPGAs,
specially Digital Signal Processor (DSP) and carry blocks. C. Floorplanning
They recognized that current HLS solutions only sum up the In chip floorplanning, the main and large blocks of a netlist
individual delays of each component along the paths. This are placed onto 2-D grids aiming for optimal PPA, while
does not consider the underlying optimizations done during obeying design rules. This can be represented as a Markov
the synthesis. As solution, they proposed a novel architecture process, which can be solved using RL.
D-SAGE [21], a GNN to predict the complex technology The most significant work in this area is presented in [23].
mapping done by logic synthesis. In [21], designs are mapped Google demonstrates the success of chip macro placement
to Data Flow Graphs (DFGs). The nodes are the set of opera- using a DRL framework for the floorplanning of Tensor
tions (i.e. additions or multiplications), and the edges, the data Processing Unit (TPU) accelerators. In [23], a GNN is in-
dependencies between the nodes. Node types and bit widths of corporated to the RL framework to encode the different
the data are considered as node attributes. Nodes and edges are states of the process, predict the reward labels for congestion,
labeled according to the end-to-end task. For instance, if the density, and wirelength, and generalize to unseen netlist. The
nodes are mapped to DSP blocks or Lookup Tables (LUTs), proposed architecture is called Edge-Based Graph Neural
they are labeled to one or zero, respectively. Similarly, edges Network (Edge-GNN) [23], which calculates the node and
are marked with one if their connected nodes are mapped to edge embeddings for the whole netlist. This RL agent gives
 TABLE I
S UMMARY OF GNN S FOR THE EDA FLOW

Section GNN Algorithm Type of Task End-to-End Task Reference

Logic Synthesis GraphSAGE Node classification Learning mapping patterns from HLS to FPGA blocks D-SAGE [21]
Verification and Signoff GCN Node regression Vector-based average power estimation GRANNITE [22]
Floorplanning GCN GNN-RL Floorplanning optimization as RL task Edge-GNN [23]
GAT Node regression Net length estimation Net2 [24]
Placement GraphSAGE Node clustering Optimization of placement groups as guidance for tool PL-GNN [25]
GraphSAGE GNN-RL Generalization PPA optimization as RL task - [26]
GraphSAGE GNN-RL Optimization of placement parameters using RL - [27]
Routing GAT Node regression Estimation routing congestion CongestionNet [28]
Testing GCN Node classification Prediction of observation point candidates - [29]
GraphSAGE, GAT Node regression Prediction of net parasitic capacitances ParaGraph [30]
Analog Design GNN Graph regression Simulation electromagnetic properties of distributed circuits CircuitGNN [31]
GCN GCN-RL Transferring knowledge of transistor sizing Circuit Designer [32]
GAT Node regression Prediction analog circuit performance due to placement PEA [33]

comparable or better results than a human designer but takes netlist. The GCN is a key component because it extracts local
hours instead of months. and global information, which is needed by the RL agent.
Wirelength optimization during 2-D placement is analyzed as
D. Placement a case of study.
During placement, the design gates are mapped to the In [27], an autonomous RL agent finds optimal placement
exact locations of the chip layout. The larger the design, parameters in an inductive manner. Netlists are mapped as
the more complex this process is. A poor decision during directed graphs, and nodes and edges features are handcrafted
placement can increase the chip area but also worsen the chip placement-related attributes. GraphSAGE learns the netlist
performance and, even, make it unsuitable for manufacturing embeddings and helps to generalize to new designs.
if the wirelenght is higher than the available routing resources.
Therefore, placement is seen as a constrained optimization E. Routing
problem. ML and specially, GNNs are being explored to ease In this step, the placed components, gates, and clock signals
this steps [24], [25], [26], [27]. are wired while following design rules (e.g. type of permitted
A GAT called Net2 is used to provide pre-placement net angles). These rules determine the complexity of the routing,
and path length estimations in [24]. To that end, they converted which is mostly an NP-hard or NP-complete problem. Thus,
the netlists to directed graphs, where nets represent nodes, and routing tools are mostly based on heuristics, and they do not
edges connect nets in both directions. The number of cells, fan- aim to find an optimal solution. ML methods could enhance
in, fan-out sizes, and areas are used as feature nodes. The edge the routing process by providing earlier estimations, which can
features are defined using clustering and partitioning results. be used to adjust the placement accordingly, and avoid high
The ground truth label for the nodes is the net length obtained area and long wires.
as the half-perimeter wirelength of the bounding box after In [28], a GAT is used to predict routing congestion values
placement. During inference, Net2 predicts the net length per using only a technology-specific gate-level netlist obtained
node, outperforming existing solutions. For instance, Net2a , a after physical design. To that end, the netlists are built as
version targeting accuracy, is 15% more accurate in identifying undirected graphs, where each gate is a node, and the edges are
long nets and paths, and Net2f targeting runtime, is 1000 × defined as the connections between gates that are connected by
faster. a net. The feature nodes are 50-D vectors containing informa-
In [25], GraphSAGE is leveraged to build PL-GNN, a tion about cell types, sizes, pin counts, and logic descriptions.
framework helping placer tools to make beneficial decisions To get the ground truth labels for the nodes, congestion maps
to accelerate and optimize the placement. PL-GNN converts are split into grids, and the congestion value of each grid is
netlists to hypergraphs, where nodes and edges features are taken as a label for the cells that were placed into that grid.
based on the hierarchy and the affinity of the net with The architecture presented in [28] called CongestionNet is not
memory blocks, as this provides information about critical more than an eight-layer GAT following the Equation 5. The
paths. A GNN is used to learn the node embeddings, which node embeddings are used to predict local congestion values.
are clustered by the K-means algorithm to determine optimal Using GATs improves the quality of the predictions, and the
placement groups based on the cell area. This guidance leads inference time is around 19 seconds for circuits with more
the placer tool to a placement that reduces wirelength, power, than one million cells.
and worst slack.
A proof of concept framework mapping the PPA optimiza- F. Testing
tion task in EDA to a RL problem is presented in [26]. This Testing takes place only after the packaging of the design.
RL framework uses GraphSAGE with unsupervised training to The larger the design, the higher the complexity and the
learn node and edges embeddings that can generalize to unseen execution time of the testing tools. Moreover, testing should
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