What are the inputs at the floorplan stage?

1. Synthesized Netlist
2. Timing Library (LIB)
3. Physical Library (LEF- Library Exchange Format)
4. Design Exchange Format (DEF)
5. Unified Power Format (UPF)
6. Standard Design Constraint (SDC)

What are the two types of lef and what is present in both the lef ?
1. Technology LEF
2. Cell/Macro LEF

What is there in .lib file?

The timing library is an ASCII representation of the Timing, Power and Area
associated with the standard cells.
• Characterization of cells under different PVT conditions results in the timing
library (.lib).
• The delay calculation happens based on input transition (Slew) and the output
capacitance (Load).
• Nowadays, CCS and ECSM models are used to characterize the library,
where the calculations are based on current models which is more accurate.
(In earlier days, it was NLDM model which was based on voltage calculation.)
• There are basically three major parts in the .lib file:
1. Global definition
2. Cell definition
3. Pin definition

What kind of physical libraries are used?

There are basically two types of physical libraries (LEF):
• Tech LEF: Technology LEF file contains all the details about the Metal layer
information (Type, Direction, Pitch, Offset, Area, Width, Mincut, Resistance,
Capacitance, Edge Capacitance, Thickness, Antenna Model, Antenna Ratio,
etc.), Via Definition (Type, Spacing, Width, Enclosure, Antenna model,
Antenna Ratio etc.) , Site Info, Resistance, Capacitance, Edge Capacitance,
Antenna information, etc.
• Macro LEF: Macro/Cell LEF contains all the information about the standard
cell physical information, Macro cell physical information (Class, Origin,
Symmetry, Site, Pin Direction, etc.), Pin location etc.

How much space is required between macros?

Distance between macros = (No. of Pins * pitch *2) / Available metal Layers.

What is the difference between soft & hard placement blockage?

Soft Blockages: Soft blockages do not allow cells to place during the placement,
but this region can be used during in-place optimization, CTS, ECO etc. Basically, it
is not adding any STD cell but buffers and inverters for the optimization.
Hard Blockages: Hard blockages never allow any cells to place where the region is
defined.

Why is it not recommended to place the macros at the centre?

If we place the macros at the centre, then all the std cell logics will be sitting around
the macros and we might get detour which will impact quality of result like timing,
long nets etc. check out the macro placement guidelines in below link.

What is placement?
Placing of standard cells in the design is known as placement.

What are the pre placement sanity checks?

• Floating pins in netlist
• Unconstrained Pins
• Undriven Input Ports
• Unloaded Output ports
• Pin direction Mismatch
• Timing
• Check Physical constrains (mainly FP objects)
• PG grid check
• Check Legality such as orientation, overlap etc
• Check Quality Of Results (QOR)

What are the stages of placement?

• Global Placement
• Refine Placement (Legalization)
• Detailed Placement

What are the objectives/quality checks of placement?

• Congestion
• Performance (Timing)
• Power
• Routability
• Placement Runtime

What is congestion?
If the number of required routing resources are more than the number of available
routing tracks, then this phenomenon is known as congestion.

What are the types of congestion?

1. Placement congestion
2. Routing congestion.

What are the reasons for congestion?

• Bad Floorplan.
• High standard cell density in particular area.
• High pin density in particular area.
• Missing/Small Halos near macro cell.
• Huge number of cells sitting near the macro cell.

What are the ways to fix congestion issues?

• Use blockages in the design, partial blockages help more in optimized way.
• Cell padding
• Module padding
 • Decomposition of large cells into small cells (Pin distribution happens)

What are the different ways for placement optimization?

• Adding buffers
• Resizing gates
• Restructuring the Netlist
• Remapping Logic
• Swapping pins
• Deleting buffer
• Moving Instances
• Apply useful Skew
• Layer optimization
• Track Optimization

What is there in place_opt log file? What is optimization or steps it does in this
stage?
Place_opt stage does all the optimization after detail placement. Checkout the below
link which says all the details about the optimization.

How does ‘specify cell padding’ work?

Cell padding is the method to reduce congestion in some particular area where there
are too many cells sitting. If we use cell padding in a cell that means we basically
make fool to tool and does not allow any other cells in that particular area. It is a
simple tool command like “specify_cell_pad” or similar based on tools which we use
in our tool.

Have you use bounds/groups for placement? If yes, in what scenarios you
have added those?
The situation where timing critical paths are getting disturbed because of placement
of cells has happened too far and we don’t have timing margins on these paths,
which may be because of logic groups or macros etc then we need to create a
physical bound where we place these logic groups in that particular area only. Which
helps us converge timing.

What are the steps of placement? What checks will you do in placement
stage?
Global Placement
Refine placement
Detail placement
If you want to dig into these steps and wants to read more for cross questions in
interview, then go for below links.
https://ivlsi.com/global-placement-vlsi-physical-design/
https://ivlsi.com/refine-placement-detailed-placement-vlsi-physical-design/

What are the checks you will perform after placement completes?
Placement objectives and quality checks are written in details in below links.
https://ivlsi.com/placement-vlsi-physical-design/

What is secondary PG routing?

Secondary PG details are in below link.
https://ivlsi.com/placement-optimization-vlsi-physical-design/

What is scan chain reordering and why it is done during placement stage?
Scan chain DEF contents and scan chain reordering are explained in below link.
https://ivlsi.com/scan-chain-reordering-vlsi-physical-design/

How does partial density help?

Partial density is basically a partial blockage, here is the link for more details.

What are the CTS inputs?

Placement DB
CTS Spec File

What does the CTS Spec File contain?

1. Inverters or buffers to be defined which will be used to balance the
clock tree.
2. CTS Exceptions (End points of clock tree).
3. Skew group information.
4. Contains target Skew, max target transition and other timing
constraints as per clock tree.
5. Top layer and bottom layer route info. VIA’s information which will be
used during clock route.
6. Clock related info (Generated clocks {E.g. Clock divider, Clock
multiplier etc}).
7. NDR Rule definition.

What are the quality checks for CTS?

• Minimize Insertion Delay
• Skew Balancing
• Duty Cycle
• Pulse Width
• Clock Tree power consumption
• Signal Integrity and Crosstalk
For detailed concept visit the below link.
https://ivlsi.com/clock-tree-synthesis-cts-vlsi-physical-design/#CTS_Quality_Checks

What are the Clock Exceptions?

There are many points present in the design after which we don’t need clock tree
propagation. So, to avoid unnecessary buffering, we can ask the tool not to go for
balancing further to these points.
There are following clock tree exceptions:
Stop Pin – No buffer/inverter insertion beyond this point (Don’t touch scenario)
Ignore Pin (Float Pins) – No DRV, No Balance
Exclude Pin – DRV Fixing but no balancing
Through Pin – DRV Fixing as well as Balancing
Please visit below link for more details.
https://ivlsi.com/clock-tree-synthesis-cts-vlsi-physical-design/

How to reduce congestion post CTS?

Read the below link.
https://ivlsi.com/clock-tree-synthesis-cts-vlsi-physical-design/

In CTS, what type of NDRs have you used & why?

To understand the NDR in detail visit below link.
https://ivlsi.com/cts-spec-file-vlsi-physical-design/

Explain Multi Point CTS?

For big designs like 5 mm, 8mm, or 10mm length we can not depend on the typical
tool strategies to do clock tree balancing. If we will depend then there will be a very
high latency number, and unnecessary buffering will happen then lots of power
issues will be there and basically not acceptable clock tree. so to avoid this we
create tap points in between this long size design wherever we have pipeline
registers placed. In this situation we are not going to do balancing w.r.t clock port but
w.r.t tap points which is also named as multi-source CTS points. Looking at these
points we do clock balancing. This method we plan with local skew groups and save
design from unnecessary buffering.

Why NDR is applied on clock net?

Clock nets are very sensitive nets. If clock is being touched and varies in ps as well
then there will be huge violations. Without applying NDR on clock nets, you cant
close the designs.

What is stop pin, Exclude pin & Float pin?

Stop Pin – No buffer/inverter insertion beyond this point (Don’t touch scenario)
Ignore Pin (Float Pins) – No DRV, No Balance
Exclude Pin – DRV Fixing but no balancing
Through Pin – DRV Fixing as well as Balancing

What is the difference between normal buffer and clock buffer?

Clock buffer have equal rise time and fall time; therefore, pulse width violation is
avoided.
Normal buffers may not have equal rise and fall time.
Clock buffers are usually designed such that an input signal with 50% duty cycle
produces an output with 50% duty cycle.

What if timing is met and insertion delay is still more. Is it okay to proceed?
What can be impacted?
If timing is met and still insertion delay is high, this situation leads to too much of
clock tree buffering.
Hence the entire clock tree will consume more power.
To avoid this situation, we use multi point CTS balancing and creates local skew
groups.

Why do we do hold analysis after CTS only?

Before Clock tree synthesis, our clock propagation is ideal and clock tree has not yet
been built.
Once clock tree is built, we can go for hold analysis (Skew is zero till we build CTS.
We’ll discuss more in timing section).
 If there are buffers and inverters present in the library to build clock tree,
which one you will prefer and why?
For clock tree balancing, we need both buffer and inverter. As we know, buffer circuit
is made up of even number of inverters back-to-back, hence by using buffer, we
have more power consumption.

There are two designs, one is having skew zero and another is having some
skew value, then which design you will choose?
I will go for some skew value where clock transition will have some difference which
will help lower IR Drop.

If the design meets timing even if the Insertion Delay is high, what things will
be affected? Whether it is accepted or not?
Still it will affect Power and area. Runtime increases. So we have some insertion
delay target which needs to meet.

What is routing?
Creating physical connections to all the logical connections present in the design
with the help of metal layers is known as routing.

What are the types of routing?

• PG Route: Power/Ground physical routing is completed during floorplan.
Secondary PG routing happens just after STD cell placement.
• Clock Route: Clock physical routing is completed during CTS after clock
buffer insertion.
Signal Route: All the signal routing are completed after all the cells are placed
which is called as routing stage.

What are the pre routing checks?

• All the Physical cells and Standard cells should be placed properly inside the
core area.
• Clock cells should be placed and clock routing should be completed. Clock
NDR should be applied for the required or all clock nets.
• Acceptable congestion, Timing (Setup/Hold), Power and Logical DRCs.
• We should fix all the assign statements where 1’b0 should be connected via
TIE low and similarly 1’b1 should be connected to TIE high cell.
• ATPG and scan coverage should be proper. The entire design should have
testability.
• PDN report (Low Power report) should be clean.
• Logical Equivalence should be clean.
• Max Tran, Max Cap, Max Load etc. violations should not be too high. Marginal
can be handled during routing or ECO stage.

What are the goals of routing?

• Route all the signal nets with minimal physical DRCs.
• Optimize Data path logic for timing, DRCs and Power.
Quality of route in a way, post route CTO is optionally performed.

What are the stages of routing?

• Global Routing
• Track Assignment
• Detail Routing