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FPGA Architecture and Design - SET-2 - Objectives

FPGA Architecture

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P Surendranath
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21 views

FPGA Architecture and Design - SET-2 - Objectives

FPGA Architecture

Uploaded by

P Surendranath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as RTF, PDF, TXT or read online on Scribd
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SET -

02
SUBJECT: FPGA Architecture and Design Max Marks: 10 Duration: 20 Min.
S.No. Question
Multiple Choice Questions
The digital logic family which has minimum power dissipation is: [ ]
A.TTL B.RTL
1) C.DTL D.CMOS L2

Which among the following is a process of transforming RTL to a gate-level [ ]


netlist?
A. Optimization B. Simulation
2) L2
C. synthesis D. Verification

Which model uses transistors as their basic components? [ ]


A. Switch level B. Gate level
3) L3
C. Circuit level D. Layout level

Which phase of ASIC Flow involves converting the RTL design into a gate- [ ]
level representation?
a) Design Specification
4) b) Functional Verification L2
c) Logic Synthesis
d) Physical Design

5) What are the Outputs of AND gate in PLD is said to be _____ [ ]


a. Both input and output same
B. Strobe lines
L2
C. Output lines
D. Input lines

Fill in the blanks

6) _____________phase of ASIC Flow involves converting the gate-level L2


representation into a physical layout?

7) 7.The final output of the Physical Design phase is __________

8) 8.In floor planning, placement and routing are __________ tools.

9) 9.In Verilog HDL, the `always` block is commonly used to describe __________
logic.

10) 10. Logic synthesis optimizes the design for factors such as __________, area,
and power.

True or False Type (Mention “T” or “F”)

Verilog is a programming language used for hardware description. [ ]


11) L2
12) Verilog code describes the behaviour of digital circuits and systems [ ] L3
Verilog can only be used for simulation and cannot be synthesized into actual [ ]
13) hardware. L2

14) Verilog supports both sequential and concurrent programming styles. [ ] L3


[ ]
15) In Verilog, the "always" block is used to describe combinational logic. L2

Match the Following


16 Match the following
)
A. [ ] L2
1. Levels
i. RTL ( ) a. specific physical
component placement.
ii. gate level( ) b. specifics data flow and
operations.
iii. switch level ( ) c. circuits using logic
gates.
iv. layout level ( ) d. consider transistors
and switches.

A) i.b, ii.c, iii.d, iv.a B) i.c, ii.a, iii.b, iv.d


C) i.b, ii.c, iii.a, iv.d D) i.a, ii.b, iii.c, iv.d

17 Match the following


L2
)
B. 2. Abbreviation [ ]
i. ASIC ( ) a. Field programmable gate
array.
ii. HDL ( ) b.Application specific
integrated circuits.
iii. FPGA ( ) c.Complex programmable
logic device.
iv. CPLD ( ) d.Hardware description
language.

A) i.b, ii.c, iii.d, iv.a B) i.c, ii.a, iii.b, iv.d

C)i.b, ii.d, iii.a, iv.c D) i.b, ii.c, iii.a, iv.d

18 Match the following


)
C. [ ] L3
3.ASIC design flow
i. Step-1 ( ) a. RTL synthesis.
ii. Step-2 ( ) b. Chip specification.
iii. Step-3 ( ) c. Design entry/functional
verification.
iv. Step-4 ( ) d. Partitioning of chip.

A) i.b, ii.c, iii.d, iv.a B) i.b, ii.c, iii.a, iv.d


C)i.b, ii.d, iii.a, iv.c D) i.c, ii.a, iii.d, iv.b

19 Match the following


L2
)
4. Verilog constructs [ ]
i. Basic ( ) a.blocking, non blocking
ii. Data types ( ) b.and,or,nand,nor,xor
iii. Premitives ( ) c. identifiers,module,end
module.
D.
iv. Procedural assignments
( )d.wire,wand,tri
A) i.b, ii.c, iii.a, iv.d B) i.b, ii.c, iii.d, iv.a
C) i.a, ii.c, iii.b, iv.d D) i.c, ii.d, iii.b, iv.a

20 Match the following


)
E. [ ] L2
5.IEEE standards for
i.system verilog ( )a.1164
ii.VHDL ( ) b.1368
iii.verilog ( ) c.1800

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