Chapter 4

Combinational Logic
• Combinational Circuits • Magnitude Comparator
• Analysis Procedure • Decoders
• Design Procedure • Encoders
• Binary Adder-Subtractor • Priority Encoder
• Decimal Adder • Multiplexers
• Binary Multiplier
 Combinational Circuits

• Logic circuits for digital system may be combinational

or sequential
– A combinational circuit consists of logic gates whose outputs are a
function of the current inputs
– Sequential circuits
» contains storage elements in addition to logic gates 1
7
» the outputs are a function of the current inputs and 3

the state of the memory (storage) elements

» The state of storage elements, in turn, is a function of
previous inputs so outputs also depend on past inputs
» They have feedback connection
• For n input variables there are 2n possible binary input
combinations
• For each possible input combination there is one
possible output value
• The most important standard combinational circuits
(discussed in this chapter) are adders, subtractors,
comparators, decoders, encoders, and multiplexers
• If the storage registers are included with the
combinational gates then this circuit is considered as
sequential circuit
Analysis Procedure

• The analysis of a combinational circuit requires that

we determine function that the circuit implements
• The first step in analysis procedure is to make sure
that the given circuit is combinational and not
sequential (No feedback path)
• To obtain the output Boolean function from a logic
diagram we proceed as follows
– Label all gate outputs that are a function of input variables with
arbitrary symbols. Determine the Boolean function for each gate
output
– Label the gates that are a function of input variables and previously
labeled gates with other arbitrary symbols. Find the boolean function
of these gates
– Repeat the above process (step 2) until the outputs of the circuit are
obtained
– By repeated substitution of previously defined functions, obtain the
output Boolean functions in terms of input variables
Analysis Procedure-Example
Analysis Procedure-Example

• The circuit has three binary inputs- A,B and C and two
binary outputs- F1 and F2
• The outputs of various gates are labeled with
intermediate symbols
• The output of gates that are a function of input
variables are T1 and T2
• Output F2 can be easily derived from the input
variables
• The boolean function for these three outputs are:
– F2 = AB + AC + BC
– T1 = A + B + C
– T2 = ABC
• Next we consider output of gates that are a function of
already defined symbols
– T3 = F’2T1
– F1 = T3+T2
Analysis Procedure-Example

• To obtain F1 as a function of A,B and C, from a series

of substitutions as follows
F1 = T3+T2
= F2'T1+ABC
=(AB+AC+BC)'(A+B+C)+ABC
=(A'+B')(A'+C')(B'+C')(A+B+C)+ABC
=(A'+B'C')(AB'+AC'+BC'+B'C)+ABC
=A'BC'+A'B'C+AB'C'+ABC
• These functions F1 and F2 implement circuit of a full-
adder. Where:
– F1 is the sum
– F2 is the carry
Derivation of the Truth Table

• The derivation of the truth table for the circuit is a

straight forward process once the output Boolean
functions are known
• To obtain the truth table directly from the logic
diagram without going through the derivations of the
Boolean functions, we proceed as follows:
– Determine the number of input variables in the circuit. For n inputs,
form the 2n possible input combinations and list binary numbers
from 0 to 2n – 1 in a table
– Label the outputs of selected gates with arbitrary symbols
– Obtain the truth table for the outputs of those gates that are a
function of the input variables only
– Proceed to obtain the truth table for the outputs of those gates that
are function of previously defined values until the columns for all
outputs are determined
 Truth Table for Fig 4-2
• F2 equal to 1 for any combination that has 2 or 3 inputs equal to 1
• F2’ is the complement of F2
• T1 and T2 are the OR and AND functions of input variables respectively
• T3 = 1, when T1 and F2’ are equal to 1
• F1 = 1, when either T2 or T3 or both are equal to 1
Design Procedure

• The design procedure of combinational circuits

involves following steps
– State the problem (system spec)
– From the circuit specifications determine the inputs and outputs
– The input and output variables are assigned symbols
– Derive the truth table that gives the relationship between inputs and
outputs
– Derive the simplified Boolean functions (simplify by algebraic
manipulation or K-map method) for each output as a function of
input variables
– Draw the logic diagram and verify the correctness of the design
Code conversion example

• Different digital systems uses different types of codes

• It is sometimes necessary to use the output of one
system as the input to another
• A conversion circuit must be inserted between the two
systems if each uses different codes for the same
information
• A code converter is a circuit that makes the two
systems compatible even though each uses a
different binary code
• To convert from binary code A to binary code B, the
input lines (of combinational circuit) must supply the
bit combination of elements as specified by code A
and the output lines must generate the corresponding
bit combination of code B
Code conversion: BCD to Excess-3 Code

• Each code uses four bits to represent a decimal digit,

there must be four input variables and four output
variables
• Designate the four input binary variables by the
symbols A,B,C,D and the four output variables by w, x,
y and z.
• The truth table relating the input and output variable is
made (shown in next slide)
• Four binary variables have 16 bit combinations but
only 10 are listed in the truth table as 6 bit
combinations not listed are don’t care conditions.
These have no meaning in BCD
Code conversion:Truth Table

Input Output
BCD Excess-3 Code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
K-Maps

• There are four outputs, each as a function of four

input variables.
• There are four maps, each representing one of the
outputs, to obtain simplified Boolean functions.
• The I’s marked inside the square are obtained from
the minterms that makes the output equal to 1
• The I’s are obtained from the truth table by going over
the output columns one at a time.
• The 6 don’t care minterms 10 through 15 are marked
with an X
The Maps
• The simplified functions
– z = D'
– y = CD +C'D‘
– x = B'C + B'D+BC'D'
– w = A+BC+BD
• A two-level logic diagram may be obtained directly
from the above Boolean expressions but there are
various other possibilities for logic diagram that
implements this circuit
• Another implementation
– z = D'
– y = CD +C'D' = CD + (C+D)'
– x = B'C + B'D+BC'D' = B'(C+D) +B(C+D)'
– w = A+BC+BD
• The purpose this manipulation is to use common
gates for two or more outputs
• This is implemented with three levels of gates
• OR gate with output C+D is used to implement
partially each of three outputs
• Implementation with original sum of products require
seven AND gates and three OR gates whereas after
manipulation we require four AND gates and four OR
gates
• In this way the logical circuit has been implemented in
a much economical way.
Logic Diagram
• The logic diagram
 Binary Adder-Subtractor

• Digital computers perform various arithmetic

operations
• The most basic arithmetic operation is the addition of
two binary digits
• When both augend and addend are equal to 1, the
binary sum consists of two digits (1+1=10). The higher
significant bit of this result is called a carry. This carry
is added to the next higher order pair of significant
bits.
• A combinational circuit that performs the addition of
two bits is called a half adder.
 Half Adder

• Half adder adds two binary bits so it requires two

inputs and two outputs
– 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10
• The input variable designate the augend and addend
bit, the output variables produce the sum (S) and
carry (C)
• The truth table for half adder is shown. The C output
is 1 only when both inputs are 1. The S output
represents the least significant bit of the sum
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Half Adder Expressions

• The simplified sum of products expressions are:

– S = x'y+xy'
– C = xy
• It can be implemented in sum of products. It can also
be implemented with an exclusive-OR and an AND
gate
– S=xy
– S = (x+y)(x'+y')
– S' = xy+x'y'
– S' = C+ x'y'
– S = (C+x'y')'
– C = xy
– C = (x'+y')'
Logic Diagram of Half Adder
Full Adder
• A full-adder is a combinational circuit that forms the
arithmetic sum of three bits (three input bits).
– Two of the input variables x, y represents the two significant bits to
be added
– The third input z represents the carry bit from the previous lower
significant position
– Two output bits are necessary designated by the symbol S for sum
and C for carry
• When all input bits are 0, the
x y z c s
output is 0 0 0 0 0 0
0 0 1 0 1
• The S output is equal to 1 when 0 1 0 0 1
only one input is equal to 1 or
0 1 1 1 0
when all three inputs are equal
to 1 1 0 0 0 1
1 0 1 1 0
• The C output has a carry of 1 if 1 1 0 1 0
two or three inputs are equal to 1 1 1 1 1 1
Maps for Full Adder

c
Simplified Expressions for Full Adder

• The simplified expressions for full adder are

– S = x' y' z + x' y z' + x y' z' + x y z
– C = xy + xz + yz
 Full Adder with Two Half Adders
• Full adder can also be implemented with two half adders and
an OR gate. The S output from the second half adder is the
exclusive-OR of z and the output of the first half adder giving
– S = z  (x  y)
= z'(xy'+x'y)+z(xy'+x'y)'
=z'(xy'+x'y)+z(xy+x'y')
= xy'z'+x'yz'+xyz+x'y'z
– C = z(xy'+x'y)+xy C=z(x%y)+xy
= xy'z+x'yz+ xy

Half adder
Binary Adder

• A binary adder is a digital circuit that produces the

arithmetic sum of two binary numbers.
• A binary adder can be implemented using multiple full
adders (FA) connected in cascade with the output
carry from each full adder to the input carry of the
next full adder in the chain
Binary Adder

• The augend bits of A and the addend bits of B are

designated by subscript numbers from right to left,
with subscript 0 denoting the least significant bit
• The carries are connected in a chain through the full
adders
• The S outputs generate the required sum bits
 Binary Adder
• Consider the two binary numbers, A= 1011 and B= 0011
• Their sum S= 1110 is formed with four-bit adders
• The bits are added with full adders, starting from the
least significant position (subscript 0), to form the sum
bit and carry bit
• The input carry C0 in the least significant position must
be 0
• The value of Ci+1 in a significant position is the output
carry of the full adder
• This value is transferred into the
Subscript i 3 2 1 0
input carry of the full adder that Input carry 0 1 1 0 C i

adds the bits one higher significant Augend

Addend
1 0 1 1 A
0 0 1 1 B
i

position to the left Sum 1 1 1 0 S i

Output carry 0 0 1 1 Ci+

1
Binary Adder
• The sum bits are thus generated starting from the
rightmost position and are available as soon as the
corresponding previous carry bit is generated
• All the carries must be generated for the correct sum
bits to appear at the outputs

Subscript i 3 2 1 0
Input carry 0 1 1 0 Ci
Augend 1 0 1 1 Ai
Addend 0 0 1 1 Bi
Sum 1 1 1 0 Si
Output carry 0 0 1 1 Ci+
1
Carry Propagation

• The addition of two binary numbers in parallel implies

that all the bits of the augend and addend are
available for computation at the same time
• In any combinational circuit, the signal must
propagate through the gates before the correct output
is available in the output terminals.
• The Total propagation time = the propagation delay of
a typical gate X the number of gate levels
• The longest propagation delay time in a binary adder
is the time it takes the carry to propagate through the
full adders.
• This is because each bit of the sum output depends
on the value of the input carry. This makes the binary
adder very slow.
Carry Propagation

• Since each bit of the sum output depends on the value

of input carry, the value of Si in any given stage in the
adder will be in its steady state final value only after
the input carry to the stage has been propagated
• Consider output S3 in figure 4-9. Inputs A3 and B3 are
available as soon as input signals are applied to the
adder, however input carry C3 doesn’t settle to its final
value until C2 is available from the previous stage
• Similarly C2 has to wait for C1 and so on down to C0
• In this way only after the carry propagates and ripples
through all stages will the last output S3 and carry C4
settle to their final correct value
Carry Propagation

• The number of gate levels for the carry propagation

can be found from the circuit of the full adder
• The input and output variables use the subscript i to
denote a typical stage in the adder
• The signals at Pi and Gi settle to their steady state
values after they propagate through their respective
gates
 Carry Propagation
• These two signals are common to all full adders and
depend only on the augend and addend bits
• The signal from the input carry Ci to the output carry
Ci+1 propagates through an AND gate and an OR gate,
which constitutes two gate levels
• If there are four full adders in the adder, the output
carry C4 would have 2 x 4 = 8 gate levels from C0 to C4.
• For an n-bit adder, there are 2n gate levels for the
carry to propagate from input to output
• The outputs of a combinational circuit will not be
correct unless the signals are given enough time to
propagate through the gates connected from inputs to
outputs
• All other arithematic operations are implemented by
successive additions, the time consumed during the
addition process is very critical.
Carry Propagation

• One choice to reduce the carry propagation delay is to

employ faster gates but the most widely used
technique for reducing the carry propagation time in
parallel adder is principle of carry lookahead
• Consider the circuit of full adder shown in fig 4-10
• If we define two binary variables
– carry propagate: Pi = AiBi (Term associated with the propagation of
carry from Ci to Ci+1)
– carry generate: Gi = AiBi (Produces 1 when both Ai and Bi are 1)
• Output sum and carry can be expressed as
– sum: Si = PiCi
– carry: Ci+1 = Gi+PiCi
Carry Propagation

• We now write the Boolean functions for the carry

outputs of each stage and substitute for each Ci, its
value from the previous equation
– Co= input carry
– C1 = G0+P0C0
– C2 = G1+P1C1
– = G1+P1(G0+P0C0)
– = G1+P1G0+P1P0C0
– C3 = G2+P2C2
– = G2+P2G1+P2P1G0+ P2P1P0C0
– C4 = G3+P3C3
– =G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0
• Since the Boolean function for each output carry is
expressed in sum of products, each function can be
implemented with one level of AND gates followed by
an OR gate (or by two-level NAND )
Carry Lookahead Generator

• The three Boolean functions for C1, C2 and C3 are

implemented in the carry lookahead generator shown
in figure 4-11
• Here C3 doesn’t have to wait for C2 and C1 to
propagate and C3 is propagated at the same time as C1
and C2
Carry Lookahead Generator
 4-Bit Adder with Carry Lookahead

• The construction of 4-bit adder with a carry lookahead

generator is shown in fig 4-12
• Each sum output requires two exclusive-OR gates.
• The output of first exclusive-OR gate generates the Pi
variable and the AND gate generates the Gi variable
• The carries are propagated through the carry
lookahead generator and applied as inputs to the
second exclusive-OR gate
• All outputs carries are generated after a delay through
two levels of gates
• Outputs S1 through S3 have equal propagation delay
times
4-Bit Adder with Carry Lookahead