Step 1: Verilog Behavioral Models

PC:program counter
module PC(input clk, input reset, input [31:0] nextPC, output reg [31:0] PC);
always @(posedge clk or posedge reset) begin
if (reset)
PC <= 32'b0;
else
PC <= nextPC;
end
endmodule
IM:instruction memory
module InstructionMemory(input [31:0] address, output [31:0] instruction);
reg [31:0] memory [0:127];
initial begin
// Initialize instructions
memory[0] = 32'h00100200; // ADD reg3, reg2, reg1
memory[4] = 32'h00200400; // SHIFT reg6, reg5, reg4
memory[8] = 32'h00300600; // XOR reg9, reg8, reg7
memory[12] = 32'h00400A00; // NOR reg13, reg11, reg10
end
assign instruction = memory[address>>2];
endmodule
Register File:
module RegisterFile(input clk, input [4:0] readAddr1, input [4:0] readAddr2, input
[4:0] writeAddr, input [31:0] writeData, input writeEnable, output [31:0]
readData1, output [31:0] readData2);
reg [31:0] registers [0:31];
initial begin
registers[2] = 60;
registers[5] = 40;
registers[7] = 32'hFFFF856D;
registers[10] = 32'h1FFF756F;
registers[1] = 40;
 registers[4] = 4;
registers[8] = 32'hEEEE3721;
registers[11] = 32'hFFFF765E;
end
assign readData1 = registers[readAddr1];
assign readData2 = registers[readAddr2];
always @(negedge clk) begin
if (writeEnable)
registers[writeAddr] <= writeData;
end
endmodule
ALU:
module ALU(input [31:0] operand1, input [31:0] operand2, input [3:0] aluControl,
output reg [31:0] aluResult);
always @(*) begin
case (aluControl)
4'b0001: aluResult = operand1 + operand2; // ADD
4'b0010: aluResult = operand1 << operand2; // SHIFT (barrel shifter)
4'b0011: aluResult = operand1 ^ operand2; // XOR
4'b0100: aluResult = ~(operand1 | operand2); // NOR
default: aluResult = 32'b0;
endcase
end
endmodule
Step 2: Top Level Structural Model
Top:

module Processor(input clk, input reset);

wire [31:0] pc, nextPC, instruction, readData1, readData2, aluResult;
wire [4:0] writeAddr;
wire [3:0] aluControl;
 // Instantiate components
PC pc_reg (.clk(clk), .reset(reset), .nextPC(nextPC), .PC(pc));
InstructionMemory im (.address(pc), .instruction(instruction));
RegisterFile rf
(.clk(clk), .readAddr1(instruction[25:21]), .readAddr2(instruction[20:16]), .writeAd
dr(writeAddr), .writeData(aluResult), .writeEnable(1'b1), .readData1(readData1), .
readData2(readData2));
ALU alu
(.operand1(readData1), .operand2(readData2), .aluControl(aluControl), .aluResult
(aluResult));
// Add additional logic for control signals, pipeline registers, and nextPC
calculation
Endmodule
Step 3: Initialize Instruction Memory and Registers
Instruction Memory Initialization:
initial begin
memory[0] = 32'h00100200; // ADD reg3, reg2, reg1
memory[4] = 32'h00200400; // SHIFT reg6, reg5, reg4
memory[8] = 32'h00300600; // XOR reg9, reg8, reg7
memory[12] = 32'h00400A00; // NOR reg13, reg11, reg10
end

Register File Initialization:

initial begin
registers[2] = 60;
registers[5] = 40;
registers[7] = 32'hFFFF856D;
registers[10] = 32'h1FFF756F;
registers[1] = 40;
registers[4] = 4;
registers[8] = 32'hEEEE3721;
registers[11] = 32'hFFFF765E;
end
STATEMENT: Given that the sequence of instructions to be executed by the
processor is guaranteed to be free from pipeline hazards, design a 4 – stage
(Instruction Fetch; Decode and read operand; execute; write back) pipelined RISC
processor that can execute following register to – register instructions with a
throughput of one instruction per clock –cycle: ADD , Barrel shifter, XOR, NOR.
The adder and barrel shifter, ALU designed in assignment-1 should be used here.
STEP 0: Draw the detailed architecture level diagram of the processor, naming
and depicting the various architectural blocks (e.g. register file, instruction
memory, ALU, pipeline registers, PC and combinational functional blocks etc).
STEP 1: Create Verilog behavioral models for each of the architectural blocks.
(Register file, Instruction memory, ALU, Pipeline registers, PC etc) STEP 2: Build
the top level structural model of the processor by instantiating and
interconnecting the architectural blocks created in step 1. STEP 3: Initialize the
instruction memory with a program consisting of 4 instructions: 0000 ADD 0004
SHIFT XOR NOR reg3, reg2, reg1 reg6, reg5, reg4 reg9, reg8, reg7 reg 13, reg11,
reg10 Initialize the register file with the following data reg2 = 60 reg5 = 40 reg7
= FFFF856D reg10 = 1FFF756F reg1 = 40 reg4 = 4 reg8 = EEEE3721 reg11 =
FFFF765E Initialize PC with 0000 address. The instruction format is: 31 14 9 4 0
OPCODE Dest. Reg Source Reg.1 Source Reg.2 Opcode ADD 0 --------------- 001
SHIFT 0 ---------------010 XOR 0 ------------------ 011 NOR 0 -------------- 100 The
register file has 32 number of 32 bit registers. All data is unsigned. Assume that
register file has two 32-bit read ports: A and B for data reading and one 32 bit
write port: C for data writing. At the rising edge of the clock the read ports A and
B output the data from the registers whose addresses are present at port A
address and port B address respectively if the enable read port A and enable
read port B signals are true. At the falling edge of a clock, data is written to the
register whose address is present at Port C address if write enable Port C is true.
Design the pipeline registers such that they are latched at the rising edge of the
clock. Specify the size and format of all pipeline registers including the fields
holding the decoded control signals as well as data. The instruction memory is of
size 128 bytes. A read operation from the memory outputs 4 consecutive bytes
of information (starting from the byte address provided to the memory) at the
positive edge of clock if the read enable instruction memory signal is true. Byte
addresses must be aligned and to be provided to memory must be either 0 or
multiples of 4.
Alright, let's break this down step-by-step. Given the complexity of your
assignment, I'll outline the key components and processes involved in designing
and implementing your 4-stage pipelined RISC processor.
Step 0: Architecture Level Diagram
The detailed architecture diagram will include:
1. Instruction Fetch (IF) Stage:
o Program Counter (PC)

o Instruction Memory (IM)

o Pipeline Register (IF/ID)

2. Decode and Read Operand (ID) Stage:

 o Register File

o Control Unit

o Pipeline Register (ID/EX)

3. Execute (EX) Stage:

o Arithmetic Logic Unit (ALU)

o Barrel Shifter

o Pipeline Register (EX/MEM)

4. Write Back (WB) Stage:

o Pipeline Register (MEM/WB)

o Write Back Logic

Step 1: Verilog Behavioral Models

1. Program Counter (PC):
verilog
module PC(input clk, input reset, input [31:0] nextPC, output reg [31:0] PC);
always @(posedge clk or posedge reset) begin
if (reset)
PC <= 32'b0;
else
PC <= nextPC;
end
endmodule
2. Instruction Memory (IM):
verilog
module InstructionMemory(input [31:0] address, output [31:0] instruction);
reg [31:0] memory [0:127];
initial begin
// Initialize instructions
memory[0] = 32'h00100200; // ADD reg3, reg2, reg1
memory[4] = 32'h00200400; // SHIFT reg6, reg5, reg4
memory[8] = 32'h00300600; // XOR reg9, reg8, reg7
memory[12] = 32'h00400A00; // NOR reg13, reg11, reg10
end
 assign instruction = memory[address>>2];
endmodule
3. Register File:
verilog
module RegisterFile(input clk, input [4:0] readAddr1, input [4:0] readAddr2, input
[4:0] writeAddr, input [31:0] writeData, input writeEnable, output [31:0]
readData1, output [31:0] readData2);
reg [31:0] registers [0:31];
initial begin
registers[2] = 60;
registers[5] = 40;
registers[7] = 32'hFFFF856D;
registers[10] = 32'h1FFF756F;
registers[1] = 40;
registers[4] = 4;
registers[8] = 32'hEEEE3721;
registers[11] = 32'hFFFF765E;
end
assign readData1 = registers[readAddr1];
assign readData2 = registers[readAddr2];
always @(negedge clk) begin
if (writeEnable)
registers[writeAddr] <= writeData;
end
endmodule
4. ALU:
verilog
module ALU(input [31:0] operand1, input [31:0] operand2, input [3:0] aluControl,
output reg [31:0] aluResult);
always @(*) begin
case (aluControl)
4'b0001: aluResult = operand1 + operand2; // ADD
4'b0010: aluResult = operand1 << operand2; // SHIFT (barrel shifter)
 4'b0011: aluResult = operand1 ^ operand2; // XOR
4'b0100: aluResult = ~(operand1 | operand2); // NOR
default: aluResult = 32'b0;
endcase
end
endmodule
Step 2: Top Level Structural Model
Integrate the components created above into a single top-level module:
verilog
module Processor(input clk, input reset);
wire [31:0] pc, nextPC, instruction, readData1, readData2, aluResult;
wire [4:0] writeAddr;
wire [3:0] aluControl;

// Instantiate components
PC pc_reg (.clk(clk), .reset(reset), .nextPC(nextPC), .PC(pc));
InstructionMemory im (.address(pc), .instruction(instruction));
RegisterFile rf
(.clk(clk), .readAddr1(instruction[25:21]), .readAddr2(instruction[20:16]), .writeAd
dr(writeAddr), .writeData(aluResult), .writeEnable(1'b1), .readData1(readData1), .
readData2(readData2));
ALU alu
(.operand1(readData1), .operand2(readData2), .aluControl(aluControl), .aluResult
(aluResult));
// Add additional logic for control signals, pipeline registers, and nextPC
calculation
endmodule
Step 3: Initialize Instruction Memory and Registers
 Instruction Memory Initialization:
verilog
initial begin
memory[0] = 32'h00100200; // ADD reg3, reg2, reg1
memory[4] = 32'h00200400; // SHIFT reg6, reg5, reg4
memory[8] = 32'h00300600; // XOR reg9, reg8, reg7
 memory[12] = 32'h00400A00; // NOR reg13, reg11, reg10
end
 Register File Initialization:
verilog
initial begin
registers[2] = 60;
registers[5] = 40;
registers[7] = 32'hFFFF856D;
registers[10] = 32'h1FFF756F;
registers[1] = 40;
registers[4] = 4;
registers[8] = 32'hEEEE3721;
registers[11] = 32'hFFFF765E;
end
Final Steps:
 Connect Pipeline Registers: Add pipeline registers between stages
(IF/ID, ID/EX, EX/MEM, MEM/WB).
 Control Logic: Add control signals to ensure correct operation of
instructions (e.g., enabling read/write ports, selecting ALU operations).
 PC Update Logic: Add logic to update the PC based on instruction flow
(e.g., incrementing PC, handling branches/jumps if any).