Very Low Power CMOS SRAM

1M X 8 bit
Pb-Free and Green package materials are compliant to RoHS BS62LV8001
n FEATURES n DESCRIPTION
Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V The BS62LV8001 is a high performance, very low power CMOS
Ÿ Very low power consumption : Static Random Access Memory organized as 1,048,576 by 8 bits
VCC = 3.0V Operation current : 31mA (Max.) at 55ns and operates form a wide range of 2.4V to 5.5V supply voltage.
2mA (Max.) at 1MHz
O Advanced CMOS technology and circuit techniques provide both
Standby current : 0.8uA (Typ.) at 25 C
high speed and low power features with typical CMOS standby
VCC = 5.0V Operation current : 76mA (Max.) at 55ns O
current of 0.8uA at 3.0V/25 C and maximum access time of 55ns at
10mA (Max.) at 1MHz O
Standby current : 3.5uA (Typ.)
O
at 25 C 3.0V/85 C.
Ÿ High speed access time : Easy memory expansion is provided by an active LOW chip enable
-55 55ns (Max.) at V CC : 3.0~5.5V (CE1), an active HIGH chip enable (CE2), and active LOW output
-70 70ns (Max.) at V CC : 2.7~5.5V enable (OE) and three-state output drivers.
Ÿ Automatic power down when chip is deselected The BS62LV8001 has an automatic power down feature, reducing
Ÿ Easy expansion with CE1, CE2 and OE options the power consumption significantly when chip is deselected.
Ÿ Three state outputs and TTL compatible The BS62LV8001 is available in DICE form, JEDEC standard 44-pin
Ÿ Fully static operation TSOP II and 48-ball BGA package.
Ÿ Data retention supply voltage as low as 1.5V

n POWER CONSUMPTION

POWER DISSIPATION
PRODUCT OPERATING STANDBY Operating
(ICCSB1, Max) (ICC, Max) PKG TYPE
FAMILY TEMPERATURE
VCC=5.0V VCC=3.0V
VCC=5.0V VCC=3.0V
1MHz 10MHz fMax. 1MHz 10MHz fMax.
BS62LV8001DC DICE
Commercial
BS62LV8001EC O O 25uA 4.0uA 9mA 39mA 75mA 1.5mA 19mA 30mA TSOP II-44
+0 C to +70 C
BS62LV8001FC BGA-48-0912
BS62LV8001EI Industrial TSOP II-44
O O 50uA 8.0uA 10mA 40mA 76mA 2mA 20mA 31mA
BS62LV8001FI -40 C to +85 C BGA-48-0912

n PIN CONFIGURATIONS n BLOCK DIAGRAM

A4 1 44 A5
A3 2 43 A6
A2 3 42 A7 A13
A1 4 41 OE
A17
A0 5 40 CE2
CE1 6 39 A8 A15
NC 7 38 NC A18 Address 22 2048 Memory Array
NC 8 37 NC A16
DQ0 9 36 DQ7 A14 Input Row
DQ1 10 35 DQ6 A12 Decoder
VCC 11 BS62LV8001EC 34 VSS Buffer 2048 x 4096
A7
VSS 12 BS62LV8001EI 33 VCC
A6
DQ2 13 32 DQ5
DQ3 14 31 DQ4 A5
NC 15 30 NC A4
NC 16 29 NC
WE 17 28 A9 4096
A19 18 27 A10 DQ0 Data
8
A18 19 26 A11 Input 8 Column I/O
DQ1
A17 20 25 A12 Buffer
A16 21 24 A13 DQ2 Write Driver
A15 22 23 A14 DQ3 Sense Amp
DQ4 8 8
Data
1 2 3 4 5 6 DQ5 512
Output
DQ6 Buffer
A NC OE A0 A1 A2 CE2 DQ7 Column Decoder

B NC NC A3 A4 CE1 NC CE1 18
CE2
Control Address Input Buffer
C DQ0 NC A5 A6 NC DQ4 WE
OE
VCC
D VSS DQ1 A17 A7 DQ5 VCC VSS A11 A9 A8 A3 A2 A1 A0 A10 A19

E VCC DQ2 NC A16 DQ6 VSS

F DQ3 NC A14 A15 NC DQ7

G NC NC A12 A13 WE NC

H A18 A8 A9 A10 A11 A19

48-ball BGA top view

Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.

R0201-BS62LV8001 1 Revision 2.3

May. 2006
 BS62LV8001
n PIN DESCRIPTIONS

Name Function
A0-A19 Address Input These 20 address inputs select one of the 1,048,576 x 8-bit in the RAM

CE1 Chip Enable 1 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
CE2 Chip Enable 2 Input
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output There 8 bi-directional ports are used to read data from or write data into the RAM.

Ports
VCC Power Supply

VSS Ground

n TRUTH TABLE

MODE CE1 CE2 WE OE I/O OPERATION VCC CURRENT

Not selected H X X X
High Z ICCSB, ICCSB1
(Power Down)
X L X X

Output Disabled L H H H High Z ICC

Read L H H L DOUT ICC

Write L H L X DIN ICC

n ABSOLUTE MAXIMUM RATINGS (1) n OPERATING RANGE

AMBIENT
SYMBOL PARAMETER RATING UNITS RANG VCC
TEMPERATURE
Terminal Voltage with (2) O O
VTERM -0.5 to 7.0 V Commercial 0 C to + 70 C 2.4V ~ 5.5V
Respect to GND
Temperature Under O O O
TBIAS -40 to +125 C Industrial -40 C to + 85 C 2.4V ~ 5.5V
Bias
O
TSTG Storage Temperature -60 to +150 C

PT Power Dissipation 1.0 W n CAPACITANCE (1) (T A = 25OC, f = 1.0MHz)

IOUT DC Output Current 20 mA

SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
1. Stresses greater than those listed under ABSOLUTE CIN VIN = 0V 6 pF
Capacitance
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of Input/Output
CIO VI/O = 0V 8 pF
the device at these or any other conditions above those Capacitance
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for 1. This parameter is guaranteed and not 100% tested.
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns.

R0201-BS62LV8001 2 Revision 2.3

May. 2006
 BS62LV8001
n DC ELECTRICAL CHARACTERISTICS (T A =-40OC to +85OC)

PARAMETER
PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS
NAME

VCC Power Supply 2.4 -- 5.5 V

(2)
VIL Input Low Voltage -0.5 -- 0.8 V

(3)
VIH Input High Voltage 2.2 -- VCC+0.3 V

IIL Input Leakage Current VIN = 0V to VCC -- -- 1 uA

VI/O = 0V to VCC,
ILO Output Leakage Current -- -- 1 uA
CE1= V IH or CE2= V IL , or OE = VIH

VOL Output Low Voltage VCC = Max, IOL = 2.0mA -- -- 0.4 V

VOH Output High Voltage VCC = Min, IOH = -1.0mA 2.4 -- -- V

Operating Power Supply CE1 = VIL and CE2 = VIH, VCC=3.0V 31

ICC(5) (4) -- -- mA
Current IDQ = 0mA, f = FMAX VCC=5.0V 76
Operating Power Supply CE1 = VIL and CE2 = VIH, VCC=3.0V 2
ICC1 -- -- mA
Current IDQ = 0mA, f = 1MHz VCC=5.0V 10
CE1 = VIH, or CE2 = VIL, VCC=3.0V 1.0
ICCSB Standby Current – TTL -- -- mA
IDQ = 0mA VCC=5.0V 2.0
CE1≧VCC-0.2V or CE2≦0.2V, VCC=3.0V 0.8 8.0
ICCSB1(6) Standby Current – CMOS -- uA
VIN≧VCC-0.2V or VIN≦0.2V VCC=5.0V 3.5 50

O
1. Typical characteristics are at TA=25 C and not 100% tested. 4. FMAX=1/tRC.
O
2. Undershoot: -1.0V in case of pulse width less than 20 ns. 5. ICC (MAX.) is 30mA/75mA at VCC=3.0V/5.0V and TA=70 C.
O
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 6. ICCSB1(MAX.) is 4.0uA/25uA at VCC=3.0V/5.0V and T A=70 C.

n DATA RETENTION CHARACTERISTICS (T A = -40OC to +85OC)

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS

CE1≧VCC-0.2V or CE2≦0.2V,
VDR VCC for Data Retention 1.5 -- -- V
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
ICCDR(3) Data Retention Current -- 0.4 4.0 uA
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
tCDR 0 -- -- ns
Retention Time
See Retention Waveform
(2)
tR Operation Recovery Time tRC -- -- ns

O
1. VCC=1.5V, TA=25 C and not 100% tested.
2. tRC = Read Cycle Time.
O
3. ICCRD(Max.) is 2.0uA at TA=70 C.

n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)

Data Retention Mode

VDR≧1.5V
VCC VCC VCC
tCDR tR

VIH CE1≧VCC - 0.2V VIH

CE1

R0201-BS62LV8001 3 Revision 2.3

May. 2006
 BS62LV8001
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)

Data Retention Mode

VCC VDR≧1.5V VCC
VCC
tCDR tR

CE2≦0.2V
CE2 VIL VIL

n AC TEST CONDITIONS n KEY TO SWITCHING WAVEFORMS

(Test Load and Input/Output Reference)

WAVEFORM INPUTS OUTPUTS

Input Pulse Levels Vcc / 0V

Input Rise and Fall Times 1V/ns MUST BE MUST BE

STEADY STEADY
Input and Output Timing
0.5Vcc
Reference Level
MAY CHANGE WILL BE CHANGE
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL FROM “H” TO “L” FROM “H” TO “L”
Output Load
Others CL = 30pF+1TTL
MAY CHANGE WILL BE CHANGE
FROM “L” TO “H” FROM “L” TO “H”
ALL INPUT PULSES
1 TTL VCC 90% 90% DON’T CARE
CHANGE :
ANY CHANGE
Output 10% 10% STATE UNKNOW
GND PERMITTED
CL
(1) → ← → ←
Rise Time : Fall Time : CENTER LINE IS
DOES NOT
1V/ns 1V/ns HIGH INPEDANCE
APPLY
“OFF” STATE
1. Including jig and scope capacitance.

n AC ELECTRICAL CHARACTERISTICS (T A = -40OC to +85OC)

READ CYCLE

JEDEC CYCLE TIME : 55ns CYCLE TIME : 70ns

PARANETER
PARAMETER DESCRIPTION (VCC = 3.0~5.5V) (VCC = 2.7~5.5V) UNITS
NAME
NAME MIN. TYP. MAX. MIN. TYP. MAX.
tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns

tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns

tE1LQV tACS1 Chip Select Access Time (CE1) -- -- 55 -- -- 70 ns

tE2HQV tACS2 Chip Select Access Time (CE2) -- -- 55 -- -- 70 ns

tGLQV tOE Output Enable to Output Valid -- -- 25 -- -- 30 ns

tE1LQX tCLZ1 Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns

tE2HQX tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns

tGLQX tOLZ Output Enable to Output Low Z 10 -- -- 10 -- -- ns

tE1HQZ tCHZ1 Chip Select to Output High Z (CE1) -- -- 30 -- -- 35 ns

tE2LQZ tCHZ2 Chip Select to Output High Z (CE2) -- -- 30 -- -- 35 ns

tGHQZ tOHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns

tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns

R0201-BS62LV8001 4 Revision 2.3

May. 2006
 BS62LV8001
n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1 (1,2,4)

tRC

ADDRESS
tAA tOH
tOH

DOUT

READ CYCLE 2 (1,3,4)

CE1

tACS1

CE2
tACS2
(5)
tCHZ1, tCHZ2(5)
tCLZ
DOUT

READ CYCLE 3 (1, 4)

tRC

ADDRESS

tAA

OE
tOH
tOE

CE1 tOLZ

(5)
tACS1 tOHZ(5)
tCLZ1 tCHZ1(1,5)
CE2
tACS2
tCHZ2(1,5)
tCLZ2(5)
DOUT

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.

R0201-BS62LV8001 5 Revision 2.3

May. 2006
 BS62LV8001
n AC ELECTRICAL CHARACTERISTICS (T A = -40OC to +85OC)

WRITE CYCLE

JEDEC CYCLE TIME : 55ns CYCLE TIME : 70ns

PARANETER
PARAMETER DESCRIPTION (VCC = 3.0~5.5V) (VCC = 2.7~5.5V) UNITS
NAME
NAME MIN. TYP. MAX. MIN. TYP. MAX.
tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns

tAVWL tAS Chip Select to End of Write 0 -- -- 0 -- -- ns

tAVWH tAW Address Set up Time 40 -- -- 50 -- -- ns

tE1LWH tCW Address Valid to End of Write 40 -- -- 50 -- -- ns

tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns

tWHAX tWR1 Write Recovery Time (CE1, WE) 0 -- -- 0 -- -- ns

tE2LAX tWR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns

tWLQZ tWHZ Write to Output High Z -- -- 25 -- -- 30 ns

tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns

tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns

tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns

tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns

n SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1 (1)

tWC
ADDRESS

tWR1(3)
OE

tCW(11)
CE1 (5)

CE2 (5)

tCW(11)
tAW tWR2(3)
tWP(2)
WE tAS
tOHZ(4,10)

DOUT
tDH
tDW

DIN

R0201-BS62LV8001 6 Revision 2.3

May. 2006
 BS62LV8001
WRITE CYCLE 2 (1,6)

tWC
ADDRESS

tCW(11)
CE1 (5)

CE2 (5)
(11)
tCW
tAW tWR2(3)
tWP(2)
WE
tAS
tWHZ(4,10) tOW (7) (8)

DOUT
tDW
tDH (8,9)

DIN

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.

R0201-BS62LV8001 7 Revision 2.3

May. 2006
 BS62LV8001
n ORDERING INFORMATION

BS62LV8001 X X Z YY

SPEED
55: 55ns
70: 70ns

PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant

GRADE
o o
C: +0 C ~ +70 C
o o
I: -40 C ~ +85 C

PACKAGE
D: DICE
E: TSOP II-44
F: BGA-48-0912

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.

n PACKAGE DIMENSIONS

TSOP II-44

R0201-BS62LV8001 8 Revision 2.3

May. 2006
 BS62LV8001
n PACKAGE DIMENSIONS (continued)

0.25±0.05
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.2 Max.

SIDE VIEW

D 0.1
N D E D1 E1 e

3.375 D1 48 12.0 9.0 5.25 3.75 0.75

SOLDER BALL 0.35 ±0.05

e

E±0.1
E1
2.625

VIEW A

48 mini-BGA (9mm x 12mm)

R0201-BS62LV8001 9 Revision 2.3

May. 2006
 BS62LV8001
n Revision History

Revision No. History Draft Date Remark

2.2 Add Icc1 characteristic parameter Jan. 13, 2006

Improve Iccsb1 spec.
I-grade from 110uA to 50uA at 5.0V
10uA to 8.0uA at 3.0V
C-grade from 55uA to 25uA at 5.0V
5.0uA to 4.0uA at 3.0V

2.3 Change I-grade operation temperature range May. 25, 2006

- from –25OC to –40OC
Change Iccdr spec.
I-grade from 2.5uA to 4.0uA
C-grade from 1.3uA to 2.0uA
Typical from 0.8 to 0.4uA

R0201-BS62LV8001 10 Revision 2.3

May. 2006