EXPERIMENT -1

AIM-

To give a detailed descrip on of the tanner tools and its working.

TANNER EDA INTRODUCTION CAD-

Computer Aided Design Computer-aided design (CAD) is the use of computers to aid in the crea on,
modifica on, analysis, or op miza on of a design.

CAD so ware is used to increase the produc vity of the designer, improve the quality of design, improve
communica ons through documenta on create a database for manufacturing.

CAD output is o en in the form of electronic files for print, machining or other manufacturing opera ons.

Its use in designing electronic system is known as Electronic Design Automa on EDA.

In mechanical design it is known as mechanical design automa on or computer aided dra ing.

INTRODUCTION TO SPICE-

Simula on program was integrated circuit emphasis.

Developed in 1970s at Berkeley

Many commercial versions are available

SPICE is a robust industry standard

Has many enhancements that we will use.

General purpose, open-source analog electronics circuit simulator

Program used in integrated circuits and board level design because to check integrity of circuit design and to
predict circuit behaviour.

Wri en in FORTRAN for punch-card machine.

Circuit's elements are called cards.

Complete descrip on is called a SPICE deck

VERSION OF SPICE

High level and larger computer

• TSPICE :Student level Tanner EDA

• HSPICE
TANNER EDA DESIGN TOOLS

• S-edit -> A schema c capture tool

• T-spice -> The spice simula on engine integrated with S-edit.

• L-edit - > Physical design tool.

• W-edit - > Waveform forma ng.

S-EDIT

• S-edit is a powerful design capture and entry tool that can generate netlists directly usable in T-spice
simula ons.

• Provides an integrated environment for edi ng circuits, se ng up and running simula ons and probing the
results.

• It also provides the ability to perform SPICE simula on of the circuit.

• These circuits that can be driven forward into a physical layout.

L-EDIT

• L-edit refers to the layout editor

• Flexible to do micromachining design, PCB layout and other CAD work.

• L-edit/DRC – it iden fies any design faults

• L-edit/Extract-generates a circuit “netlist” which is used for SPICE simula on.

W-EDIT

• Not just a waveform viewer but a robust analysis tool.

• Built in measurements like max, min, average etc.

• Easy measurement by selec ng traces and applying op ons.

T-SPICE

• It is a complete design capture and simula on solu on that provides accuracy.

• The role of T-spice is to help design and verify a circuits opera on.

• T-spice simula on results allow circuit designers to verify and fine-tune designs before submi ng them for
fabrica on.

• Performs fast, accurate simula ons for analog and mixed-signal IC design and fully supports foundry
models for reliable and accurate simula ons.

TYPES OF ANALYSIS

• DC opera ng point analysis

• DC transfer analysis

• Transient analysis

• AC analysis
 EXPERIMENT – 2

Aim –

To draw the schema c and waveform of NMOS with double voltage source and to analyze voltage 1.

THEORY-

N type metal oxide semiconductor logic uses n-type MOSFETs to implement logic gates and other digital
circuits. These NMOS transistors operate by crea ng an inversion layer in a p-type transistor body. This
inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals.
The n-channel is created by applying voltage to the third terminal called the gate. Like other MOSFETs, nMOS
transistors have 4 modes of opera on: cut off (or subthreshold), triode, satura on and velocity satura on.

PROCEDURE-

1. Open s-edit then create n new design file.

2. Then add the library files.

3. To open the schema c view, select schema c in view 0 and click OK.

4. Draw the design, check for errors and then save the design.

5. Then generate the net list program of schema c.

6. Then add necessary modelling and input commands to the net-list and then save and run simula on.

7. Output waveforms will be generated in W-edit window

S -Edit Window
 T-Edit Window

********* Top Level*********

.lib “C:\Libraries\Models\Generic_025.lib”TT
MNMOS_1 N_2 N_3 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 N_3 Gnd DC 5
.DC VVoltageSource_2 0 5 1
.print I(MNMOS_1)

********* Simula on Se ngs – Analysis Sec on ********

********* Simula on Se ngs – Addi onal SPICE Commands ********
.end

W-Edit Window

RESULT-

Hence, we have studied the waveforms for CMOS Technology with AC voltage
 EXPERIMENT -3

AIM-

To draw the schema c and waveform of NMOS with single voltage source.

THEORY-

N type metal oxide semiconductor logic uses n-type MOSFETs to implement logic gates and other digital
circuits. These NMOS transistors operate by crea ng an inversion layer in a p-type transistor body. This
inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals.
The n-channel is created by applying voltage to the third terminal called the gate. Like other MOSFETs, nMOS
transistors have 4 modes of opera on: cut off (or subthreshold), triode, satura on and velocity satura on.

PROCEDURE-

1. Open s-edit then create n new design file.

2. Then add the library files.

3. To open the schema c view, select schema c in view 0 and click OK.

4. Draw the design, check for errors and then save the design.

5. Then generate the net list program of schema c.

6. Then add necessary modelling and input commands to the net-list and then save and run simula on.

7. Output waveforms will be generated in W-edit window.

S -Edit Window
T-Edit Window

********* Top Level*********

.lib “C:\Libraries\Models\Generic_025.lib”TT

MNMOS_1 N_2 N_1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_1 N_2 Gnd DC 5

.DC VVoltageSource_1 0 5 0.1

.print I(MNMOS_1)

********* Simulation Settings – Analysis Section ********

********* Simulation Settings – Additional SPICE Commands ********

.end

W-Edit Window

Result: Studied and plo ed the schema c waveform of NMOS with single voltage source.
 EXPERIMENT – 4
AIM:

Draw the schema c and waveform of PMOS with double voltage source.

SOFTWARE USED:

Tanner Tools v13.0

THEORY:

Ptype metal-oxide-semiconductor logic, PMOS or pMOS, in a type of digital circuit constructed using
metaloxide-semiconductor field effect transistors (MOSFET) with a p-type semiconductor source and drain
printed on a bulk n-type "well". When ac vated, by lowering the voltage on the gate, the resul ng circuit
allows the confuc on of electron holes between the source and drain, turning the circuit "on" PMOS circuits
are less suscep ble to electronic noise than other types of MOSFET.

SCHEMATIC PROCEDURE:

1. Open S-Edit then create a new design file.

File New New design and save the file with design name

2. Then add the library files.

Add Documents Tanner EDA Tanner tools v13.0 Libraries All-All tanner

3. To open the schema c view, select schema c in view 0 and then click ok. Cell-New view-Ok

4. Draw the design and then check for errors and then save the design.

5. Then generate the net list program of schema c Tools-T-Spice.

6. Then add the necessary modelling and input commands to the net- list and then save and run simula on.

7. Output waveform will generated in W-Edit.

S-Edit Window
T SPICE PROCEDURE:

1. First, check your design using the pull down menus: Tools - Design Checks (any warnings or errors will be
shown at the bo om)

2. Simulate your design:- Click on the green arrow to start the simulator. The T-Spice window will appear

3. If everything is Ok, the waveform viewer will also appear.

4. View the waveform.

5. If the waveform viewer did NOT automa cally appear, you can click on the file in the T-Spice window and
select "Show waveform"

T-SPICE Window:

********* Top Level*********

.lib “C:\Libraries\Models\Generic_025.lib”TT

MPMOS_1 Gnd N_2 N_3 Gnd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_1 N_1 Gnd DC 5

VVoltageSource_2 N_2 Gnd DC 5

.DC VVoltageSource_2 0 5 0.1

.print I(MPMOS_1)

********* Simula on Se ngs – Analysis Sec on ********

********* Simula on Se ngs – Addi onal SPICE Commands ********

.end
W -Edit Window:

RESULT-

Hence, we have studied the waveforms for PMOS Technology with double voltage source .
 EXPERIMENT – 5

AIM:

To draw the schema c and waveform of PMOS with single source voltage source.

SOFTWARE USED:

Tanner Tools v13.0

THEORY:

P-type metal-oxide-semiconductor logic, PMOS or pMOS, is a type of digital circuit constructed using
metaloxide-semiconductor field effect transistors (MOSFET) with a p-type semiconductor source and drain
printed on a bulk n-type "well". When ac vated, by lowering the voltage on the gate, the resul ng circuit
allows the conduc on of electron holes between the source and drain, turning the circuit "on" PMOS circuits
are less suscep ble to electronic noise than other types of MOSFETs,

SCHEMATIC PROCEDURE:

1. Open S-Edit then create a new design file.

File ->New ->New design and save the file with design name.

2. Then add the library files. Add Documents

Tanner EDA Tanner tools v13.0 Libraries tanner

3. To open the schema c view, select schema c in view 0 and then click ok. Cell→ New view Ok

4. Draw the design and then check for errors and then save the design.

5. Then generate the net list program of schema c.

6. Then add the necessary modelling and input commands to the net- list and then save and run simula on.

Tools T-Spice.

7. Output waveform will generated in W-Edit.

S-SPICE Window:

T -SPICE PROCEDURE:

1. First, check your design using the pull down menus: Tools Design Checks (any warnings or errors will be
shown at the bo om).

2. Simulate your design: Click on the green arrow to start the simulator. The T-Spice window will appear.

3. If everything is Ok, the waveform viewer will also appear.

4. View the waveform.

5. If the waveform viewer did NOT automa cally appear, you can click on the file in the T-Spice window and
select "Show waveform".
T-SPICE WINDOW:

********* Top Level*********

.lib “C:\Libraries\Models\Generic_025.lib”TT
MPMOS_1 Gnd N_2 N_3 Gnd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_1 Gnd DC 5
.DC VVoltageSource_2 0 5 0.1
.print I(MPMOS_1)

********* Simulation Settings – Analysis Section ********

********* Simulation Settings – Additional SPICE Commands ********
.end
W -SPICE Window:

RESULT-

Hence, we have studied the waveforms for PMOS Technology with Single voltage source
 EXPERIMENT – 6

Aim:

To draw the schema c and waveform of a CMOS with a DC voltage source.

Software Used:

Tanner Tools v13.0

Theory:

A CMOS inverter consists of a PMOS and an NMOS transistor. The gate terminals of both transistors are
connected to a common input, VIN, while the output voltage, VOUT, is taken from the drain terminals. The
PMOS transistor's drain terminal is connected to a supply voltage, VDD, while the NMOS source terminal is
connected to ground. The CMOS design does not contain resistors, making it more power-efficient than a
tradi onal resistor-MOSFET inverter. As the input voltage, VIN, varies between 0 and 5 volts, the states of the
NMOS and PMOS transistors change accordingly. If each transistor is viewed as a switch ac vated by VIN, the
opera on of the inverter becomes easily understandable.

Schematic Procedure:

1. Open S-Edit in Tanner Tools v13.0.

Select File -> New -> New to create a new design file.

2. Add Library Files:

Add -> Documents -> Tanner EDA -> Tanner Tools v13.0 -> Libraries -> All Tanner to add the necessary library
files for the design.

3. Open Schema c View:

In the Cell menu, select New View -> Schema c in View 0 -> Ok to open the schema c view.

4. Draw the Design:

Check for any design errors and save the completed schema c.

5. Generate Netlist:

Select Tools -> T-Spice

6. Add the required SPICE models and input commands to the netlist.

And save the netlist and run the simula on.

7. The output waveform will be generated and displayed in W-Edit.

S-Edit Window

T-SPICE Procedure:

1. Go to Tools > Design Checks in the pull-down menu to check for any warnings or errors (displayed at the
bo om).

2. Click on the green arrow to start the simulator. The T-Spice window will appear.

[Link] everything is correct, the waveform viewer will automa cally open.

4. Observe the generated waveform in the waveform viewer.

5. If the waveform viewer does not appear, go to the T-Spice window, select the file, and click Show
waveform.
T-EDIT WINDOW:
********* Top Level*********

.lib “C:\Libraries\Models\Generic_025.lib”TT
MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_1 Out In N_1 N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_1 Gnd DC 5
VVoltageSource_2 In Gnd DC 5
.DC VVoltageSource_2 0 5 0.1
.print V(Cut) V(In)

********* Simula on Se ngs – Analysis Sec on ********

********* Simula on Se ngs – Addi onal SPICE Commands ********
.end
W-Edit Window

RESULT -

Hence, we have studied the waveforms for CMOS Technology with double voltage source

.
 EXPERIMENT – 7
Aim:

To draw the schema c and waveform of a CMOS with a AC voltage source.

Software Used:

Tanner Tools v13.0

Theory:

A CMOS inverter consists of a PMOS and an NMOS transistor connected at their drain and gate terminals. The
PMOS source terminal is connected to a supply voltage, VDD, while the NMOS source terminal is connected
to ground. VIN is applied to the gate terminals, and VOUT is taken from the drain terminals. This design does
not require resistors, making it more power-efficient than a tradi onal resistor-MOSFET inverter. As the input
voltage (VIN) varies between 0 and 5 volts, the states of the NMOS and PMOS transistors change accordingly.
By modelling each transistor as a switch ac vated by VIN, the opera on of the inverter becomes easy to
understand.

Schematic Procedure:

1. Create New Design:

Open S-Edit in Tanner Tools v13.0.

Select File > New > New to create a new design file.

Save the file with a suitable design name.

2. Add Library Files:

Go to Add > Documents > Tanner EDA > Tanner Tools v13.0 > Libraries > All Tanner to add the necessary
library files.

3. Open Schema c View:

In the Cell menu, select New View > Schema c in View 0 > Ok to open the schema c view.

4. Draw the Design:

Using the components from the library, construct the CMOS inverter by connec ng the PMOS and NMOS
transistors, VDD, ground, and input/output ports.

Check for any design errors and save the schema c.

5. Generate Netlist:

Select Tools > T-Spice to generate the netlist for the schema c.

6. Add Modeling and Input Commands:

Include the required SPICE models and input commands in the netlist.

Save the netlist and run the simula on.

7. View Output Waveform:

The output waveform will be generated and displayed in W-Edit.

S -Edit Window

T-SPICE Procedure:

1. Go to Tools > Design Checks to check for any warnings or errors. Any issues will appear at the bo om of
the window.

2. Click the green arrow to start the simulator. The T-Spice window will appear.

3. If everything is correct, the waveform viewer will automa cally open.

4. View the Waveform.

4. If the waveform viewer does not appear automa cally, go to the T-Spice window, select the output file,
and click Show Waveform.

T-Edit Window
********* Top Level*********
.lib “C:\Libraries\Models\Generic_025.lib”
MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource 2 In Gnd DC 0 AC 1 0
.ac dec 10 10Khz 100Khz
.print ac Vdb(Out) Vp(Out) Vn(Out)
********* Simula on Se ngs – Analysis Sec on ********
********* Simula on Se ngs – Addi onal SPICE Commands ********
.end
W-EDIT WINDOW:

RE SULT -

Hence, we have studied the waveforms for CMOS Technology with AC voltage.
 EXPERIMEN – 8
Aim: To draw the schema c and waveform of CMOS with Transient voltage source.

SOFTWARE USED:

Tanner Tools v13.0

THEORY:

A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a
supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal,
were Vin is connected to the gate terminals and VOUT is connected to the drain terminals (See diagram). It is
important to no ce that the CMOS does not contain any resistors, which makes it more power efficient that a
regular resistor-MOSFET inverter. As the voltage at the input of the CMOS device varies between () and 5
volts, the state of the NMOS and PMOS varies accordingly. If we model each transmi er as a simple switch
ac vated by VIN, the inverter's opera ons can be seen very easily.

SCHEMATIC PROCEDURE:

1. Open S-Edit then create a new design file

File ->New ->New design and save the file with design name.

2. Then add the library files.

Add ->Documents -> Tanner EDA ->Tanner tools v13.0 -> Libraries ->All ->All tanner

3. To open the schema c view, select schema c in view 0 and then click ok. Cell -> New view ->Ok

4. Draw the design and then check for errors and then save the design.

5. Then generate the net list program of schema c. Tools -> T-Spice.

6. Then add the necessary modelling and input commands to the net list and then save and run simula on.

7. Output waveform will generated in W-Edit.

S-Edit Window
T-SPICE PROCEDURE:

1. First, check your design using the pull down menus: Tools Design Checks (any warnings or errors will be
shown at the bo om).

2. Simulate your design:- Click on the green arrow to start the simulator. The T-Spice window will appear

3. If everything is Ok, the waveform viewer will also appear.

4. View the waveform

5. If the waveform viewer did NOT automa cally appear, you can click on the file in the T-Spice window and
select "Show waveform".

T-Edit Window :
********* Top Level*********

CCapac tor_1 Out Gnd 1p

MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_2 Vdd Gnd DC 5
VVoltageSource_1 In Gnd BIT((0100101111))
.lib “C:\Libraries\Models\Generic_025.lib”
.tran 1ns 50ns
.print tran V(Out) V(In)

********* Simula on Se ngs – Analysis Sec on ********

********* Simula on Se ngs – Addi onal SPICE Commands ********
.end

W-Edit Window

RESULT-

Hence, we have studied the waveforms for CMOS Technology with Transient voltage.
 EXPERIMENT – 9
Aim:

To draw the schema c and waveform of a NAND gate using CMOS Technology with DC analysis.

SOFTWARE USED:

Tanner Tools v13.0

THEORY:

No ce how transistors Q; and Q resemble the series-connected complementary pair from the inverter circuit.
Both are controlled by the same input signal (input A), the upper transistor turning off and the lower
transistor turning on when the input is "high" (1), and vice versa.

No ce also how transistors Q: and Q are similarly controlled by the same input signal (input By, and how they
will also exhibit the same on/off behavior for the same input logic levels. The upper transistors of both pairs
(Q: and Q:) have their source and drain terminals paralleled, while the lower transistors (Q) and Q4) are
series-connected.

What this means is that the output will go "high" (1) if either top transistor saturates, and will ge "low" (0)
only if both lower transistors saturate.

SCHEMATIC PROCEDURE:

1. Open S-Edit, then create a new design file:

File > New > New Design and save the file with a design name.

2. Add the library files:

Add > Documents > Tanner EDA > Tanner Tools v13.0 > Libraries > All

3. To open the schema c view:

Click New Cell > Select Schema c in View, then click OK.

4. Draw the design schema c, check for errors, and save the design.

5. Generate the netlist and input the necessary commands for modeling and simula on.

6. Run the simula on to generate the output waveform.

S-Edit Window

T-SPICE PROCEDURE:

1. First, check your design using the pull down menus: Tools Design Checks (any warnings or errors will be

shown at the bo om).

2. Simulate your design: Click on the green arrow to start the simulator. The T-Spice window will appear.

3. If everything is Ok, the waveform viewer will also appear.

5. If the waveform viewer did NOT automa cally appear, you can click on the file in the T-Spice window and
select "Show waveform

T-Edit Window:
********* Top Level*********

MNMOS_1 Out a Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Out b Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_1 a N_2 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out b N_1 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 a Gnd DC 5
VVoltageSource_3 b Gnd DC 5
.lib “C:\Libraries\Models\Generic_025.lib”
.print DC V(out)
.DC 1in VVoltageSource_2 0 5 1 VVoltageSource_3 0 5 1

********* Simula on Se ngs – Analysis Sec on ********

********* Simula on Se ngs – Addi onal SPICE Commands ********
.end
W-EDIT WINDOW:

RE SULT -

Hence, we have studied the waveforms for NAND gate CMOS Technology with DC voltage.
 EXPERIMENT – 10
Aim:

To draw the schema c and waveform of a NAND gate using CMOS Technology with transient analysis.

SOFTWARE USED:

Tanner Tools v13.0

THEORY:

No ce how transistors Q and Qs resemble the series-connected complementary pair from the inverter
circuit. Both are controlled by the same input signal (input A), the upper transistor turning off and the lower
transistor turning on when the input is "high" (1), and vice versa.

No ce also how transistors Q and Q are similarly controlled by the same input signal (input B), and how they
will also exhibit the same on/off behavior for the same input logic levels. The upper transistors of both pairs
(Q: and Q2) have their source and drain terminals paralleled, while the lower transistors (Qs and Q4) are
series-connected.

What this means is that the output will go "high" (1) if either top transistor saturates, and will go "low" (0)
only if both lower transistors saturate.

SCHEMATIC PROCEDURE:

1. Open S-Edit then create a new design file.

File -> New -> New design and save the file with design name.

2. Then add the library files. Add Documents Tanner EDA tanner

Tanner tools v13.0 Libraries

3. To open the schema c view, select schema c in view 0 and then click ok. Cell New view Ok

4. Draw the design and then check for errors and then save the design.

5. Then generate the net list program of schema c.

6. Then add the necessary modelling and input commands to the net- list and then save and run simula on.

Tools -> T- Spice.

7. Output waveform will generated in W-Edit.

S-Edit Window:

T-SPICE PROCEDURE:

1. First, check your design using the pull down menus: Tools Design Checks (any warnings or errors will be
shown at the bo om).

2. Simulate your design: Click on the green arrow to start the simulator. The T-Spice window will appear.

3. If everything is Ok, the waveform viewer will also appear.

4. View the waveform.

5. If the waveform viewer did NOT automa cally appear, you can click on the file in the T-Spice window and
select "Show waveform"

T-Edit Window:

********* Top Level*********

MNMOS_1 Out a N_1 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 N_1 b Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out a N_2 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out b N_2 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 a Gnd BIT((0100101111))
VVoltageSource_3 b Gnd BIT((0100101111))
.lib “C:\Libraries\Models\Generic_025.lib”
.tran 1ns 100ns
.print tran V(Out) V(a) V(b)
********* Simula on Se ngs – Analysis Sec on ********
********* Simula on Se ngs – Addi onal SPICE Commands ********
.end

W_EDIT WINDOW:

RE SULT -

Hence, we have studied the waveforms for NAND Gate CMOS Technology with Transient voltage.
 EXPERIMENT – 11
Aim:

To draw the schema c and waveform of a NOR gate using CMOS Technology with transient analysis.

THEORY

The NOR gate is a digital logic gate that implements logical NOR it behaves according to the truth table to the
right. A HIGH output (1) results if both the inputs to the gate are LOW (0), if one or both input is HIGH (1), a
LOW output (0) results. NOR is the result of the nega on of the OR operator. It can also in some senses be
seen as the inverse of an AND gate. NOR is a func onally complete opera on-NOR gates can be combined to
generate any other logical func on. It shares this property with the NAND gate. By contrast, the OR operator
is monotonic as it can only change LOW to HIGH but not vice versa.

In most, but not all, circuit implementa ons, the nega on comes for free including CMOS and TTL.. In such
logic families, OR is the more complicated opera on, it may use a NOR followed by a NOT. A significant
excep on is some forms of the domino logic family.

The original Apollo Guidance Computer used 4,100 integrated circuits (IC), cach one containing only two
3input NOR gates.

SCHEMATIC PROCEDURE:

1. Open S-Edit then create a new design file.

File -> New ->New design and save the file with design name.

2. Then add the library files.

Add -> Documents -> Tanner EDA -> Tanner tools v13.0 -> Libraries -> All->All fanner

[Link] open the schema c view, select schema c in view 0 and then click ok. Cell New ->

view -> OK

4. Draw the design and then check for errors and then save the design. 5. Then generate the net list program
of

6. Then add the necessary modelling and input commands to the net-list and then schema c Tools

→ T-Spice save and run simula on.

7. Output waveform will generated in W-Edit

S-Edit Window:

T-SPICE PROCEDURE:

1. First, check your design using the pull down menus: Tools - Design Checks (any warnings or errors will be

shown at the bo om).

2. Simulate your design: Click on the green arrow to start the simulator. The T-Spice window will appear.

3. If everything is Ok, the waveform viewer will also appear.

4. View the wave form

5. If the waveform viewer did NOT automa cally appear, you can click on the file in the T-Spice window and
select "Show waveform"

T-Edit Window:
********* Top Level*********
MNMOS_1 Out a Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Out b Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_1 a N_2 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out b N_1 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 a Gnd DC 5
VVoltageSource_3 b Gnd DC 5
.lib “C:\Libraries\Models\Generic_025.lib”
.print dc V(out)
.dc 1in VVoltageSource_2 0 5 1 VVoltageSource_3 0 5 1

********* Simula on Se ngs – Analysis Sec on ********

********* Simula on Se ngs – Addi onal SPICE Commands ********
.end
W-EDIT WINDOW:

RE SULT -

Hence, we have studied the waveforms for NOR Gate CMOS Technology with DC voltage.
 EXPERIMENT – 12
Aim:

To draw the schema c and waveform of a NOR gate using CMOS Technology with transient analysis.

SOFTWARE USED:

Tanner Tools v13.0

Theory :

The NOR gate is a digital logic gate that implements logical NOR-it behaves according to the truth table to the
right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a
LOW output (0) results. NOR is the result of the nega on of the OR operator. It can also in some senses be
seen as the inverse of an AND gate NOR is a func onally complete opera on-NOR gates can be combined to
generate any other logical func on. It shares this property with the NAND gate. By contrast, the OR operator
is monotonic as it can only change LOW to HIGH but not vice versa.

In most, but not all, circuit implementa ons, the nega on comes for free- including CMOS and TIL. In such
logic families, OR is the more complicated opera on, it may use a NOR followed by a NOT. A significant
excep on is some forms of the domino logic family

The original Apollo Guidance Computer used 4,100 integrated circuits (IC), each one containing only two
3inpot NOR gates.

SCHEMATIC PROCEDURE:

1. Open S-Edit then create a new design file.

File New New design and save the file with design name Then add the library files.

Add Documents tanner Tanner EDA Tanner tools v13.0 Libraries All All

3. To open the schema c view, select schema c in view 0 and then click ok. Cell New View OL

4. Draw the design and then check for errors and then save the design

5. Then generate the net list program of schema c

6. Then add the necessary modelling and input commands to the net- list and then save
S-Edit Window

T-SPICE PROCEDURE:

1. First, check your design using the pull down menus: Tools Design Checks (any warnings or errors will be
shown at the bo om).

2. Simulate your design: Click on the green arrow to start the simulator. The T-Spice window will appear.

3. If everything is Ok, the waveform viewer will also appear.

4. View the waveform.

5. If the waveform viewer did NOT automa cally appear, you can click on the file in the T-Spice window and
select "Show waveform"

T-Edit Window:
********* Top Level*********

.lib “C:\Libraries\Models\Generic_025.lib”
MNMOS_1 Out a Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Out b Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_1 a N_2 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out b N_1 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 a Gnd BIT ((0100101111))
VVoltageSource_3 b Gnd BIT ((0100101111))
.tran 1ns 100ns
.print tran V(Out) V(a) V(b)

********* Simula on Se ngs – Analysis Sec on ********

********* Simula on Se ngs – Addi onal SPICE Commands ********
.end
W-Edit Window

RE SULT -

Hence, we have studied the waveforms for NOR Gate CMOS Technology with Transient voltage