2077 QUESTION SOLUTION PAPER

DCOM Computer Architecture (II/II)

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1. Define instruction with its format. How can you find direct or indirect
addressing in memory? Describe with suitable diagram.
 A computer instruction is a binary code that specifies a sequence of operation
i.e. an instruction code is a group of bits that instruct the computer to perform a
specific operation. Instruction has 2 parts, first part specifies operation and second
part specifies address where we can find the operand.

When the second part of an instruction code specifies an operand, the instruction is
said to have an immediate operand. When the second part specifies the address of
an operand it is said to have a direct address. When the second part of an
instruction code specifies address of a memory where address of address of an
operand is found, it is called indirect address.
1 bit of instruction code can be used to distinguish between direct and indirect
address. The indirect address instruction needs two references to memory to fetch
an operand.

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2. Illustrate common bus system with diagram in brief.
 A basic computer has 8 registers, memory unit and a control unit. The diagram
of the common bus system is as shown below.

The outputs of all the registers except the OUTR (output register) are
connected to the common bus. The output selected depends upon the binary
value of variables S2, S1 and S0. The lines from common bus are connected
to the inputs of the registers and memory. A register receives the information
from the bus when its LD (load) input is activated while in case of memory
the Write input must be enabled to receive the information. The contents of
memory are placed onto the bus when its Read input is activated.

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3. Define microinstruction with its format. Describe about binary and
symbolic micro program with examples.
 An instruction that controls data flow and instruction-execution sequencing in a
processor at a more fundamental level than machine instructions. Note: A series
of microinstructions is necessary to perform an individual machine instruction.
A microinstruction format includes 20 bits in total. They are divided into four
elements as displayed in the figure.

 F1, F2, F3 are the micro-operation fields. They determine micro-operations

for the computer.
 CD is the condition for branching. They choose the status bit conditions.
 BR is the branch field. It determines the type of branch.
 AD is the address field. It includes the address field whose length is 7 bits.
 The micro-operations are divided into three fields of three bits each. These
three bits can define seven different micro-operations. In total there are 21
operations as displayed in the table.

The symbols defined in microoperation tables can be used to specify

microprogram in a symbolic way. This is called symbolic microprogram.
Symbolic microprogram is translated into its binary equivalent by a
microprogram assembler. Symbols are used in microinstructions as in assembly
language.
The symbolic microprogram is a convenient way for writing
microprograms in a way that people can read and understand, but this is
not the way that the microprogram is stored in memory. The symbolic
microprogram must be translated to binary either by means of an
assembler program or by the user if the microprogram is simple enough. The
equivalent binary form of the microprogram is called binary microprogram.

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4. What do you mean by sub sub-routine?
routine? Differentiate between micro
programmed and hardwired control unit with its major properties.
 A set of instructions that are used repeatedly in a program can be referred to as
Subroutine. Only one copy of this Instruction is stored in the memory. When a
Subroutine
routine is required it can be called many times during the Execution of a
particular program.

For example, the sequence of micro

micro-operations
operations needed to generate the effective
address of the operand for instruction is common to all memory reference
instructions. This sequence could be a subroutine that is called from within many
other routines to execute
ute the effective address computation.

There are two types of control units Hardwired Control unit and Micro-
Micro
programmed control unit.

1. Hardwired control units are generally faster than microprogrammed designs.

In hardwired control, we saw how all the control sig
signals
nals required inside the
CPU can be generated using a state counter and a PLA circuit.

2. A microprogrammed control unit is a relatively simple logic circuit that is

capable of sequencing tthrough microinstructions and generating control
signals to execute
cute each microinstruction.

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 Hardwired Control Unit Microprogrammed Control Unit
 Microprogrammed control unit
 Hardwired control unit generates the
generates the control signals with
control signals needed for the
the help of micro instructions stored
processor using logic circuits
in control memory
 Hardwired control unit is faster when
 This is slower than the other as
compared to microprogrammed control
micro instructions are used for
unit as the required control signals are
generating signals here
generated with the help of hardwares
 Difficult to modify as the control  Easy to modify as the modification
signals that need to be generated are need to be done only at the
hard wired instruction level
 Less costlier than hardwired control
 More costlier as everything has to be
as only micro instructions are used
realized in terms of logic gates
for generating control signals
 It cannot handle complex instructions
as the circuit design for it becomes  It can handle complex instructions
complex
 Only limited number of instructions
 Control signals for many
are used due to the hardware
instructions can be generated
implementation
 Used in computer that makes use of  Used in computer that makes use of
Reduced Instruction Set Complex Instruction Set
Computers(RISC) Computers(CISC)

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5. Define control word. Enlist the various types of addressing mode. Explain
any two of them.
In a control word various control signals are represented by its individual bits. It
is a set of micro-instructions in a micro-routine. It is used in control data register in
any instruction cycle. It consists of:
 branch conditions
 flags
 control signal field
 next microinstruction field
The different ways of specifying the location of an operand in an instruction are
called as addressing modes.
1. Implied Addressing Mode-
In this addressing mode, the definition of the instruction itself specifies the
operands implicitly. It is also called as implicit addressing mode.
Example: The instruction “Complement Accumulator” is an implied mode
instruction.
2. Stack Addressing Mode-
In this addressing mode, the operand is contained at the top of the stack.
Example: ADD
 This instruction simply pops out two symbols contained at the top of the
stack.
 The addition of those two operands is performed.
 The result so obtained after addition is pushed again at the top of the stack.
3. Immediate Addressing Mode-
In this addressing mode, the operand is specified in the instruction
explicitly. Instead of address field, an operand field is present that contains
the operand.
Example: ADI 10H
 M It will increment the value stored in the accumulator by 10.
4. Direct Addressing Mode-
In this addressing mode, the address field of the instruction contains the
effective address of the operand. Only one reference to memory is required
to fetch the operand. It is also called as absolute addressing mode.

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Example: ADD X
 It will increment the value stored in the accumulator by the value stored
at memory location X.
AC ← AC + [X]
5. Indirect Addressing Mode-
In this addressing mode, the address field of the instruction specifies the
address of memory location that contains the effective address of the
operand. Two references to memory are required to fetch the operand.

Example: ADD X
 It will increment the value stored in the accumulator by the value stored
at memory location specified by X.
AC ← AC + [[X]]

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6. Register Direct Addressing Mode-
In this addressing mode, the operand is contained in a register set. The
address field of the instruction refers to a CPU register that contains the
operand. No reference to memory is required to fetch the operand.

Example: ADD R
 It will increment the value stored in the accumulator by the content of
register R.
AC ← AC + [R]
7. Register Indirect Addressing Mode-
In this addressing mode, the address field of the instruction refers to a CPU
register that contains the effective address of the operand. Only one
reference to memory is required to fetch the operand.

Example: ADD R
 It will increment the value stored in the accumulator by the content of
memory location specified in register R.
AC ← AC + [[R]]

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6. Differentiate between RISC and CISC architecture. Write down hardware
algorithm and implementation of addition and subtraction.
 Reduced Instruction Set Architecture (RISC) – The main idea behind this is to
make hardware simpler by using an instruction set composed of a few basic
steps for loading, evaluating, and storing operations just like a load command
will load data, a store command will store the data.
Complex Instruction Set Architecture (CISC) – The main idea is that a single
instruction will do all loading, evaluating, and storing operations just like a
multiplication command will do stuff like loading data, evaluating, and storing
it, hence it’s complex.
Both approaches try to increase the CPU performance
1. RISC: Reduce the cycles per instruction at the cost of the number of
instructions per program.
2. CISC: The CISC approach attempts to minimize the number of instructions
per program but at the cost of an increase in the number of cycles per
instruction.
 RISC  CISC
 Focus on software  Focus on hardware
 Uses both hardwired and
 Uses only Hardwired control unit
microprogrammed control unit
 Transistors are used for storing
 Transistors are used for more
complex
registers
Instructions
 Fixed sized instructions  Variable sized instructions
 Can perform only Register to  Can perform REG to REG or REG
Register Arithmetic operations to MEM or MEM to MEM
 Requires more number of
 Requires less number of registers
registers
 Code size is large  Code size is small
 An instruction executed in a  Instruction takes more than one
single clock cycle clock cycle
 Instructions are larger than the size
 An instruction fit in one word
of one word

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7. Define mapping. Explain any two types of mapping.
 Cache mapping defines how a block from the main memory is mapped to the
cache memory in case of a cache miss. In simple words, cache mapping is a
technique by which the contents of main memory are brought into the cache
memory.
There are three different types of mapping used for the purpose of cache
memory which are as follows: Direct mapping, Associative mapping, and Set-
Associative mapping. These are explained below.
1. Direct Mapping – The simplest technique, known as direct mapping, maps
each block of main memory into only one possible cache line. or
In Direct mapping, assign each memory block to a specific line in the cache. If
a line is previously taken up by a memory block when a new block needs to be
loaded, the old block is trashed. An address space is split into two parts index
field and a tag field. The cache is used to store the tag field whereas the rest is
stored in the main memory. Direct mapping`s performance is directly
proportional to the Hit ratio.
2. Associative Mapping – In this type of mapping, the associative memory is
used to store content and addresses of the memory word. Any block can go into
any line of the cache. This means that the word id bits are used to identify
which word in the block is needed, but the tag becomes all of the remaining
bits. This enables the placement of any word at any place in the cache memory.
It is considered to be the fastest and the most flexible mapping form.
3. Set-associative Mapping – This form of mapping is an enhanced form of direct
mapping where the drawbacks of direct mapping are removed. Set associative
addresses the problem of possible thrashing in the direct mapping method. It
does this by saying that instead of having exactly one line that a block can map
to in the cache; we will group a few lines together creating a set. Then a block
in memory can map to any one of the lines of a specific set..Set-associative
mapping allows that each word that is present in the cache can have two or
more words in the main memory for the same index address. Set associative
cache mapping combines the best of direct and associative cache mapping
techniques. In this case, the cache consists of a number of sets, each of which
consists of a number of lines.

Also draw diagrams provided in class.

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8. What is pipelining? Mention about four segment instruction pipeline.
 Pipelining is a technique where multiple instructions are overlapped during
execution. Pipeline is divided into stages and these stages are connected with
one another to form a pipe like structure. Instructions enter from one end and
exit from another end.
Pipelining increases the overall instruction throughput. In pipeline system, each
segment consists of an input register followed by a combinational circuit. The
register is used to hold data and combinational circuit performs operations on it.
The output of combinational circuit is applied to the input register of the next
segment.
Types of Pipeline
It is divided into 2 categories:
1. Arithmetic Pipeline
2. Instruction Pipeline
Instruction Pipeline: In this a stream of instructions can be executed by
overlapping fetch, decode and execute phases of an instruction cycle. This type
of technique is used to increase the throughput of the computer system.
An instruction pipeline reads instruction from the memory while previous
instructions are being executed in other segments of the pipeline. Thus we can
execute multiple instructions simultaneously.
As the name suggests, four segment pipeline consists of four segments:
Segment 1:
The instruction fetch segment can be implemented using first in, first out
(FIFO) buffer.
Segment 2:
The instruction fetched from memory is decoded in the second segment, and
eventually, the effective address is calculated in a separate arithmetic circuit.
Segment 3:
An operand from memory is fetched in the third segment.
Segment 4:
The instructions are finally executed in the last segment of the pipeline
organization.

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9. Write short notes on :
a) Program Interrupt
Program interrupt can be described as a transfer of program control from a
currently running program to another service program on a request generated
externally or internally. After the service program is executed, the control
returns to the original program.
The interrupt procedure is identical to a subroutine call except for three
variations:
 The interrupt is usually generated by an internal or external signal rather
than from the execution of an instruction (except for software interrupt).
 The address of the interrupt service program is determined by the
hardware rather than from the address field of an instruction.
 An interrupt procedure usually stores all the information necessary to
define the state of the CPU rather than storing only the program counter.
It is imperative for the CPU to return to the same state that it was when
interrupt occurred after the program interrupted and the service routine has
been executed. The state of the CPU at the end of the execute cycle (when
the interrupt is recognized) is determined from:
 The content of the program counter.
 The content of all processor registers.
 The content of certain status conditions.
The collection of all status bit conditions in the CPU is referred as a program
status word or PSW.
b) Characteristics of multiprocessors
A multiprocessor is a single computer that has multiple processors. It is
possible that the processors in the multiprocessor system can communicate
and cooperate at various levels of solving a given problem. The
communications between the processors take place by sending messages
from one processor to another, or by sharing a common memory.
Characteristics of Multiprocessor
There are the major characteristics of multiprocessors are as follows −
 Parallel Computing: This involves the simultaneous application of multiple
processors. These processors are developed using a single architecture to
execute a common task. In general, processors are identical and they work

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 together in such a way that the users are under the impression that they are
the only users of the system. In reality, however, many users are accessing
the system at a given time.
 Distributed Computing: This involves the usage of a network of processors.
Each processor in this network can be considered as a computer in its own
right and have the capability to solve a problem. These processors are
heterogeneous, and generally, one task is allocated to a single processor.
 Supercomputing: This involves the usage of the fastest machines to resolve
big and computationally complex problems. In the past, supercomputing
machines were vector computers but at present, vector or parallel computing
is accepted by most people.
 Pipelining: This is a method wherein a specific task is divided into several
subtasks that must be performed in a sequence. The functional units help in
performing each subtask. The units are attached serially and all the units
work simultaneously.
 Vector Computing: It involves the usage of vector processors, wherein
operations such as ‘multiplication’ are divided into many steps and are then
applied to a stream of operands (“vectors”).
c) Data Dependency
A data dependency occurs when an instruction depends on the results of a
previous instruction. A particular instruction might need data in a register which
has not yet been stored since that is the job of a preceding instruction which has
not yet reached that step in the pipeline. For example:

ADD $R3, $R2, $R1

ADD $R5, $R4, $R3
more instructions that are independent of the first two
In this example, the first instruction tells the processor to add the contents of
registers r1 and r2 and store the result in register r3. The second instructs it to
add r3 and r4 and store the sum in r5. We place this set of instructions in a
pipeline. When the second instruction is in the second stage, the processor will
be attempting to read r3 and r4 from the registers. Remember, though, that the
first instruction is just one step ahead of the second, so the contents of r1 and r2
are being added, but the result has not yet been written into register r3. The
second instruction therefore cannot read from the register r3 because it hasn't

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been written yet and must wait until the data it needs is stored. Consequently,
the pipeline is stalled and a number of empty instructions (known as bubbles go
into the pipeline. Data dependency affects long pipelines more than shorter ones
since it takes a longer period of time for an instruction to reach the final
register-writing
writing stage of a long pipeline.

d) Cache Memory

Cache memory is a small

small-sized
sized type of volatile computer memory that provides
high-speed data accessss to a processor and stores frequently used computer
programs, applications and data.

A temporary storage of memory, cache makes data retrieving easier and more
efficient. It is the fastest memory in a computer, and is typically integrated onto
the motherboard
rboard and directly embedded in the processor or main random access
memory (RAM).

Cache memory is used to reduce the average time to access data from the Main
memory. The cache is a smaller and faster memory which stores copies of the
data from frequently used main memory locations. There are various different
independent caches in a CPU, which store instructions and data.

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