Scribd
Upload
12 views

Unit 1 Part1 Notes

Uploaded by

avpoojitha26
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
12 views

Unit 1 Part1 Notes

Uploaded by

avpoojitha26
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 9

UNIT 1

Combinational and Sequential Logic Circuit Design


Introduction
• Logic circuits may be combinational or sequential.
• A combinational circuit consists of logic gates whose outputs at any time are determined
from only the present combination of inputs. The operation of combinational circuits
can be specified logically by a set of Boolean functions.
• Sequential circuits contain storage elements in addition to logic gates. The outputs of
sequential circuits are a function of the inputs and the state of the storage elements. The
state of the storage elements is a function of previous inputs.
• The outputs of a sequential circuit depend not only on present values of inputs, but also
on past inputs, and the circuit behaviour must be specified by a time sequence of inputs
and internal states.

Design, Analysis and Synthesis of Combinational Circuits:


Combinational Circuits
• A combinational circuit consists of an interconnection of logic gates.
• Combinational circuits react to the values at their inputs and produce the value of the
output signal, transforming binary information from the given input data to a required
output data.
• A block diagram of a combinational circuit is shown.

• The n inputs come


from an external source; the m outputs are produced by the combinational circuit and
go to an external destination.
• Each input and output variable is an analog electrical signal whose values are
interpreted to be a binary signal that represents logic 1 and logic 0.
• Several extensively used combinational circuits, such as adders, subtractors,
multipliers, comparators, decoders, encoders, and multiplexers, are available in
standard integrated circuit components and used as standard cells in complex very large
scale integrated (VLSI) circuits.

Analysis Procedure
• The analysis is to determine the function of an implemented circuit.
• The task starts with a given logic diagram and culminates with a set of Boolean
functions, a truth table, or, possibly, an explanation of the circuit operation.
• The analysis can be performed manually by finding the Boolean functions or truth table
or by using a computer simulation program.
• The first step in the analysis is to make sure that the given circuit is combinational and
not sequential.
• A combinational circuit has no feedback paths or memory elements.
• A feedback path is a connection from the output of one gate to the input of a second
gate whose output forms part of the input to the first gate.
• Feedback paths in a digital circuit define a sequential circuit.

Design Procedure

• The design is to derive a logic circuit or a set of Boolean functions from the
specification of the design objective.
• The design procedure involves the following steps:
• From the specifications of the circuit, determine the required number of inputs and
outputs and assign a symbol to each.
• Derive the truth table that defines the required relationship between inputs and outputs.
• Obtain the simplified Boolean functions for each output as a function of the input
variables.
• Draw the logic diagram and verify the correctness of the design (manually or by
simulation).
ENCODERS
The inverse function of a decoder.
• 2n (or fewer) input lines and n output lines.
• The output lines generate the binary code corresponding to the input value.

8:3 Encoder RTL Code and Testbench:


module encoder8_3(d, x, y, z);
input [7:0] d;
output reg x, y, z;
always @ (*)
begin
case(d)
8’b00000001: {x, y, z} =3’b000;
8’b00000010: {x, y, z} =3’b001;
8’b00000100: {x, y, z} =3’b010;
8’b00001000: {x, y, z} =3’b011;
8’b00010000: {x, y, z} =3’b100;
8’b00100000: {x, y, z} =3’b101;
8’b01000000: {x, y, z} =3’b110;
8’b10000000: {x, y, z} =3’b111;
endcase
end
endmodule

Testbench
module encoder_tb ();
reg [7:0] d;
wire x, y, z;
encoder8_3(d, x, y, z);
initial
begin
d=8’b00000001;
d=8’b00000010;
d=8’b00000100;
d=8’b00001000;
d=8’b00010000;
d=8’b00100000;
d=8’b01000000;
d=8’b10000000;
end
endmodule

PRIORITY ENCODER
Encoder that includes the priority function.
• Resolve the ambiguity of illegal inputs, only one of the inputs is encoded.
• The input having the highest priority will take precedence.

4:2 Priority Encoder


module encoder4_2(d, y);
input [3:0] d;
output reg [1:0] y;
always @(*)
begin
casex(d)
4’b1000: y=2’b00;
4’bx100: y=2’b01;
4’bxx10: y=2’b10;
4’bxxx1: y=2’b11;
endcase
end
endmodule
DECODERS
A decoder converts binary information from n input lines to a maximum of 2n unique output
lines.
A n-to-m decoder (m ≦2n)
– a binary code of n bits has 2n distinct information
– n input variables; up to 2n output lines
– only one output can be active (high) at any time

3:8 Decoder – RTL Code and Testbench


module decoder3_8(d, x, y, z);
input x,y,z;
output reg [7:0] d;
always @ (*)
begin
case({x,y,z})
3’b000: d=8’b00000001;
3’b001: d=8’b00000010;
3’b010: d=8’b00000100;
3’b011: d=8’b00001000;
3’b100: d=8’b00010000;
3’b101: d=8’b00100000;
3’b110: d=8’b01000000;
3’b111: d=8’b10000000;
endcase
end
endmodule

Testbench

module decoder_tb ();


reg x, y, z;
wire [7:0] d;
decoder3_8 n1(d, x, y, z)
initial
begin
#5 x=0; y=0; z=0;
#5 x=0; y=0; z=1;
#5 x=0; y=1; z=0;
#5 x=0; y=1; z=1;
#5 x=1; y=0; z=0;
#5 x=1; y=0; z=1;
#5 x=1; y=1; z=0;
#5 x=1; y=1; z=1;
end
endmodule

2:4 Decoder
module decoder2_4(y,d);
input [1:0]d;
output reg [3:0]y;
always @(*)
begin
case(d)
2’b00: y=4’b0001:
2’b01: y=4’b0010:
2’b10: y=4’b0100:
2’b11: y=4’b1000:
endcase
end
endmodule

MULTIPLEXERS
• Select from one of many inputs and directs it to a single output, controlled by a set of
selection lines.
• A multiplexer is also called a data selector.
• Normally, there are 2n inputs and n selection lines whose bit combinations determine
which input is selected.
4:1 Mux – RTL Code and Testbench
module mux4_1 (y, s1, s0, d);
input [3:0] d;
input s1, s0;
output reg y;
always @ (s1, s0, d)
begin
case ({s1, s0})
2’b00: y=d [0];
2’b01: y=d [1];
2’b10: y=d [2];
2’b11: y=d [3];
endcase
end
endmodule

Testbench
module mux4_1tb ().
reg s1, s0;
reg [3:0] d;
wire y;
mux 4_1 n1(y, s1, s0, d);
initial
begin
#5 $ monitor (“s1=%b s0=%b d=%b y=%b”, s1, s0, d, y);
d=4’b1010;
s1=1’b0; s0=1’b0;
s1=1’b0; s0=1’b1;
s1=1’b1; s0=1’b0;
s1=1’b0; s0=1’b1;
#5 $finish
end
endmodule

1:4 demux-RTL Code and Testbench


module Demux1_4(Y, S, I);
input [1:0] S;
output [3:0] Y;
assign Y0=I & (~S [1]) & (~S [0]);
assign Y1=I & (S [1]) & (~S [0]);
assign Y2=I & (~S [1]) & (~S [0]);
assign Y3=I & (S [1]) & (S [0]);
end
endmodule

Testbench

module Demuxtb;
reg [1:0] S;
reg I;
wire [3:0] Y;
Demux1_4 n1(Y, S, I);
initial
begin
S=2’b00;
I=1’b1;
#5 S=2’b01;
#5 S=2’b10;
#5 S=2’b11;
$monitor (“S=%b,I=%b,Y=%b”,S,I,Y);
end
endmodule

4-bit Comparator

module comp4bit (alb,agb,aeb,a ,b);


input [3:0] a,b;
output reg alb, agb, aeb;
always @ (*)
begin
if (a==b)
aeb=1;
else if(a>b)
agb=1;
else if(a<b)
alb=1;
end
endmodule

Testbench

module comptb;
reg [3:0] a,b;
wire alb, agb, aeb;
comp4bit n1(alb, agb, aeb, a, b);
initial
begin
a = 4'b1010;
b = 4'b0101;
#20 a=4’b0001;
#40 b=4’b0001;
$monitor (“a=%b, b=%b, alb=%b, aeb=%b, agb=%b”a,b,alb, aeb, agb);
end
endmodule

You might also like