A25LS512A Series

512Kbit Low Voltage, Serial Flash Memory

With 100MHz Uniform 4KB Sectors

Document Title
512Kbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors

Revision History

Rev. No. History Issue Date Remark

1.0 Final version release October 16, 2012 Final
1.1 Change 8-pin USON(2*3mm) package outline dimensions November 14, 2014

(November, 2014, Version 1.1) AMIC Technology Corp.

 A25LS512A Series

512Kbit Low Voltage, Serial Flash Memory

With 100MHz Uniform 4KB Sectors

FEATURES
„ Family of Serial Flash Memories „ Electronic Signatures
- A25LS512A: 512K-bit /64K-byte - JEDEC Standard Two-Byte Signature
„ Flexible Sector Architecture with 4KB sectors A25LS512A (3010h)
- Sector Erase (4K-bytes) in 0.2s (typical) - RES Instruction, One-Byte, Signature, for backward
- Block Erase (64K-bytes) in 0.5s (typical) compatibility
„ Page Program (up to 256 Bytes) in 2ms (typical) A25LS512A (05h)
„ 2.7 to 3.6V Single Supply Voltage „ Package options
„ SPI Bus Compatible Serial Interface - 8-pin SOP (150/209mil), 8-pin DIP (300mil), 8-pin TSSOP ,
„ 100MHz Clock Rate (maximum) 8-pin USON (2*3mm) and 8-pin WSON (6*5mm)
- All Pb-free (Lead-free) products are RoHS2.0 compliant

GENERAL DESCRIPTION
The A25LS512A is 512K bit Serial Flash Memory, with Each sector is composed of 16 pages. Each page is 256 bytes
advanced write protection mechanisms, accessed by a high wide. Thus, the whole memory can be viewed as consisting of
speed SPI-compatible bus. 512 pages, or 65,536 bytes.
The memory can be programmed 1 to 256 bytes at a time, The whole memory can be erased using the Chip Erase
using the Page Program instruction. instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
The memory is organized as one block, containing 16 sectors.

Pin Configurations
„ SOP8 Connections „ DIP8 Connections

A25LS512A A25LS512A

S VCC S VCC
1 8 1 8
DO 2 7 HOLD DO 2 7 HOLD
W 3 6 C W 3 6 C
VSS 4 5 DIO VSS 4 5 DIO

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 A25LS512A Series
Pin Configurations (Continued)

„ TSSOP8 Connections „ USON8/WSON8 Connections

A25LS512A A25LS512A

S 1 8 VCC
S 1 8 VCC
DO DO 2 7 HOLD
2 7 HOLD
W 3 6 C
W 3 6 C VSS
VSS 4 5 DIO
4 5 DIO

Block Diagram

HOLD
High Voltage
W Control Logic
Generator
S

DIO
I/O Shift Register
DO

Address register 256 Byte Status

and Counter Data Buffer Register

FFFFh

Size of the
Y Decoder

memory area

00000h 000FFh
256 Byte (Page Size)

X Decoder

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 A25LS512A Series
Pin Descriptions Logic Symbol

Pin No. Description

VCC
C Serial Clock
DIO Serial Data Input 1
DIO DO
DO Serial Data Output 2
C
S Chip Select
S A25LS512A

W Write Protect W

Hold HOLD
HOLD
VCC Supply Voltage
VSS
VSS Ground
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast
Read Dual Input-Output instruction is executed.

SIGNAL DESCRIPTION
Serial Data Output (DO). This output signal is used to Status Register cycle is in progress, the device will be in the
transfer data serially out of the device. Data is shifted out on Standby mode (this is not the Deep Power-down mode).
the falling edge of Serial Clock (C). Driving Chip Select ( S ) Low enables the device, placing it in
The DO pin is also used as an input pin when the Fast Read the active power mode.
Dual Input-Output instruction is executed.
Serial Data Input (DIO). This input signal is used to transfer After Power-up, a falling edge on Chip Select ( S ) is required
data serially into the device. It receives instructions, prior to the start of any instruction.
addresses, and the data to be programmed. Values are Hold ( HOLD ). The Hold ( HOLD ) signal is used to pause
latched on the rising edge of Serial Clock (C). any serial communications with the device without
The DIO pin is also used as an output pin when the Fast deselecting the device.
Read Dual Output instruction and the Fast Read Dual During the Hold condition, the Serial Data Output (DO) is
Input-Output instruction are executed. high impedance, and Serial Data Input (DIO) and Serial
Serial Clock (C). This input signal provides the timing of the Clock (C) are Don’t Care. To start the Hold condition, the
serial interface. Instructions, addresses, or data present at
device must be selected, with Chip Select ( S ) driven Low.
Serial Data Input (DIO) are latched on the rising edge of
Serial Clock (C). Data on Serial Data Output (DO) changes Write Protect ( W ). The main purpose of this input signal is
after the falling edge of Serial Clock (C). to freeze the size of the area of memory that is protected
Chip Select ( S ). When this input signal is High, the device against program or erase instructions (as specified by the
is deselected and Serial Data Output (DO) is at high values in the BP2, BP1, and BP0 bits of the Status Register).
impedance. Unless an internal Program, Erase or Write

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 A25LS512A Series
SPI MODES
These devices can be driven by a microcontroller with its SPI falling edge of Serial Clock (C).
peripheral running in either of the two following modes: The difference between the two modes, as shown in Figure 2,
– CPOL=0, CPHA=0 is the clock polarity when the bus master is in Stand-by mode
– CPOL=1, CPHA=1 and not transferring data:
For these two modes, input data is latched in on the rising – C remains at 0 for (CPOL=0, CPHA=0)
edge of Serial Clock (C), and output data is available from the – C remains at 1 for (CPOL=1, CPHA=1)

Figure 1. Bus Master and Memory Devices on the SPI Bus

SDO
SPI Interface with
(CPOL, CPHA) SDI
= (0, 0) or (1, 1) SCK

C DO DIO C DO DIO C DO DIO

Bus Master
(ST6, ST7, ST9,
ST10, Other)
SPI Memory SPI Memory SPI Memory
Device Device Device
CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.

Figure 2. SPI Modes Supported

CPOL CPHA

0 0 C

1 1 C

DIO MSB

DO MSB

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 A25LS512A Series
OPERATING FEATURES
Page Programming Status Register
To program one data byte, two instructions are required: Write The Status Register contains a number of status and control
Enable (WREN), which is one byte, and a Page Program (PP) bits that can be read or set (as appropriate) by specific
sequence, which consists of four bytes plus data. This is instructions.
followed by the internal Program cycle (of duration tPP). WIP bit. The Write In Progress (WIP) bit indicates whether
To spread this overhead, the Page Program (PP) instruction the memory is busy with a Write Status Register, Program or
allows up to 256 bytes to be programmed at a time (changing Erase cycle.
bits from 1 to 0), provided that they lie in consecutive WEL bit. The Write Enable Latch (WEL) bit indicates the
addresses on the same page of memory. status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits
Sector Erase, Block Erase, and Chip Erase are non-volatile. They define the size of the area to be
The Page Program (PP) instruction allows bits to be reset software protected against Program and Erase instructions.
from 1 to 0. Before this can be applied, the bytes of memory SRWD bit. The Status Register Write Disable (SRWD) bit is
need to have been erased to all 1s (FFh). This can be operated in conjunction with the Write Protect ( W ) signal.
achieved, a sector at a time, using the Sector Erase (SE) The Status Register Write Disable (SRWD) bit and Write
instruction, a block at a time, using the Block Erase (BE) Protect ( W ) signal allow the device to be put in the Hardware
instruction, or throughout the entire memory, using the Chip Protected mode. In this mode, the non-volatile bits of the
Erase (CE) instruction. This starts an internal Erase cycle (of Status Register (SRWD, BP2, BP1, BP0) become read-only
duration tSE, tBE, or tCE). bits.
The Erase instruction must be preceded by a Write Enable
(WREN) instruction. Protection Modes
Polling During a Write, Program or Erase Cycle The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate correctly
A further improvement in the time to Write Status Register in the presence of excessive noise. To help combat this, the
(WRSR), Program (PP) or Erase (SE, BE, or CE) can be A25LS512A boasts the following data protection mechanisms:
achieved by not waiting for the worst case delay (tW, tPP, tSE, „ Power-On Reset and an internal timer (tPUW) can provide
tBE, tCE). The Write In Progress (WIP) bit is provided in the protection against inadvertent changes while the power
Status Register so that the application program can monitor supply is outside the operating specification.
its value, polling it to establish when the previous Write cycle, „ Program, Erase and Write Status Register instructions are
Program cycle or Erase cycle is complete. checked that they consist of a number of clock pulses that
Active Power, Stand-by Power and Deep is a multiple of eight, before they are accepted for
execution.
Power-Down Modes „ All instructions that modify data must be preceded by a
When Chip Select ( S ) is Low, the device is enabled, and in Write Enable (WREN) instruction to set the Write Enable
Latch (WEL) bit. This bit is returned to its reset state by
the Active Power mode.
the following events:
When Chip Select ( S ) is High, the device is disabled, but - Power-up
could remain in the Active Power mode until all internal cycles - Write Disable (WRDI) instruction completion
have completed (Program, Erase, Write Status Register). The - Write Status Register (WRSR) instruction completion
device then goes in to the Stand-by Power mode. The device - Page Program (PP) instruction completion
consumption drops to ICC1. - Sector Erase (SE) instruction completion
The Deep Power-down mode is entered when the specific - Block Erase (BE) instruction completion
instruction (the Deep Power-down Mode (DP) instruction) is - Chip Erase (CE) instruction completion
executed. The device consumption drops further to ICC2. The „ The Block Protect (BP2, BP1, BP0) bits allow part of the
device remains in this mode until another specific instruction memory to be configured as read-only. This is the
(the Release from Deep Power-down Mode and Read Software Protected Mode (SPM).
Electronic Signature (RES) instruction) is executed.
„ The Write Protect ( W ) signal allows the Block Protect
All other instructions are ignored while the device is in the
(BP2, BP1, BP0) bits and Status Register Write Disable
Deep Power-down mode. This can be used as an extra
(SRWD) bit to be protected. This is the Hardware
software protection mechanism, when the device is not in
Protected Mode (HPM).
active use, to protect the device from inadvertent Write,
„ In addition to the low power consumption feature, the
Program or Erase instructions.
Deep Power-down mode offers extra software protection
from inadvertent Write, Program and Erase instructions,
as all instructions are ignored except one particular
instruction (the Release from Deep Power-down
instruction).

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 A25LS512A Series
Table 1. Protected Area Sizes

A25LS512A
Status Register Content Memory Content
BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area
1
X 0 0 None All block
X X 1 All block None
X 1 X All block None
Note: 1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0

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 A25LS512A Series
Hold Condition
The Hold ( HOLD ) signal is used to pause any serial Serial Clock (C) next goes Low. This is shown in Figure 3.
communications with the device without resetting the clocking During the Hold condition, the Serial Data Output (DO) is high
sequence. However, taking this signal Low does not impedance, and Serial Data Input (DIO) and Serial Clock (C)
terminate any Write Status Register, Program or Erase cycle are Don’t Care.
that is currently in progress. Normally, the device is kept selected, with Chip Select ( S )
To enter the Hold condition, the device must be selected, with driven Low, for the whole duration of the Hold condition. This
Chip Select ( S ) Low. is to ensure that the state of the internal logic remains
The Hold condition starts on the falling edge of the Hold unchanged from the moment of entering the Hold condition.
( HOLD ) signal, provided that this coincides with Serial Clock If Chip Select ( S ) goes High while the device is in the Hold
(C) being Low (as shown in Figure 3.). condition, this has the effect of resetting the internal logic of
The Hold condition ends on the rising edge of the Hold the device. To restart communication with the device, it is
( HOLD ) signal, provided that this coincides with Serial Clock necessary to drive Hold ( HOLD ) High, and then to drive
(C) being Low. Chip Select ( S ) Low. This prevents the device from going
If the falling edge does not coincide with Serial Clock (C) back to the Hold condition.
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after

Figure 3. Hold Condition Activation

HOLD

Hold Hold
Condition Condition
(standard use) (non-standard use)

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 A25LS512A Series
MEMORY ORGANIZATION
The memory is organized as: Each page can be individually programmed (bits are
„ 262,144 bytes (8 bits each) programmed from 1 to 0). The device is Sector, Block, or Chip
„ 4 64-Kbytes blocks Erasable (bits are erased from 0 to 1) but not Page Erasable.
„ 64 4-Kbytes sectors
„ 1024 pages (256 bytes each)

Table 2. Memory Organization

A25LS512A Address Table
Block Sector Address Range
15 F000h FFFFh
…

…
3 3000h 3FFFh
0
2 2000h 2FFFh
1 1000h 1FFFh
0 0000h 0FFFh

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 A25LS512A Series
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of sequence is being shifted out.
the device, most significant bit first. In the case of a Page Program (PP), Sector Erase (SE), Block
Serial Data Input (DIO) is sampled on the first rising edge of Erase (BE), Chip Erase (CE), Write Status Register (WRSR),
Serial Clock (C) after Chip Select ( S ) is driven Low. Then, the Write Enable (WREN), Write Disable (WRDI) or Deep
one-byte instruction code must be shifted in to the device, Power-down (DP) instruction, Chip Select ( S ) must be driven
most significant bit first, on Serial Data Input (DIO), each bit High exactly at a byte boundary, otherwise the instruction is
being latched on the rising edges of Serial Clock (C). rejected, and is not executed. That is, Chip Select ( S ) must
The instruction set is listed in Table 3. driven High when the number of clock pulses after Chip Select
Every instruction sequence starts with a one-byte instruction ( S ) being driven Low is an exact multiple of eight.
code. Depending on the instruction, this might be followed by
All attempts to access the memory array during a Write Status
address bytes, or by data bytes, or by both or none.
Register cycle, Program cycle or Erase cycle are ignored, and
In the case of a Read Data Bytes (READ), Read Data Bytes at
the internal Write Status Register cycle, Program cycle or
Higher Speed (Fast_Read), Read Status Register (RDSR) or Erase cycle continues unaffected.
Release from Deep Power-down, Read Device Identification
and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip
Select ( S ) can be driven High after any bit of the data-out

Table 3. Instruction Set

One-byte Address Dummy Data

Instruction Description
Instruction Code Bytes Bytes Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
FAST_READ_DUAL Read Data Bytes at Higher Speed by
00111011 3Bh 3 1 1 to ∞
_OUTPUT Dual Output (1)
FAST_READ_DUAL Read Data Bytes at Higher Speed by
10111011 BBh 3(2) 1(2) 1 to ∞
_INPUT-OUTPUT Dual Input and Dual Output (1)
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 0010 0000 20h 3 0 0
BE Block Erase 1101 1000 D8h 3 0 0
CE Chip Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RDID Read Device Identification 1001 1111 9Fh 0 0 1 to ∞
Read Electronic Manufacturer & Device (3)
REMS 1001 0000 90h 1 2 1 to ∞
Identification
Release from Deep Power-down, and
0 3 1 to ∞
RES Read Electronic Signature 1010 1011 ABh
Release from Deep Power-down 0 0 0

Note: (1) DIO = (D6, D4, D2, D0)

DO = (D7, D5, D3, D1)
(2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0)
DO = (A23, A21, A19, …….., A7, A5, A3, A1)
(3) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first

(November, 2014, Version 1.1) 9 AMIC Technology Corp.

 A25LS512A Series
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4.) sets the The Write Enable (WREN) instruction is entered by driving
Write Enable Latch (WEL) bit. Chip Select ( S ) Low, sending the instruction code, and then
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and driving Chip Select ( S ) High.
Write Status Register (WRSR) instruction.

Figure 4. Write Enable (WREN) Instruction Sequence

0 1 2 3 4 5 6 7
C
Instruction
DIO

High Impedance
DO

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 5.) resets the ﹣ Power-up
﹣ Write Disable (WRDI) instruction completion
Write Enable Latch (WEL) bit. ﹣ Write Status Register (WRSR) instruction completion
The Write Disable (WRDI) instruction is entered by driving Chip ﹣ Page Program (PP) instruction completion
Select ( S ) Low, sending the instruction code, and then driving ﹣ Sector Erase (SE) instruction completion
Chip The Write Enable Latch (WEL) bit is reset under the ﹣ Bulk Erase (BE) instruction completion
following conditions:

Figure 5. Write Disable (WRDI) Instruction Sequence

0 1 2 3 4 5 6 7
C
Instruction
DIO

High Impedance
DO

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 A25LS512A Series

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the WEL bit. The Write Enable Latch (WEL) bit indicates the
Status Register to be read. The Status Register may be read status of the internal Write Enable Latch. When set to 1 the
at any time, even while a Program, Erase or Write Status internal Write Enable Latch is set, when set to 0 the internal
Register cycle is in progress. When one of these cycles is in Write Enable Latch is reset and no Write Status Register,
progress, it is recommended to check the Write In Progress Program or Erase instruction is accepted.
(WIP) bit before sending a new instruction to the device. It is BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits
also possible to read the Status Register continuously, as are non-volatile. They define the size of the area to be
shown in Figure 6. software protected against Program and Erase instructions.
These bits are written with the Write Status Register (WRSR)
Table 4. Status Register Format instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as
b7 b6 b5 b4 b3 b2 b1 b0 defined in Table 1.) becomes protected against Page
SRWD 0 0 BP2 BP1 BP0 WEL WIP Program (PP), Sector Erase (SE), and Block Erase (BE)
instructions. The Block Protect (BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not
Status Register been set. The Chip Erase (CE) instruction is executed if, and
Write Protect only if, all Block Protect (BP2, BP1, BP0) bits are 0.
Block Protect Bits
SRWD bit. The Status Register Write Disable (SRWD) bit is
Write Enable Latch Bit operated in conjunction with the Write Protect ( W ) signal.
The Status Register Write Disable (SRWD) bit and Write
Write In Progress Bit
Protect ( W ) signal allow the device to be put in the
Hardware Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect ( W ) is
The status and control bits of the Status Register are as driven Low). In this mode, the non-volatile bits of the Status
follows: Register (SRWD, BP2, BP1, BP0) become read-only bits and
WIP bit. The Write In Progress (WIP) bit indicates whether the Write Status Register (WRSR) instruction is no longer
the memory is busy with a Write Status Register, Program or accepted for execution.
Erase cycle. When set to 1, such a cycle is in progress, when
reset to 0 no such cycle is in progress.

Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
DIO

Status Register Out Status Register Out

High Impedance
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB

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 A25LS512A Series

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new Write Status Register cycle is in progress, the Status
values to be written to the Status Register. Before it can be Register may still be read to check the value of the Write In
accepted, a Write Enable (WREN) instruction must Progress (WIP) bit. The Write In Progress (WIP) bit is 1
previously have been executed. After the Write Enable during the self-timed Write Status Register cycle, and is 0
(WREN) instruction has been decoded and executed, the when it is completed. When the cycle is completed, the
device sets the Write Enable Latch (WEL). Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction is entered by The Write Status Register (WRSR) instruction allows the
user to change the values of the Block Protect (BP2, BP1,
driving Chip Select ( S ) Low, followed by the instruction
BP0) bits, to define the size of the area that is to be treated
code and the data byte on Serial Data Input (DIO).
as read-only, as defined in Table 1. The Write Status
The instruction sequence is shown in Figure 7. The Write
Register (WRSR) instruction also allows the user to set or
Status Register (WRSR) instruction has no effect on b6, b5,
reset the Status Register Write Disable (SRWD) bit in
b1 and b0 of the Status Register. b6 and b5 are always read
as 0. accordance with the Write Protect ( W ) signal. The Status
Register Write Disable (SRWD) bit and Write Protect ( W )
Chip Select ( S ) must be driven High after the eighth bit of
signal allow the device to be put in the Hardware Protected
the data byte has been latched in. If not, the Write Status
Mode (HPM). The Write Status Register (WRSR) instruction
Register (WRSR) instruction is not executed. As soon as
is not executed once the Hardware Protected Mode (HPM)
Chip Select ( S ) is driven High, the self-timed Write Status is entered.
Register cycle (whose duration is tW) is initiated. While the

Figure 7. Write Status Register (WRSR) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C

Instruction Status
Register In

DIO 7 6 5 4 3 2 1 0

DO High Impedance MSB

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 A25LS512A Series
Table 5. Protection Modes

W SRWD Write Protection of the Status Memory Content

Mode
Signal Bit Register Protected Area
1
Unprotected Area1

1 0 Status Register is Writable (if the

Protected against Page Ready to accept Page
Software WREN instruction has set the WEL
Program, Sector Erase, Program, Sector Erase,
0 0 Protected bit).
Block Erase, and Chip and Block Erase
(SPM) The values in the SRWD, BP2, BP1,
Erase instructions
1 1 and BP0 bits can be changed

Status Register is Hardware write Protected against Page Ready to accept Page
Hardware
protected. Program, Sector Erase, Program, Sector Erase,
0 1 Protected
The values in the SRWD, BP2, BP1, Block Erase, and Chip and Block Erase
(HPM)
and BP0 bits cannot be changed Erase instructions

Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

The protection features of the device are summarized in Table Register are rejected, and are not accepted for execution).
5. As a consequence, all the data bytes in the memory area
When the Status Register Write Disable (SRWD) bit of the that are software protected (SPM) by the Block Protect
Status Register is 0 (its initial delivery state), it is possible to (BP2, BP1, BP0) bits of the Status Register, are also
write to the Status Register provided that the Write Enable hardware protected against data modification.
Latch (WEL) bit has previously been set by a Write Enable Regardless of the order of the two events, the Hardware
(WREN) instruction, regardless of the whether Write Protect Protected Mode (HPM) can be entered:
( W ) is driven High or Low. ­ by setting the Status Register Write Disable (SRWD) bit
When the Status Register Write Disable (SRWD) bit of the after driving Write Protect ( W ) Low
Status Register is set to 1, two cases need to be considered, ­ or by driving Write Protect ( W ) Low after setting the
depending on the state of Write Protect ( W ): Status Register Write Disable (SRWD) bit.
­ If Write Protect ( W ) is driven High, it is possible to write The only way to exit the Hardware Protected Mode (HPM)
to the Status Register provided that the Write Enable once entered is to pull Write Protect ( W ) High.
Latch (WEL) bit has previously been set by a Write If Write Protect ( W ) is permanently tied High, the Hardware
Enable (WREN) instruction. Protected Mode (HPM) can never be activated, and only the
­ If Write Protect (W) is driven Low, it is not possible to Software Protected Mode (SPM), using the Block Protect
write to the Status Register even if the Write Enable Latch (BP2, BP1, BP0) bits of the Status Register, can be used.
(WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status

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 A25LS512A Series
Read Data Bytes (READ)
therefore, be read with a single Read Data Bytes (READ)
The device is first selected by driving Chip Select ( S ) Low.
The instruction code for the Read Data Bytes (READ) instruction. When the highest address is reached, the
instruction is followed by a 3-byte address (A23-A0), each bit address counter rolls over to 000000h, allowing the read
being latched-in during the rising edge of Serial Clock (C). sequence to be continued indefinitely.
Then the memory contents, at that address, is shifted out on The Read Data Bytes (READ) instruction is terminated by
Serial Data Output (DO), each bit being shifted out, at a driving Chip Select ( S ) High. Chip Select ( S ) can be driven
maximum frequency fR, during the falling edge of Serial Clock High at any time during data output. Any Read Data Bytes
(C). (READ) instruction, while an Erase, Program or Write cycle is
The instruction sequence is shown in Figure 8. The first byte in progress, is rejected without having any effects on the
addressed can be at any location. The address is cycle that is in progress.
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,

Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction 24-Bit Address

DIO 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
DO 7 6 5 4 3 2 1 0 7
MSB

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

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 A25LS512A Series
Read Data Bytes at Higher Speed (FAST_READ)
Speed (FAST_READ) instruction. When the highest address
The device is first selected by driving Chip Select ( S ) Low.
is reached, the address counter rolls over to 000000h,
The instruction code for the Read Data Bytes at Higher
allowing the read sequence to be continued indefinitely.
Speed (FAST_READ) instruction is followed by a 3-byte
The Read Data Bytes at Higher Speed (FAST_READ)
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the instruction is terminated by driving Chip Select ( S ) High.
memory contents, at that address, is shifted out on Serial Chip Select ( S ) can be driven High at any time during data
Data Output (DO), each bit being shifted out, at a maximum output. Any Read Data Bytes at Higher Speed (FAST_READ)
frequency fC, during the falling edge of Serial Clock (C). instruction, while an Erase, Program or Write cycle is in
The instruction sequence is shown in Figure 9. The first byte progress, is rejected without having any effects on the cycle
addressed can be at any location. The address is that is in progress.
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher

Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction 24-Bit Address

DIO 23 22 21 3 2 1 0
MSB
High Impedance
DO

S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte

DIO 7 6 5 4 3 2 1 0

Data Out 1 Data Out 2

DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB MSB

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

(November, 2014, Version 1.1) 15 AMIC Technology Corp.

 A25LS512A Series
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the accomplished by adding eight “dummy” clocks after the
Fast_Read (0Bh) instruction except the data is output on two 24-bit address as shown in figure 10. The dummy clocks
pins, DO and DIO, instead of just DO. This allows data to be allow the device’s internal circuits additional time for setting
transferred from the A25LS512A at twice the rate of standard up the initial address. The input data during the dummy
SPI devices. clocks is “don’t care”. However, the DIO pin should be
Similar to the Fast Read instruction, the Fast Read Dual high-impedance prior to the falling edge of the first data out
Output instruction can operate at the highest possible clock.
frequency of fC (See AC Characteristics). This is

Figure 10. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction 24-Bit Address

DIO 23 22 21 3 2 1 0
MSB
High Impedance
DO

S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte DIO switches from input to output

DIO 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

DO 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB MSB MSB
Data Out 1 Data Out 2 Data Out 3 Data Out 4

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

(November, 2014, Version 1.1) 16 AMIC Technology Corp.

 A25LS512A Series
Fast Read Dual Input-Output (BBh)
The Fast Read Dual Input-Output (BBh) instruction is similar accomplished by adding four “dummy” clocks after the 24-bit
to the Fast_Read (0Bh) instruction except the data is input address as shown in figure 11. The dummy clocks allow the
and output on two pins, DO and DIO, instead of just DO. This device’s internal circuits additional time for setting up the
allows data to be transferred from the A25LS512A at twice initial address. The input data during the dummy clocks is
the rate of standard SPI devices. “don’t care”. However, the DIO and DO pins should be
Similar to the Fast Read instruction, the Fast Read Dual high-impedance prior to the falling edge of the first data out
Output instruction can operate at the highest possible clock.
frequency of fC (See AC Characteristics). This is

Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 16 17 18 19
C
Instruction 24-Bit Address

DIO 22 20 18 6 4 2 0
MSB
High Impedance
DO 23 21 19 7 5 3 1

S
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
C
Dummy DIO switches from input to output
Byte

DIO 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

DO 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB MSB MSB MSB
Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

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 A25LS512A Series
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed correctly within the same page. If less than 256
programmed in the memory (changing bits from 1 to 0). Data bytes are sent to device, they are correctly programmed
Before it can be accepted, a Write Enable (WREN) instruction at the requested addresses without having any effects on the
must previously have been executed. After the Write Enable other bytes of the same page.
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL). Chip Select ( S ) must be driven High after the eighth bit of the
last data byte has been latched in, otherwise the Page
The Page Program (PP) instruction is entered by driving Chip Program (PP) instruction is not executed.
Select ( S ) Low, followed by the instruction code, three
address bytes and at least one data byte on Serial Data Input As soon as Chip Select ( S ) is driven High, the self-timed
(DIO). If the 8 least significant address bits (A7-A0) are not all Page Program cycle (whose duration is tPP) is initiated. While
zero, all transmitted data that goes beyond the end of the the Page Program cycle is in progress, the Status Register
current page are programmed from the start address of the may be read to check the value of the Write In Progress (WIP)
same page (from the address whose 8 least significant bits bit. The Write In Progress (WIP) bit is 1 during the self-timed
Page Program cycle, and is 0 when it is completed. At some
(A7-A0) are all zero). Chip Select ( S ) must be driven Low for unspecified time before the cycle is completed, the Write
the entire duration of the sequence. Enable Latch (WEL) bit is reset.
The instruction sequence is shown in Figure 12. If more than A Page Program (PP) instruction applied to a page which is
256 bytes are sent to the device, previously latched data are protected by the Block Protect (BP2, BP1, BP0) bits (see
discarded and the last 256 data bytes are guaranteed to be table 1and table 2.) is not executed.

Figure 12. Page Program (PP) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C

Instruction 24-Bit Address Data Byte 1

DIO 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

S
2072
2073
2074
2075
2076
2077
2078
2079

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C

Data Byte 2 Data Byte 3 Data Byte 256

DIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

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 A25LS512A Series
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits
instruction is not executed. As soon as Chip Select ( S ) is
inside the chosen sector. Before it can be accepted, a Write
driven High, the self-timed Sector Erase cycle (whose
Enable (WREN) instruction must previously have been ex-
duration is tSE) is initiated. While the Sector Erase cycle is in
ecuted. After the Write Enable (WREN) instruction has been
progress, the Status Register may be read to check the value
decoded, the device sets the Write Enable Latch (WEL).
of the Write In Progress (WIP) bit. The Write In Progress
The Sector Erase (SE) instruction is entered by driving Chip
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
Select ( S ) Low, followed by the instruction code on Serial 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
Data Input (DIO). Chip Select ( S ) must be driven Low for the
A Sector Erase (SE) instruction applied to a page which is
entire duration of the sequence.
protected by the Block Protect (BP2, BP1, BP0) bits (see
The instruction sequence is shown in Figure 13. Chip Select
table 1and table 2.) is not executed.
( S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase

Figure 13. Sector Erase (SE) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction 24-Bit Address

DIO 23 22 21 3 2 1 0
MSB

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

(November, 2014, Version 1.1) 19 AMIC Technology Corp.

 A25LS512A Series
Block Erase (BE)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside
instruction is not executed. As soon as Chip Select ( S ) is
the chosen block. Before it can be accepted, a Write Enable
driven High, the self-timed Block Erase cycle (whose duration
(WREN) instruction must previously have been executed.
is tBE) is initiated. While the Block Erase cycle is in progress,
After the Write Enable (WREN) instruction has been decoded,
the Status Register may be read to check the value of the
the device sets the Write Enable Latch (WEL).
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
The Block Erase (BE) instruction is entered by driving Chip
is 1 during the self-timed Block Erase cycle, and is 0 when it
Select ( S ) Low, followed by the instruction code on Serial is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
Data Input (DIO). Chip Select ( S ) must be driven Low for the
A Block Erase (BE) instruction applied to a page which is
entire duration of the sequence.
protected by the Block Protect (BP2, BP1, BP0) bits (see
The instruction sequence is shown in Figure 14. Chip Select
table 1and table 2.) is not executed.
( S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Block Erase

Figure 14. Block Erase (BE) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction 24-Bit Address

DIO 23 22 21 3 2 1 0
MSB

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

(November, 2014, Version 1.1) 20 AMIC Technology Corp.

 A25LS512A Series
Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before
is not executed. As soon as Chip Select ( S ) is driven High,
it can be accepted, a Write Enable (WREN) instruction must
the self-timed Chip Erase cycle (whose duration is tCE) is
previously have been executed. After the Write Enable
initiated. While the Chip Erase cycle is in progress, the Status
(WREN) instruction has been decoded, the device sets the
Register may be read to check the value of the Write In
Write Enable Latch (WEL).
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
The Chip Erase (CE) instruction is entered by driving Chip
the self-timed Chip Erase cycle, and is 0 when it is completed.
Select ( S ) Low, followed by the instruction code on Serial At some unspecified time before the cycle is completed, the
Write Enable Latch (WEL) bit is reset.
Data Input (DIO). Chip Select ( S ) must be driven Low for the
The Chip Erase (CE) instruction is executed only if all Block
entire duration of the sequence.
Protect (BP2, BP1, BP0) bits are 0. The Chip Erase (CE)
The instruction sequence is shown in Figure 15. Chip Select
instruction is ignored if one, or more, blocks are protected.
( S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Bulk Erase instruction

Figure 15. Chip Erase (CE) Instruction Sequence

0 1 2 3 4 5 6 7
C

Instruction
DIO

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 A25LS512A Series

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only The Deep Power-down mode automatically stops at
way to put the device in the lowest consumption mode (the Power-down, and the device always Powers-up in the
Deep Power-down mode). It can also be used as an extra Standby mode.
software protection mechanism, while the device is not in The Deep Power-down (DP) instruction is entered by driving
active use, since in this mode, the device ignores all Write,
Chip Select ( S ) Low, followed by the instruction code on
Program and Erase instructions.
Serial Data Input (DIO). Chip Select ( S ) must be driven Low
Driving Chip Select ( S ) High deselects the device, and puts for the entire duration of the sequence. The instruction
the device in the Standby mode (if there is no internal cycle sequence is shown in Figure 16.
currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be Chip Select ( S ) must be driven High after the eighth bit of the
entered by executing the Deep Power-down (DP) instruction, instruction code has been latched in, otherwise the Deep
to reduce the standby current (from ICC1 to ICC2, as specified in Power-down (DP) instruction is not executed. As soon as
DC Characteristics Table.). Chip Select ( S ) is driven High, it requires a delay of tDP
Once the device has entered the Deep Power-down mode, all before the supply current is reduced to ICC2 and the Deep
instructions are ignored except the Release from Deep Power-down mode is entered.
Power-down and Read Electronic Signature (RES) instruction. Any Deep Power-down (DP) instruction, while an Erase,
This releases the device from this mode. The Release from Program or Write cycle is in progress, is rejected without
Deep Power-down and Read Electronic Signature (RES) having any effects on the cycle that is in progress.
instruction also allows the Electronic Signature of the device
to be output on Serial Data Output (DO).

Figure 16. Deep Power-down (DP) Instruction Sequence

S
tDP
0 1 2 3 4 5 6 7
C

Instruction
DIO

Stand-by Mode Deep Power-down Mode

(November, 2014, Version 1.1) 22 AMIC Technology Corp.

 A25LS512A Series

Read Device Identification (RDID)

The Read Identification (RDID) instruction allows the 8-bit This is followed by the 24-bit device identification, stored in
manufacturer identification code to be read, followed by two the memory, being shifted out on Serial Data Output (DO),
bytes of device identification. The manufacturer identification each bit being shifted out during the falling edge of Serial
is assigned by JEDEC, and has the value 37h. The device Clock (C).
identification is assigned by the device manufacturer, and The instruction sequence is shown in Figure 17. The Read
indicates the memory in the first bytes (30h), and the memory Identification (RDID) instruction is terminated by driving Chip
capacity of the device in the second byte.
Any Read Identification (RDID) instruction while an Erase, or Select ( S ) High at any time during data output.
Program cycle is in progress, is not decoded, and has no
When Chip Select ( S ) is driven High, the device is put in the
effect on the cycle that is in progress.
Stand-by Power mode. Once in the Stand-by Power mode,
The device is first selected by driving Chip Select ( S ) Low. the device waits to be selected, so that it can receive, decode
Then, the 8-bit instruction code for the instruction is shifted in. and execute instructions.

Table 6. Read Identification (READ_ID) Data-Out Sequence

Manufacture Identification Device Identification

Manufacture ID Memory Type Memory Capacity
C2h 20h 10h

Figure 17. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 21 22 23 24 25 26 29 30 31

C
Instruction

DIO

DO 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0
High Impedance
Manufacture ID Memory Type Memory Capacity

(November, 2014, Version 1.1) 23 AMIC Technology Corp.

 A25LS512A Series
Read Electronic Manufacturer ID & Device ID (REMS)
The Read Electronic Manufacturer ID & Device ID (REMS) If the one-byte address is set to 01h, then the device ID will
instruction allows the 8-bit manufacturer identification code to be read first and then followed by the Manufacturer ID. On
be read, followed by one byte of device identification. The the other hand, if the one-byte address is set to 00h, then the
manufacturer identification is assigned by JEDEC, and has Manufacturer ID will be read first and then followed by the
the value 37h for AMIC. The device identification is assigned device ID.
by the device manufacturer. The instruction sequence is shown in Figure 18. The Read
Any Read Electronic Manufacturer ID & Device ID (REMS) Electronic Manufacturer ID & Device ID (REMS) instruction is
instruction while an Erase, or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in terminated by driving Chip Select ( S ) High at any time during
progress. data output.
When Chip Select ( S ) is driven High, the device is put in the
The device is first selected by driving Chip Select ( S ) Low. Stand-by Power mode. Once in the Stand-by Power mode,
The 8-bit instruction code is followed by 2 dummy bytes and the device waits to be selected, so that it can receive, decode
one byte address (A7~A0), each bit being latched-in on Serial and execute instructions.
Data Input (DIO) during the rising edge of Serial Clock (C).

Table 7. Read Electronic Manufacturer ID & Device ID (REMS) Data-Out Sequence

Manufacture Identification Device Identification

C2h 05h

Figure 18. Read Electronic Manufacturer ID & Device ID (REMS) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
C
Instruction 2 Dummy Bytes

DIO 15 14 13 3 2 1 0
MSB
High Impedance
DO

S
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
ADD(1)

DIO 7 6 5 4 3 2 1 0

Manufacturer ID Device ID
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB
Notes:
(1) ADD=00h will output the manufacturer ID first and ADD=01h will output device ID first

(November, 2014, Version 1.1) 24 AMIC Technology Corp.

 A25LS512A Series
Release from Deep Power-down and Read edge of Serial Clock (C). Then, the 8-bit Electronic Signature,
Electronic Signature (RES) stored in the memory, is shifted out on Serial Data Output
(DO), each bit being shifted out during the falling edge of
Once the device has entered the Deep Power-down mode,
Serial Clock (C).
all instructions are ignored except the Release from Deep
The instruction sequence is shown in Figure 19.
Power-down and Read Electronic Signature (RES)
The Release from Deep Power-down and Read Electronic
instruction. Executing this instruction takes the device out of
Signature (RES) instruction is terminated by driving Chip
the Deep Power-down mode.
The instruction can also be used to read, on Serial Data Select ( S ) High after the Electronic Signature has been read
Output (DO), the 8-bit Electronic Signature as shown below. at least once. Sending additional clock cycles on Serial Clock
Except while an Erase, Program or Write Status Register (C), while Chip Select ( S ) is driven Low, cause the
cycle is in progress, the Release from Deep Power-down and Electronic Signature to be output repeatedly.
Read Electronic Signature (RES) instruction always provides
When Chip Select ( S ) is driven High, the device is put in the
access to the 8-bit Electronic Signature of the device, and
Stand-by Power mode. If the device was not previously in the
can be applied even if the Deep Power-down mode has not
Deep Power-down mode, the transition to the Stand-by
been entered.
Power mode is immediate. If the device was previously in the
Any Release from Deep Power-down and Read Electronic Deep Power-down mode, though, the transition to the Stand-
Signature (RES) instruction while an Erase, Program or Write
Status Register cycle is in progress, is not decoded, and has by Power mode is delayed by tRES2, and Chip Select ( S )
no effect on the cycle that is in progress. must remain High for at least tRES2 (max), as specified in AC
Characteristics Table . Once in the Stand-by Power mode,
The device is first selected by driving Chip Select ( S ) Low. the device waits to be selected, so that it can receive, decode
The instruction code is followed by 3 dummy bytes, each bit and execute instructions.
being latched-in on Serial Data Input (DIO) during the rising

Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
C
Instruction 3 Dummy Bytes tRES2

DIO 23 22 21 3 2 1 0
MSB
High Impedance
DO 7 6 5 4 3 2 1 0
MSB

Deep Power-down Mode Stand-by Mode

Note: The value of the 8-bit Electronic Signature, for the A25LS512A is 05h.

(November, 2014, Version 1.1) 25 AMIC Technology Corp.

 A25LS512A Series
Figure 20. Release from Deep Power-down (RES) Instruction Sequence

tRES1
0 1 2 3 4 5 6 7
C

Instruction
DIO

High Impedance
DO

Deep Power-down Mode Stand-by Mode

previously in the Deep Power-down mode, though, the

Driving Chip Select ( S ) High after the 8-bit instruction byte
transition to the Stand-by Power mode is delayed by tRES1,
has been received by the device, but before the whole of the
8-bit Electronic Signature has been transmitted for the first and Chip Select ( S ) must remain High for at least tRES1 (max),
time (as shown in Figure 20.), still insures that the device is as specified in AC Characteristics Table. Once in the
put into Stand-by Power mode. If the device was not pre- Stand-by Power mode, the device waits to be selected, so
viously in the Deep Power-down mode, the transition to the that it can receive, decode and execute instructions.
Stand-by Power mode is immediate. If the device was

(November, 2014, Version 1.1) 26 AMIC Technology Corp.

 A25LS512A Series
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be ­ tPUW after VCC passed the VWI threshold
- tVSL afterVCC passed the VCC(min) level
selected (that is Chip Select ( S ) must follow the voltage
These values are specified in Table 8.
applied on VCC) until VCC reaches the correct value:
If the delay, tVSL, has elapsed, after VCC has risen above
­ VCC (min) at Power-up, and then for a further delay of tVSL VCC(min), the device can be selected for Read instructions
­ VSS at Power-down even if the tPUW delay is not yet fully elapsed.
Usually a simple pull-up resistor on Chip Select ( S ) can be At Power-up, the device is in the following state:
used to insure safe and proper Power-up and Power-down. ­ The device is in the Standby mode (not the Deep
To avoid data corruption and inadvertent write operations Power-down mode).
during power up, a Power On Reset (POR) circuit is included. ­ The Write Enable Latch (WEL) bit is reset.
The logic inside the device is held reset while VCC is less than Normal precautions must be taken for supply rail decoupling,
the POR threshold value, VWI – all operations are disabled, to stabilize the VCC feed. Each device in a system should
and the device does not respond to any instruction. have the VCC rail decoupled by a suitable capacitor close to
Moreover, the device ignores all Write Enable (WREN), Page the package pins. (Generally, this capacitor is of the order of
Program (PP), Sector Erase (SE), Block Erase (BE), Chip 0.1µF).
Erase (CE) and Write Status Register (WRSR) instructions At Power-down, when VCC drops from the operating voltage,
until a time delay of tPUW has elapsed after the moment that to below the POR threshold value, VWI, all operations are
VCC rises above the VWI threshold. However, the correct disabled and the device does not respond to any instruction.
operation of the device is not guaranteed if, by this time, VCC (The designer needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in progress, some
is still below VCC(min). No Write Status Register, Program or
data corruption can result.)
Erase instructions should be sent until the later of:

Figure 21. Power-up Timing

VCC

VCC(max)

VCC(min)

Reset tVSL Read Full Device Access

State Access
allowed
VWI

tPUW

time

(November, 2014, Version 1.1) 27 AMIC Technology Corp.

 A25LS512A Series
Table 8. Power-Up Timing

Symbol Parameter Min. Max. Unit

tVSL VCC(min) to S Low 10 μs

tPUW Time Delay Before Write Instruction 3 ms

VWI Write Inhibit Threshold Voltage 2.3 2.5 V

Note: These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains
00h (all Status Register bits are 0).

(November, 2014, Version 1.1) 28 AMIC Technology Corp.

 A25LS512A Series
Absolute Maximum Ratings* *Comments
Storage Temperature (TSTG) . . . . . . . . . . -65°C to + 150°C Stressing the device above the rating listed in the Absolute
Lead Temperature during Soldering (Note 1) Maximum Ratings" table may cause permanent damage to
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . the device. These are stress ratings only and operation of
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC+0.6V the device at these or any other conditions above those
Transient Voltage (<20ns) on Any Pin to Ground Potential . . indicated in the Operating sections of this specification is not
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VCC+2.0V implied. Exposure to Absolute Maximum Rating conditions
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . -0.6V to +4.0V for extended periods may affect device reliability. Refer also
Electrostatic Discharge Voltage (Human Body model) to the AMIC SURE Program and other relevant quality docu-
(VESD) (Note 2) . . . . . . . . . . . . . . . . . . . -2000V to 2000V ments.

Notes:
1. Compliant with JEDEC Std J-STD-020B (for small body,
Sn-Pb or Pb assembly).
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω ,
R2=500Ω)

DC AND AC PARAMETERS
This section summarizes the operating and measurement Measurement Conditions summarized in the relevant tables.
conditions, and the DC and AC characteristics of the device. Designers should check that the operating conditions in their
The parameters in the DC and AC Characteristic tables that circuit match the measurement conditions when relying on
follow are derived from tests performed under the the quoted parameters.

Table 9. Operating Conditions

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TA Ambient Operating Temperature –40 85 °C

Table 10. Data Retention and Endurance

Parameter Condition Min. Max. Unit
Erase/Program Cycles At 85°C 100,000 Cycles

Data Retention At 85°C 20 Years

Table 11. Capacitance

Symbol Parameter Test Condition Min. Max. Unit

COUT Output Capacitance (DO) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.

(November, 2014, Version 1.1) 29 AMIC Technology Corp.

 A25LS512A Series
Table 12. DC Characteristics

Symbol Parameter Test Condition Min. Typ. Max. Unit

ILI Input Leakage Current ±2 µA

ILO Output Leakage Current ±2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 5 15 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 5 15 µA
C= 0.1VCC / 0.9.VCC at 100MHz, DO = open 18 24 mA
ICC3 Operating Current (READ) C= 0.1VCC / 0.9.VCC at 50MHz, DO = open 10 21 mA
C= 0.1VCC / 0.9.VCC at 33MHz, DO = open 7 17 mA
ICC4 Operating Current (PP) S = VCC 10 15 mA
ICC5 Operating Current (WRSR) S = VCC 15 mA
ICC6 Operating Current (SE) S = VCC 25 mA
ICC7 Operating Current (BE) S = VCC 25 mA
VIL Input Low Voltage –0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6mA 0.4 V
VOH Output High Voltage IOH = –100µA VCC–0.2 V
Note: 1. This is preliminary data at 85°C

Table 13. Instruction Times

Symbol Alt. Parameter Min. Typ. Max. Unit

tW Write Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 2 3 ms

tSE Sector Erase Cycle Time 0.2 0.24 s
tBE Block Erase Cycle Time 0.5 1.3 s

tCE Chip Erase Cycle Time of A25LS512A 0.5 1.3 s

Note: 1. Max is for 85°C

2. This is preliminary data

Table 14. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

CL Load Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

Note: Output Hi-Z is defined as the point where data out is no longer driven.

(November, 2014, Version 1.1) 30 AMIC Technology Corp.

 A25LS512A Series
Figure 22. AC Measurement I/O Waveform

Input Levels Input and Output

Timing Reference Levels

0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC

(November, 2014, Version 1.1) 31 AMIC Technology Corp.

 A25LS512A Series
Table 15. AC Characteristics

Symbol Alt. Parameter Min. Typ. Max. Unit

fC fC Clock Frequency for the following instructions: FAST_READ, D.C. 80/100 MHz
PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR
(2.7V~3.6V) / (3.0V~3.6V)
fR Clock Frequency for READ instructions D.C. 66 MHz
1
tCH tCLH Clock High Time 6 ns
1
tCL tCLL Clock Low Time 5 ns
tCLCH 2 Clock Rise Time3 (peak to peak) 0.1 V/ns
tCHCL 2 Clock Fall Time3 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ 2 tDIS Output Disable Time 9 ns

tCLQV tV Clock Low to Output Valid 9 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns
2
tHHQX tLZ HOLD to Output Low-Z 8 ns
2
tHLQZ tHZ HOLD to Output High-Z 8 ns

tWHSL 4 Write Protect Setup Time 20 ns

tSHWL 4 Write Protect Hold Time 100 ns
2
tDP S High to Deep Power-down Mode 3 µs

tRES1 2 S High to Standby Mode without Electronic Signature Read 30 µs

tRES2 2 S High to Standby Mode with Electronic Signature Read 30 µs

tW Write Status Register Cycle Time 5 15 ms

tpp Page Program Cycle Time 2 3 ms
tSE Sector Erase Cycle Time 0.2 0.24 s
tBE Block Erase Cycle Time 0.5 1.3 s
tCE Chip Erase Cycle Time of A25LS512A 0.5 1.3 s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

(November, 2014, Version 1.1) 32 AMIC Technology Corp.

 A25LS512A Series

Figure 23. Serial Input Timing

tSHSL
S
tCHSL tSLCH tCHSH tSHCH

C
tCHCL
tDVCH
tCHDX tCLCH
DIO MSB IN LSB IN

High Impedance
DO

Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1

W
tSHWL
tWHSL

DIO

High Impedance
DO

(November, 2014, Version 1.1) 33 AMIC Technology Corp.

 A25LS512A Series
Figure 25. Hold Timing

tHLCH
tCHHL tHHCH
C

tCHHH

DIO

tHLQZ tHHQX
DO

HOLD

Figure 26. Output Timing

tCH
C

DIO ADDR.LSB IN

tCLQV tCLQV tCL tSHQZ

tCLQX tCLQX
DO LSB OUT

tQLQH
tQHQL

(November, 2014, Version 1.1) 34 AMIC Technology Corp.

 A25LS512A Series
Part Numbering Scheme

A25 XX XXX X X X X / X
Packing
Blank: for DIP8
G: for SOP8 In Tube
Q: for Tape & Reel

Package Material
Blank: normal
F: PB free

Temperature*
Blank = -40°C ~ +85°C

Package Type
Blank = DIP 8
M = 209 mil SOP 8
O = 150 mil SOP 8
V = TSSOP 8
Q1 = USON 8 (2*3mm)
Q4 = WSON 8 (6*5mm)

Device Version
A = A Chip Version

Device Density
512 = 512 Kbit (4KB uniform sectors)
010 = 1 Mbit (4KB uniform sectors)
020 = 2 Mbit (4KB uniform sectors)
040 = 4 Mbit (4KB uniform sectors)
080 = 8 Mbit (4KB uniform sectors)
016 = 16 Mbit (4KB uniform sectors)
032 = 32 Mbit (4KB uniform sectors)

Device Voltage
LS = 2.7-3.6V

Device Type
A25 = AMIC Serial Flash

* Optional

(November, 2014, Version 1.1) 35 AMIC Technology Corp.

 A25LS512A Series
Ordering Information

Part No. Speed (MHz) Active Read Program/Erase Standby Package

Current Current Current
Max. (mA) Max. (mA) Max. (μA)

A25LS512A-F 8 Pin Pb-Free DIP (300 mil)

A25LS512AO-F 8 Pin Pb-Free SOP (150 mil)

A25LS512AM-F 8 Pb-Free Pin SOP (209mil)

100 24 25 15
A25LS512AV-F 8 Pin Pb-Free TSSOP

A25LS512AQ1-F 8 Pin Pb-Free USON (2*3mm)

A25LS512AQ4-F 8 Pin Pb-Free WSON (6*5mm)

Operating temperature range: -40°C ~ +85°C

(November, 2014, Version 1.1) 36 AMIC Technology Corp.

 A25LS512A Series
Package Information

P-DIP 8L Outline Dimensions unit: inches/mm

Dimensions in inches Dimensions in mm

Symbol Min Nom Max Min Nom Max
A - - 0.180 - - 4.57
A1 0.015 - - 0.38 - -
A2 0.128 0.130 0.136 3.25 3.30 3.45
B 0.014 0.018 0.022 0.36 0.46 0.56
B1 0.050 0.060 0.070 1.27 1.52 1.78
B2 0.032 0.039 0.046 0.81 0.99 1.17
C 0.008 0.010 0.013 0.20 0.25 0.33
D 0.350 0.360 0.370 8.89 9.14 9.40
E 0.290 0.300 0.315 7.37 7.62 8.00
E1 0.254 0.260 0.266 6.45 6.60 6.76
e1 - 0.100 - - 2.54 -
L 0.125 - - 3.18 - -
EA 0.345 - 0.385 8.76 - 9.78
S 0.016 0.021 0.026 0.41 0.53 0.66

Notes:
1. Dimension D and E1 do not include mold flash or protrusions.
2. Dimension B1 does not include dambar protrusion.
3. Tolerance: ±0.010” (0.25mm) unless otherwise specified.

(November, 2014, Version 1.1) 37 AMIC Technology Corp.

 A25LS512A Series
Package Information

SOP 8L (150mil) Outline Dimensions unit: mm

HE
E

e b
A
A1

D 0° ~ 8° L

Symbol Dimensions in mm

A 1.35~1.75
A1 0.10~0.25
b 0.33~0.51
D 4.7~5.0
E 3.80~4.00
e 1.27 BSC
HE 5.80~6.20
L 0.40~1.27

Notes:
1. Maximum allowable mold flash is 0.15mm.
2. Complies with JEDEC publication 95 MS –012 AA.
3. All linear dimensions are in millimeters (max/min).
4. Coplanarity: Max. 0.1mm

(November, 2014, Version 1.1) 38 AMIC Technology Corp.

 A25LS512A Series
Package Information

SOP 8L (209mil) Outline Dimensions unit: mm

8 5

E1
E

1 4
C

D
A2
A

GAGE PLANE
SEATING PLANE
A1

e b θ
0.25

Dimensions in mm
Symbol
Min Nom Max
A 1.75 1.95 2.16
A1 0.05 0.15 0.25
A2 1.70 1.80 1.91
b 0.35 0.42 0.48
C 0.19 0.20 0.25
D 5.13 5.23 5.33
E 7.70 7.90 8.10
E1 5.18 5.28 5.38
e 1.27 BSC
L 0.50 0.65 0.80
θ 0° - 8°

Notes:
Maximum allowable mold flash is 0.15mm at the package
ends and 0.25mm between leads

(November, 2014, Version 1.1) 39 AMIC Technology Corp.

 A25LS512A Series
Package Information

TSSOP 8L Outline Dimensions unit: inches/mm

8 5

E1

E
C

1 4

D
A2
A

y
D

e θ
A1

b
L

L1

Dimensions in inches Dimensions in mm

Symbol
Min Nom Max Min Nom Max
A - - 0.0472 - - 1.200
A1 0.0020 - 0.0059 0.050 - 0.150
A2 0.0315 0.0394 0.0413 0.800 1.000 1.050
b 0.0075 - 0.0118 0.190 - 0.300
c 0.0035 - 0.0079 0.090 - 0.200
E 0.2441 0.2520 0.2598 6.200 6.400 6.600
E1 0.1693 0.1732 0.1772 4.300 4.400 4.500
e - 0.0256 - - 0.650 -
D 0.1142 0.1181 0.1220 2.900 3.000 3.100
L 0.0177 0.0236 0.0295 0.450 0.600 0.750
L1 - 0.0394 - - 1.000 -
y - - 0.0039 - - 0.100
θ 0° - 8° 0° - 8°

(November, 2014, Version 1.1) 40 AMIC Technology Corp.

 A25LS512A Series
Package Information

USON 8L (2 X 3mm) Outline Dimensions unit: mm

D D1

L
E1
E

e b Pin 1 I.D.

Pin 1
Top View Bottom View
A
A1

A3

Side View

Dimensions in mm
Symbol
Min Nom Max
A ＞0.50 0.55 0.60
A1 0.00 - 0.05
A3 0.152 REF
D 1.95 2.00 2.05
E 2.95 3.00 3.05
D1 1.495 1.645 1.745
E1 1.65 1.80 1.90
b 0.20 0.25 0.30
e 0.5 BSC
L 0.30 0.40 0.50

(November, 2014, Version 1.1) 41 AMIC Technology Corp.

 A25LS512A Series
Package Information

WSON 8L (6 X 5 X 0.8mm) Outline Dimensions unit: mm/mil

0.25 C
e
b
4 1 0.25 C 1 2 3 4

L
C0.30
D

D2
Pin1 ID Area

5 8 8 7 6 5
E E2

// 0.10 C
A
A1

y C
A3

Seating Plane

Dimensions in mm Dimensions in mil

Symbol
Min Nom Max Min Nom Max
A 0.700 0.750 0.800 27.6 29.5 31.5
A1 0.000 0.020 0.050 0.0 0.8 2.0
A3 0.203 REF 8.0 REF
b 0.350 0.400 0.480 13.8 15.8 18.9
D 5.900 6.000 6.100 232.3 236.2 240.2
D2 3.200 3.400 3.600 126.0 133.9 141.7
E 4.900 5.000 5.100 192.9 196.9 200.8
E2 3.800 4.000 4.200 149.6 157.5 165.4
L 0.500 0.600 0.750 19.7 23.6 29.5
e 1.270 BSC 50.0 BSC
y 0 - 0.080 0 - 3.2

Note:
1. Controlling dimension: millimeters
2. Leadframe thickness is 0.203mm (8mil)

(November, 2014, Version 1.1) 42 AMIC Technology Corp.