MGM University

Jawaharlal Nehru Engineering College, Aurangabad.

Department of Computer science & Engineering

Course Name:
Digital Electronics and Microprocessor
By
D.R.Naglot
Department of Computer Science & Engineering
JNEC, MGM University.

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Syllabus

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 Unit II
Combinational Digital Circuits
• Standard representation for logic functions, K-map
representation, and simplification of logic functions using K-
map, minimization of logical functions. Don't care conditions,
Multiplexer. De- Multiplexer/Decoders, Adders, Substractors,
BCD arithmetic, carry look ahead adder, serial adder, ALU,
elementary ALU design, parity checker/generator.

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 COMBINATIONAL CIRCUITS
• A combinational circuit consists of logic gates whose outputs
at any time are determined from only the present
combination of inputs.
• A combinational circuit performs an operation that can be
specified logically by a set of Boolean functions.

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2.1 Standard Representation of logical
functions in SOP & POS form

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
S.No. SOP POS

A way of representing Boolean expressions as A way of representing Boolean expressions

1.
sum of product terms. as product of sum terms.

SOP uses minterms. Minterm is product of POS uses maxterms. Maxterm is sum of
2. Boolean variables either in normal form or Boolean variables either in normal form or
complemented form. complemented form.

It is sum of minterms. Minterms are represented It is product of maxterms. Maxterms are

3.
as ‘m’ represented as ‘M’

SOP is formed by considering all the minterms, POS is formed by considering all the
4.
whose output is HIGH(1) maxterms, whose output is LOW(0)

While writing minterms for SOP, input with value While writing maxterms for POS, input with
1 is considered as the variable itself and input value 1 is considered as the complement
with value 0 is considered as complement of the and input with value 0 is considered as the
5.
input. variable itself.
A=1 A’=1
A’=0of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad A=0
Department
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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 SOP
A=1
A’=0

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 POS
A’=1
A=0

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Convert equation AB+AC’+BC into canonical SOP form
and find minterm and maxterm

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Convert equation (A+B)(A+C)(B+C’) into canonical
POS form and find minterm and maxterm

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Minimization Of Boolean Expressions-

The Karnaugh Map also called as K Map is a graphical representation

that provides a systematic method for simplifying the boolean expressions.

For a boolean expression consisting of n-variables, number of cells required in

K Map = 2n cells.

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 Karnaugh Map
The scientist Karnaugh was developed a karnaugh map in the year 1953.

Karnaugh maps reduce logic functions more quickly and easily compared to
boolean algebra. By reduce we mean simplify, reducing the number of gates and
inputs. There are two forms of equations .

SOP (sum of product form)

1.

POS (product of sum form)

2.

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K-Map Representation

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Two variable K map

The number of cells present in two variable K Map: 22 = 4 cells.

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 Three variable K map
The number of cells present in three variable K Map: 23 = 8 cells.

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 Four variable K map
The number of cells present in four variable K Map: 24 = 16 cells.

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 Simplification of Boolean Expression Using K-Map
Karnaugh Map Simplification Rules-

Rule-01:

We can either group 0’s with 0’s or 1’s with 1’s but we can not group 0’s and 1’s together.
● X representing don’t care can be grouped with 0’s as well as 1’s.

Rule-02:

Groups may overlap each other.

Rule-03:
We can only create a group whose number of cells can be represented in the power of 2.
● a group can only contain 1, 2, 4, 8, 16 and so on number of cells.
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Rule-04:
Groups can be only either horizontal or vertical.
We can not create groups of diagonal or any other shape.

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Rule-05:
Each group should be as large as possible.

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Rule-06:
Opposite grouping and corner grouping are allowed.

Rule-07:
There should be as few groups as possible.

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Example of two variables

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Minimize the following boolean function-
F(A, B, C) = Σm(0, 1, 6, 7)
F(A, B, C) = A’B’ + AB

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Minimize the following boolean function

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 Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)

Thus, minimized boolean expression is-

F(A, B, C, D) = BD + C’D + B’D’

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Minimize logic function in POS form

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Minimize the following boolean function-
F(A, B, C, D) = Σm(3, 4, 5, 7, 9, 13, 14, 15)

Thus, minimized boolean expression is-

F(A, B, C, D) = A’BC’ + A’CD + AC’D + ABC

It is important to note that we are not considering the quad group because we have to consider the duets anyhow.

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Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)

F(A, B, C, D) = B’C’ + D

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Minimize the following boolean function-
F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 5)
F(A, B, C) = AB + A’B’

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 Minimize the following boolean function-
F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 4, 5)

Thus, minimized boolean expression is-

F(A, B, C) = A + B’

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Minimize the following boolean function-
F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)

F(A, B, C, D) = AD + B’D + B’C’ + A’D’

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Minimize the following boolean function-
F(A, B, C) = Σm(1, 2, 5, 7) + Σd(0, 4, 6)

Thus, minimized boolean expression is-

F(A, B, C) = A + B’ + C’

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Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 15)

Thus, minimized boolean expression is-

F(A, B, C, D) = ACD’ + B’D’

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 Half Adder-
● Half Adder is a combinational logic circuit.
● It is used for the purpose of adding two single bit numbers.
● It contains 2 inputs and 2 outputs (sum and carry).

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Draw K-maps using the above truth table and determine the simplified Boolean expressions-

AB’ + B’A

A⊕B
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Draw the logic diagram.

The implementation of half adder using 1 XOR gate and 1 AND gate is as shown below-

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Limitation of Half Adder-

● Half adders have no scope of adding the carry bit resulting from the addition of previous bits.
● This is a major drawback of half adders.
● This is because real time scenarios involve adding the multiple number of bits which can not be accomplished
using half adders.

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 Full Adder-
● Full Adder is a combinational logic circuit.
● It is used for the purpose of adding two single bit numbers with a carry.
● Thus, full adder has the ability to perform the addition of three bits.
● Full adder contains 3 inputs and 2 outputs (sum and carry) as shown-

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
K-maps using the above truth table and determine the simplified Boolean expressions-

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 Logic diagram

The implementation of full adder using 1 XOR gate, 3 AND gates and 1 OR gate is as shown
below-

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Half Subtractor-
● Half Subtractor is a combinational logic circuit.
● It is used for the purpose of subtracting two single bit numbers.
● It contains 2 inputs and 2 outputs (difference and borrow).

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Logic diagram.

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Limitation of Half Subtractor-

● Half subtractors do not take into account “Borrow-in” from the previous circuit.
● This is a major drawback of half subtractors.
● This is because real time scenarios involve subtracting the multiple number of bits which can
not be accomplished using half subtractors.

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 Full Subtractor-
● Full Subtractor is a combinational logic circuit.
● It is used for the purpose of subtracting two single bit numbers.
● It also takes into consideration borrow of the lower significant stage.
● Thus, full subtractor has the ability to perform the subtraction of three bits.
● Full subtractor contains 3 inputs and 2 outputs (Difference and Borrow) as shown-

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Logic diagram.

The implementation of full subtractor using 1 XOR gate, 3 AND gates, 1 NOT gate and 1 OR gate is as
shown below-

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 Multiplexer (Data Selectors)
⮚A Multiplexer is combinational circuit that has 2^n input lines and single output
line
⮚The term Multiplexer means many into one.
⮚Multiplexing is the process of transmitting a large number of information over a
single line.
⮚A Digital Multiplexer (MUX) is a combinational Circuit that select one digital
information from several sources and transmits the selected information on a single
output line.
⮚A Multiplexer is also called a Data Selector.
⮚The Multiplexer has several data input line and a single output line.
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Cont.
⮚MUX directs one of the inputs to its output line by using a control bit word
(selection line) to its select lines.
⮚ Multiplexer contains the followings:
❖ data inputs
❖ selection inputs
❖ a single output
⮚ Selection input determines the input that should be connected to the output.
⮚The multiplexer acts like an electronic switch that selects one from different.

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Multiplexers are classified into four types:
1. 2-1 multiplexer ( 1select line)
2. 4-1 multiplexer (2 select lines)
3. 8-1 multiplexer(3 select lines)
4. 16-1 multiplexer (4 select lines)

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
8-1 Multiplexer Circuit

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 De-Multiplexer

⮚The De-Multiplexer is a combinational logic circuit that performs

the reverse operation of multiplexer (Several output lines, one input
line).
⮚De -Multiplexer means one to many. A De-Multiplexer is a
circuit with one input and many output. By applying control signal,
we can steer any input to the output. Few types of De -Multiplexer
are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 De -Multiplexer .
⮚De-Multiplexer is the process of taking information from one
input and transmitting the same over one of several outputs.
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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Types of Demultiplexer

1. 1-2 demultiplexer (1 select line)

2. 1-4 demultiplexer (2 select lines)
3. 1-8 demultiplexer (3 select lines)
4. 1-16 demultiplexer (4 select lines)

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 1x8 De-Multiplexer
A 1 to 8 demultiplexer consists of one input line, 8 output lines and 3 select lines.
Let the input be D, S1 and S2 are two select lines and eight outputs from Y0 to Y7. It
is also called as 3 to 8 demux because of the 3 selection lines. Below is the block
diagram of 1 to 8 demux.

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 1 to 8 Demux Circuit Diagram

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 1x8 De-Multiplexer
● 1x8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-Multiplexer. We know
that 1x4 De-Multiplexer has single input, two selection lines and four outputs.
Whereas, 1x8 De-Multiplexer has single input, three selection lines and eight
outputs.
● So, we require two 1x4 De-Multiplexers in second stage in order to get the final
eight outputs. Since, the number of inputs in second stage is two, we require 1x2
DeMultiplexer in first stage so that the outputs of first stage will be the inputs of
second stage. Input of this 1x2 De-Multiplexer will be the overall input of 1x8 De-
Multiplexer.

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Decoder
● The combinational circuit that change the binary information into 2N output lines is
known as Decoders.
● The binary information is passed in the form of N input lines. The output lines define
the 2N-bit code for the binary information.

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 2 to 4 line decoder
● In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and
A1 and E and four outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of
inputs, when the enable 'E' is set to 1, one of these four outputs will be 1.
The block diagram and the truth table of the 2 to 4 line decoder are given
below.
● Block Diagram:

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 Truth Table
● The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:
● Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

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Logical circuit of the above expressions is given below:

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 3 to 8 line decoder:
● The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line
decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and
three outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'. Just like 2 to 4
line decoder, when enable 'E' is set to 1, one of these four outputs will be 1. The
block diagram and the truth table of the 3 to 8 line encoder are given below.

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 Truth Table:
● The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
● Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

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Logical circuit of the above expressions is given below:

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 BCD Code
● Weighted Binary Codes : If each position of a number represents a specific weight then the coding scheme is
called weighted binary code.
● The full form of BCD is ‘Binary-Coded Decimal’. Since this is a coding scheme relating decimal and binary
numbers, four bits are required to code each decimal number.
● A decimal number in BCD (8421) is the same as its equivalent binary number only when the number is
between 0 and 9.
● A BCD number greater than 10 looks different from its equivalent binary number, even though both contain
1’s and 0’s.
1. Consider decimal 185 and its corresponding value in BCD and binary:
(185)10= (0001 1000 0101)BCD = (10111001)2

2. (35)10 and (589)10

3. is represented as 0011 0101 using BCD code, rather than (100011)2
4. Give the BCD equivalent for the decimal number 589.
The decimal number is
BCD code is 0101 1000 1001 Hence, (589)10 = (010110001001)BCD

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 Numbers from 0 to 9

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 Summary of BCD addition
Add two BCD
numbers

Sum <= 9, Sum > 9,

carry = 0 carry = 0 Sum < = 9,
carry = 1
Answer is Add 6 to sum
correct no to get
Add 6 to sum
correction to get correct
correct answer
required answer

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 BCD Addition
● Let us consider additions of 3 and 6 in BCD.

● The addition is carried out as in normal binary addition and the

sum is 1 0 0 1, which is BCD code for 9.

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Sum greater than 9 with carry 0

● The sum 1 1 1 0 is an invalid BCD number. This has occurred because the sum of the
two digits exceeds 9. Whenever this occurs the sum has to be corrected by the
addition of six (0110) in the invalid BCD number

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Sum equals 9 or less with carry 1

In this, case, result (0001 0001) is valid BCD number, but it is incorrect. To get
the correct BCD result correction factor of 6 has to be added to the least
significant digit sum

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 BCD ADDER
● To implement BCD Adder Circuit we require :
○ 4-bit binary adder for initial addition

○ Logic circuit to detect sum greater than 9 and

○ One more 4-bit adder to add 01102 in the sum if sum is greater than 9
or carry is 1.

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The logic circuit to detect sum greater than 9 can be determined by
simplifying the boolean expression of given BCD Adder Truth Table.

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Cont.
● As shown in the Fig , the two BCD numbers, together with input carry, are
first added in the top 4-bit binary adder to produce a binary sum. When the
output carry is equal to zero (i.e. when sum ≤ 9 and Cout = 0) nothing (zero)
is added to the binary sum. When it is equal to one (i.e. when sum > 9 or
Cout = 1), binary 0110 is added to the binary sum through the bottom 4-bit
binary adder. The output carry generated from the bottom binary adder can
be ignored, since it supplies information already available at the output-
carry terminal.

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 BCD Subtraction
Perform BCD subtraction using 9’s complement method (A)10 -
(B)10
1. Obtain 9’s complement of no. B
2. Add no. A and 9’s complement of no. B
3. If Answer or Sum is invalid BCD code or if carry is produced from the MSB, Add decimal 6
(0110) and carry to this sum. The result is positive number represented by this sum
4. If Answer is valid BCD code or if carry is not produced from the MSB, then the result is
negative hence take 9’s complement of the result.

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 9s Complement:
● The 9’s complement of a decimal number is found by subtracting each digit
in the number from 9. The 9’s complement of each of the decimal digits is
as follows :

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 BCD Subtraction

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Carry Look-ahead Adder
● In ripple carry adders, for each adder block, the two bits that are to be added are available
instantly. However, each adder block waits for the carry to arrive from its previous block. So, it
is not possible to generate the sum and carry of any block until the input carry is known.
The block waits for the block to produce its carry. So there will be a considerable time delay
which is carry propagation delay.

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 Carry Look-ahead Adder
● The adder produce carry propagation delay while performing other arithmetic
operations like multiplication and divisions as it uses several additions or subtraction
steps.
● This is a major problem for the adder and hence improving the speed of addition
will improve the speed of all other arithmetic operations.
● Hence reducing the carry propagation delay of adders is of great importance. There
are different logic design approaches that have been employed to overcome the
carry propagation problem.
● One widely used approach is to employ a carry look-ahead which solves this
problem by calculating the carry signals in advance, based on the input signals.
This type of adder circuit is called a carry look-ahead adder.

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 Carry Look-ahead Adder
● A carry look-ahead adder reduces the propagation delay by introducing
more complex hardware. In this design, the ripple carry design is suitably
transformed such that the carry logic over fixed groups of bits of the adder
is reduced to two-level logic.

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 Carry Look-ahead Adder
The corresponding Boolean expressions are given here to construct a carry look ahead adder. In the carry look
ahead circuit we need to generate the two signals carry propagator(P) and carry generator(G),
Pi = Ai ⊕ Bi
Gi = Ai · B i
The output sum and carry can be expressed as
Sumi = Pi ⊕ Ci
Ci+1 = Ai · Bi + Ai ⊕ Bi · Ci
Ci+1 = Gi + ( Pi · Ci)
Having these we could design the circuit. We can now write the Boolean function for the carry output of each
stage and substitute for each Ci its value from the previous equations:
C1 = G0 + P0 · C0
C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0
C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0
C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0

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Pi = Ai ⊕ Bi
Gi = Ai · Bi

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Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Arithmetic Logic Unit (ALU)

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Arithmetic Logic Unit (ALU)

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Functional Table

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Parity Generator
• What is the Parity Generator?
Definition: The parity generator is a combination circuit at the transmitter, it
takes an original message as input and generates the parity bit for that message
and the transmitter in this generator transmits messages along with its parity bit.
• Types of Parity Generator
The classification of this generator is shown in the below figure

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 Even Parity Generator
• The even parity generator maintains the binary data in even number of 1’s, for example,
the data taken is in odd number of 1’s, this even parity generator is going to maintain the
data as even number of 1’s by adding the extra 1 to the odd number of 1’s. This is also a
combinational circuit whose output is dependent upon the given input data, which means
the input data is binary data or binary code given for parity generator.

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
The even parity expression implemented by using two Ex-OR gates and the
logic diagram of this even parity using the Ex-OR logic gate is shown below.

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Odd Parity Generator
• The odd parity generator maintains the binary data in an odd number of 1’s, for example, the data taken
is in even number of 1’s, this odd parity generator is going to maintain the data as an odd number of 1’s
by adding the extra 1 to the even number of 1’s. This is the combinational circuit whose output is always
dependent upon the given input data. If there is an even number of 1’s then only parity bit is added to
make the binary code into an odd number of 1’s.

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
• The output parity bit expression for this generator
circuit is obtained as
• P = A (B C)’
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Parity Checker
• Definition: The combinational circuit at the receiver is the parity checker. This
checker takes the received message including the parity bit as input. It gives
output ‘1’ if there is some error found and gives output ‘0’ if no error is found in
the message including the parity bit.
• Types of Parity Checker
• The classification of the parity checker is shown in the below figure

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Even Parity Checker
• In even parity checker if the error bit (E) is
equal to ‘1’, then we have an error. If error
bit E=0 then indicates there is no error.
– Error Bit (E) =1, error occurs
– Error Bit (E) =0, no error

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Even Parity Checker
• The below table shows the truth table for the Even Parity Checker in which PEC = 1 if the
error occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error
occurs, i.e., if the 4-bit message has even number of 1s.

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Odd Parity Checker
• In odd parity checker if an error bit (E) is
equal to ‘1’, then it indicates there is no
error. If an error bit E=0 then indicates there
is an error.
– Error Bit (E) =1, no error
– Error Bit (E) =0, error occurs

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Odd Parity Checker

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
• After simplification, the final expression for the PEC is
obtained as
• PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR P)
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
 Parity Generator/Checker using IC’s
• The IC 74180 does the function of parity generation as well as checking.
The 9 bit (8 data bits, 1 parity bit) Parity Generator/Checker is shown in
the below figure.

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad
• The IC 74180 contains eight data bits (X0 to X7), Vcc, even input, odd input, Seven
output, S odd output, and ground pin.
• If the given even and odd input both are high (H), then the even and odd outputs
both are low (L), similarly, if the given inputs both are Low (L), then the even and
odd outputs both becomes high (H).

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 THANK
YOU

Department of Computer Science and Engineering, Jawaharlal Nehru Engineering College, Aurangabad