ASANSOL INSTITUTE OF ENGINEERING AND MANAGEMENT – POLYTECHNIC

ASANSOL

Subject : Computer System Organization

Course Code : CST207

Pre Test:
UNIT-2 (Part-3)
 Pipelining:
Pipelining is a technique used in Computer Organization to increase the throughput of a computer system by
allowing multiple instructions to be processed simultaneously at different stages of execution. This technique helps to
make better use of the CPU's resources and improve overall performance.

Key Concepts of Pipelining

1. Pipeline Stages:
o Fetch (IF): Retrieve the instruction from memory.
o Decode (ID): Decode the instruction to understand what operations are required.
o Execute (EX): Perform the operations, such as arithmetic calculations or memory access.
o Memory Access (MEM): Read from or write to memory (if needed).
o Write Back (WB): Write the result back to the register or memory.
2. Pipelining Stages in Detail:
o Instruction Fetch (IF): The instruction is fetched from memory into the instruction register.
o Instruction Decode (ID): The fetched instruction is decoded to determine the operation and operands.
o Execution (EX): The actual operation is performed based on the decoded instruction.
o Memory Access (MEM): If the instruction involves memory, data is read from or written to memory.
o Write Back (WB): The result of the execution is written back to the register file.

Example of Pipelining :
Cycle 1: IF1
Cycle 2: ID1, IF2
Cycle 3: EX1, ID2, IF3
Cycle 4: MEM1, EX2, ID3, IF4
Cycle 5: WB1, MEM2, EX3, ID4, IF5
Cycle 6: WB2, MEM3, EX4, ID5
Cycle 7: WB3, MEM4, EX5
Cycle 8: WB4, MEM5
Cycle 9: WB5
In this example:

 IF1: Instruction 1 is fetched.

 ID1: Instruction 1 is decoded.
 EX1: Instruction 1 is executed.
 MEM1: Memory operations for Instruction 1 (if needed).
 WB1: Instruction 1 results are written back.

As the pipeline progresses, subsequent instructions enter the pipeline stages, allowing the processor to work on multiple
instructions simultaneously
Pipeline Hazards

Pipelining introduces several types of hazards that can affect performance:

1. Data Hazards:
o Read After Write (RAW): An instruction needs data that has not yet been written by a previous instruction.
o Write After Read (WAR): An instruction writes to a location before a previous instruction has read it.
o Write After Write (WAW): Two instructions write to the same location in different stages.

Example:
Instruction 1: ADD R1, R2, R3 (R1 = R2 + R3)
Instruction 2: SUB R4, R1, R5 (R4 = R1 - R5)
Instruction 2 needs the result of Instruction 1 before it can proceed.

2. Control Hazards:
Branch Hazards: Occur when the pipeline makes incorrect decisions based on branch instructions.

Example:
Instruction 1: BEQ R1, R2, LABEL (Branch if R1 == R2)
Instruction 2: ADD R3, R4, R5
If the branch prediction is incorrect, Instruction 2 may need to be discarded.

3. Structural Hazards:
Occur when hardware resources are insufficient to support all the concurrent instructions.

Example: If there is only one memory unit and both an instruction fetch and data access need to occur simultaneously, a
structural hazard arises.

Techniques to Address Pipeline Hazards:

1. Data Hazard Solutions:

o Forwarding (Bypassing): Forward the result of a computation directly to the next stage that needs it.
o Stalling (Nop Insertion): Introduce delays (no-operation instructions) until data becomes available.
2. Control Hazard Solutions:
o Branch Prediction: Predict the outcome of a branch instruction to minimize delays.
o Branch Target Buffer (BTB): Store the target addresses of recently executed branches to speed up branch
resolution.
3. Structural Hazard Solutions:
o Resource Duplication: Provide additional resources to avoid conflicts.
o Pipeline Scheduling: Reorganize instruction execution to avoid resource contention.

Advantages of Pipelining

1. Increased Throughput: More instructions are completed in a given period.

2. Efficient Utilization of CPU Resources: Multiple stages of instruction processing are utilized simultaneously.
3. Improved Performance: Reduces the overall execution time of programs.

Disadvantages of Pipelining

1. Complex Design: Increased complexity in CPU design and control logic.

2. Pipeline Hazards: Requires mechanisms to handle hazards, which can reduce efficiency.
3. Diminishing Returns: Performance gains may diminish as the number of stages increases.
ARITHMETIC PIPELINE
An Arithmetic Pipeline is a technique used in computer organization to speed up the processing of arithmetic operations,
particularly in modern processors. It's based on the principle of dividing a complex arithmetic operation into smaller, more
manageable stages, where each stage performs a part of the operation in parallel with others.

Arithmetic Pipeline Stages:

 Operand Fetch: Retrieve the operands from registers or memory.

 Operand Decode: Decode the operands and prepare them for the arithmetic operation.
 Arithmetic Operation: Perform the actual arithmetic computation (addition, subtraction, multiplication, etc.).
 Result Write: Write the result to the register or memory.

Example of Arithmetic Pipelining :

Consider a simple example where we have an arithmetic pipeline that performs addition and multiplication operations.

Example Operations

1. Operation 1: ADD R1, R2, R3 (R1 = R2 + R3)

2. Operation 2: MUL R4, R5, R6 (R4 = R5 * R6)
3. Operation 3: SUB R7, R8, R9 (R7 = R8 - R9)

Pipelining Execution :
Here's how these operations might be pipelined over several clock cycles:
Cycle 1: IF1
Cycle 2: ID1, IF2
Cycle 3: EX1, ID2, IF3
Cycle 4: MEM1, EX2, ID3, IF4
Cycle 5: WB1, MEM2, EX3, ID4, IF5
Cycle 6: WB2, MEM3, EX4, ID5
Cycle 7: WB3, MEM4, EX5
Cycle 8: WB4, MEM5
Cycle 9: WB5

 Cycle 1: Fetch Operation 1 (ADD R1, R2, R3)

 Cycle 2: Decode Operation 1, Fetch Operation 2 (MUL R4, R5, R6)
 Cycle 3: Execute Operation 1, Decode Operation 2, Fetch Operation 3 (SUB R7, R8, R9)
 Cycle 4: Memory Access Operation 1, Execute Operation 2, Decode Operation 3
 Cycle 5: Write Back Operation 1, Memory Access Operation 2, Execute Operation 3
 Cycle 6: Write Back Operation 2, Memory Access Operation 3
 Cycle 7: Write Back Operation 3

Detailed Execution Steps

1. Operand Fetch:
o Fetch the operands from registers or memory.
2. Operand Decode:
o Decode the instruction to determine the arithmetic operation and operands.
3. Arithmetic Execution:
o Perform the arithmetic operation. For instance, ADD will add the contents of R2 and R3, and MUL will
multiply the contents of R5 and R6.
4. Write Back:
o Write the result of the arithmetic operation back to the destination register or memory.
Advantages:
Increased Throughput: More arithmetic operations can be processed in a shorter time.
Efficient Use of Hardware: Each stage of the pipeline can work on different instructions simultaneously.

Disadvantages:
Pipeline Overhead: Designing and managing the pipeline adds complexity to the hardware.
Latency: The time to get the final result for a single operation may be longer than a non-pipelined design due to the time
taken in each stage.

INSTRUCTION PIPELINE
An Instruction Pipeline is a technique in computer organization that allows for the overlapping execution of multiple
instructions. Instead of executing one instruction at a time, modern processors break the execution process into several
stages, allowing different stages of multiple instructions to be executed simultaneously. This increases the throughput of the
processor, meaning more instructions are executed in a shorter time.

Example: Basic 5-Stage Pipeline

Let’s assume an instruction pipeline with five stages (IF, ID, EX, MEM, WB):
Cycle 1: Fetch instruction 1 (IF stage).
Cycle 2: Decode instruction 1 (ID stage) and fetch instruction 2 (IF stage).
Cycle 3: Execute instruction 1 (EX stage), decode instruction 2 (ID stage), and fetch instruction 3 (IF stage).
This process continues, with multiple instructions being processed at different stages in parallel.

Challenges of Instruction Pipelining

1. Pipeline Hazards: Managing and mitigating hazards can be complex and may require additional mechanisms and
hardware.
2. Complex Design: Designing and managing an instruction pipeline involves complex control logic and synchronization.

RISC PIPELINE
The RISC Pipeline is an integral feature of Reduced Instruction Set Computer (RISC) architectures. RISC processors are
designed to execute instructions in a single clock cycle, making them ideal candidates for pipelining. A RISC pipeline breaks
down the instruction execution process into smaller stages, which allows for the simultaneous processing of multiple
instructions, increasing throughput and efficiency.

Stages of a RISC Pipeline:

A typical RISC pipeline consists of 5 stages. These stages are designed to ensure that each instruction moves smoothly from
one stage to the next without unnecessary delays.
Instruction Fetch (IF):
In this stage, the processor fetches the instruction from memory, typically using the program counter (PC) to locate the next
instruction. The PC is then incremented to point to the next instruction in the sequence.
Instruction Decode (ID):
The fetched instruction is decoded to understand the operation that needs to be performed. The instruction’s operands are
also identified, and the necessary registers are accessed to fetch their values.
Execute (EX):
The operation defined by the instruction is executed in the ALU (Arithmetic Logic Unit). This could involve arithmetic
operations (e.g., addition, subtraction) or logical operations (e.g., AND, OR).
Memory Access (MEM):
If the instruction involves loading data from or storing data to memory, this stage accesses the memory. For other
instructions (like arithmetic or logical instructions), this stage is bypassed.
Write Back (WB):
The result of the instruction, whether from memory or from the ALU, is written back to the appropriate register, completing
the execution of the instruction.
 Instruction 1 (I1) Instruction 2 (I2) Instruction 3 (I3)
Clock Cycle

1 IF

2 ID IF

3 EX ID IF

4 MEM EX ID

5 WB MEM EX

6 WB MEM

7 WB

VECTORS
A vector is a mathematical entity that has both magnitude and direction. In computer science and data processing, a vector
typically refers to an ordered collection of numbers, often used to represent data points, directions, or coordinates in space.
Vectors are fundamental in fields such as physics, mathematics, and computer graphics.

Vectors are versatile and essential in many applications like physics, machine learning, computer graphics, and optimization
problems.

VECTOR PROCESSING
Vector processing is a technique used in computer organization to handle operations involving vectors, which are essentially
one-dimensional arrays of data. It's particularly useful for tasks that involve large amounts of data or require parallel
processing, such as scientific computations, graphics processing, and machine learning.

Key Concepts in Vector Processing :

Vector vs. Scalar Processing:
Scalar Processing involves handling one data element at a time. Each operation processes individual data elements
sequentially.
Vector Processing involves handling multiple data elements simultaneously. Operations are applied to entire vectors (arrays
of data) in parallel, which can significantly speed up processing.

Vector Processors:
These are specialized processors designed to perform operations on vector data. They have vector registers and vector
instructions that allow them to handle large datasets efficiently.
Common operations include addition, multiplication, and other mathematical functions performed on vectors.
Example of Vectors
1. Vector Arrays
Consider an array of integers:
Vector A: [4, 8, 15, 16, 23, 42]
 This is a one-dimensional vector where each element can be accessed by its index (0 through 5).
 Operations such as addition or multiplication can be performed on this array efficiently.
Adding 5 to each element:
Resulting Vector A: [9, 13, 20, 21, 28, 47]
2. Vector Processors
Suppose we have two vectors and a vector processor that can perform operations on vectors:
Vector X: [1, 2, 3, 4]
Vector Y: [5, 6, 7, 8]
Vector Addition Operation:
Result Vector Z = X + Y: [6, 8, 10, 12]
The vector processor will perform this operation in parallel for each element of the vectors.

Vector Instructions:
Vector Load/Store: Instructions to load vectors from memory into vector registers and store vectors from vector registers to
memory.
Vector Arithmetic: Instructions to perform arithmetic operations (e.g., addition, subtraction, multiplication) on entire vectors.
Vector Reduction: Operations that combine elements of a vector into a single result, like summing all elements of a vector.

Vector Registers:
These are special-purpose registers used to store vector data. They are larger than scalar registers and can hold multiple data
elements.

Vector Length:
The length of a vector refers to the number of elements it contains. Vector processors are designed to handle vectors of a
specific length efficiently.

Pipelining and Parallelism:

Vector processors use pipelining to improve performance by overlapping the execution of multiple vector instructions.
They also leverage parallelism by performing operations on multiple data elements simultaneously.

Example Vector Instruction Execution:

Assume we have vectors A and B:

A: [2, 4, 6, 8]
B: [1, 3, 5, 7]
Executing VADD A, B, C where C is a new vector will result in:
C: [3, 7, 11, 15]

Vector vs. Scalar Processing:

Scalar Processing involves handling one data element at a time. Each operation processes individual data elements
sequentially.
Vector Processing involves handling multiple data elements simultaneously. Operations are applied to entire vectors (arrays
of data) in parallel, which can significantly speed up processing.

Applications of Vectors :

1. Scientific Computing: Vectors are used to represent and compute scientific data, such as physical simulations and
mathematical modeling.
 2. Graphics Processing: In graphics processing, vectors represent coordinates and colors, and vector operations are
used for rendering and transformations.
3. Machine Learning: Vectors represent data points and features in machine learning algorithms, enabling efficient
computation and analysis.

ARRAY PROCESSORS :
Array Processors are specialized parallel computing systems that perform the same operation on multiple data points
simultaneously. They consist of multiple processing units that work in parallel to execute vector or matrix operations, making
them ideal for tasks that involve large datasets such as scientific computations, image processing, and simulations.

Key Concepts of Array Processors

1. SIMD Architecture:
o Array processors use Single Instruction, Multiple Data (SIMD) architecture, where a single instruction is
applied to multiple data points at the same time.
o The array processor consists of multiple Processing Elements (PEs), each capable of performing operations
on different data elements in parallel.
2. Parallel Processing:
o Array processors are designed to exploit parallelism by performing operations on entire arrays or vectors in
parallel. This increases throughput and efficiency when dealing with large amounts of data.
3. Fixed Control Unit:
o The control unit issues a single instruction, which is broadcast to all the processing elements. Each processing
element then applies that instruction to its corresponding data point.

Structure of an Array Processor

 Control Unit (CU): Issues instructions that are broadcast to all processing elements.
 Processing Elements (PEs): Small, simple processors that perform the actual computation on individual data
elements. Each PE operates on one element of the array at a time.
 Interconnection Network: Connects the PEs and allows data to be transferred between them or to/from memory.

Example of Array Processors

Let's consider an example where we want to perform the addition of two arrays (vectors) using an array processor.
Problem: Add two vectors, A and B, element-wise to produce a new vector C.
A = [1, 2, 3, 4]
B = [5, 6, 7, 8]
Each element of vector A will be added to the corresponding element of vector B to produce the result vector C:
C = [A1 + B1, A2 + B2, A3 + B3, A4 + B4]
= [1+5, 2+6, 3+7, 4+8]
= [6, 8, 10, 12]
Execution in an Array Processor:

 The array processor has four Processing Elements (PE1, PE2, PE3, PE4).
 The Control Unit (CU) issues a single instruction: ADD A, B.
 Each PE will then add the corresponding elements of A and B:
o PE1 adds 1 + 5 = 6
o PE2 adds 2 + 6 = 8
o PE3 adds 3 + 7 = 10
o PE4 adds 4 + 8 = 12
 The result C = [6, 8, 10, 12] is produced in parallel.

Since all PEs work in parallel, the operation takes the same time as processing a single element, making array processors
highly efficient for vector and matrix operations.
Applications of Array Processors

1. Scientific Computing: Array processors are used in scientific simulations where large-scale mathematical
computations (e.g., matrix multiplication, solving differential equations) are required.
2. Image and Signal Processing: Array processors are used for real-time image and signal processing tasks, such as
filtering, transformation, and enhancement.
3. Artificial Intelligence and Machine Learning: In AI/ML, array processors can accelerate operations on large datasets,
such as matrix multiplications in neural networks.
4. Weather Forecasting: Large amounts of data are processed simultaneously to predict weather patterns.

Advantages of Array Processors

1. High Throughput: Since operations are performed in parallel on multiple data elements, array processors can process
large datasets much faster than traditional processors.
2. Efficient for SIMD Tasks: Ideal for tasks where the same operation needs to be performed on multiple data points,
such as matrix operations.
3. Scalability: The number of processing elements can be increased to handle larger arrays or more complex tasks,
enhancing performance.

Disadvantages of Array Processors

1. Limited Flexibility: Array processors are best suited for SIMD operations. They may not perform well on tasks that
require different instructions for different data points.
2. Complex Hardware: The design and implementation of an array processor with multiple processing elements and a
control unit can be complex and costly.
3. Memory Bottleneck: Array processors often need fast access to large amounts of memory, which can become a
bottleneck if not efficiently managed.

IMPORTANT QUESTIONS

A. Multiple Choice Questions :

Q1. What is the main advantage of an arithmetic pipeline in computer organization?

A) Reduces the size of memory
B) Speeds up complex arithmetic operations
C) Reduces instruction fetching time
D) Increases instruction length

Answer: B) Speeds up complex arithmetic operations

Q2. Which of the following operations is commonly accelerated by an arithmetic pipeline?

A) Instruction fetch
B) Memory access
C) Floating-point arithmetic
D) Branch prediction

Answer: C) Floating-point arithmetic

Q3. In an arithmetic pipeline, the result of each stage is:

A) Discarded at the end of each cycle
B) Passed to the next stage for further processing
C) Sent to memory immediately
D) Stored in a register for reuse

Answer: B) Passed to the next stage for further processing

Q4. What is the primary purpose of instruction pipelining?
A) To increase the size of cache memory
B) To fetch multiple instructions simultaneously
C) To overlap the execution of instructions
D) To execute instructions in random order

Answer: C) To overlap the execution of instructions

Q5. Which of the following hazards can occur in an instruction pipeline?

A) Data hazards
B) Structural hazards
C) Control hazards
D) All of the above

Answer: D) All of the above

Q6. What technique can be used to mitigate control hazards in an instruction pipeline?
A) Stalling
B) Branch prediction
C) Data forwarding
D) Loop unrolling

Answer: B) Branch prediction

Q7. What is one key feature of the RISC pipeline architecture?

A) Complex instructions with variable length
B) Simple, fixed-length instructions
C) Multiple memory access stages in each instruction
D) Execution of instructions in a microcoded fashion

Answer: B) Simple, fixed-length instructions

Q8. In a RISC pipeline, each instruction typically:

A) Requires multiple cycles for execution
B) Executes in a single cycle
C) Requires an interpreter for execution
D) Can be of variable length

Answer: B) Executes in a single cycle

Q9. Which of the following is true for RISC processors compared to CISC processors?
A) Fewer instructions, but they are more complex
B) More instructions and they execute faster
C) Fewer, simpler instructions with uniform execution time
D) No pipelining capabilities

Answer: C) Fewer, simpler instructions with uniform execution time

Q10. What is the primary advantage of vector processing?

A) Efficiently handles large arrays of data with a single instruction
B) Reduces the size of the cache memory
C) Speeds up memory access times
D) Simplifies control unit design

Answer: A) Efficiently handles large arrays of data with a single instruction

Q11. Which of the following is an example of a vector processor operation?
A) Scalar multiplication
B) Adding two single values
C) Adding two vectors element-wise
D) Multiplying two matrices using nested loops

Answer: C) Adding two vectors element-wise

Q12. Which architecture is commonly associated with vector processing?

A) SIMD (Single Instruction, Multiple Data)
B) MIMD (Multiple Instruction, Multiple Data)
C) SISD (Single Instruction, Single Data)
D) MISD (Multiple Instruction, Single Data)

Answer: A) SIMD (Single Instruction, Multiple Data)

Q13. What type of architecture is typically used in an array processor?

 A) SISD (Single Instruction, Single Data)

 B) SIMD (Single Instruction, Multiple Data)
 C) MIMD (Multiple Instruction, Multiple Data)
 D) MISD (Multiple Instruction, Single Data)

Answer: B) SIMD (Single Instruction, Multiple Data)

Q14. In an array processor, the same operation is applied to:

 A) Different instructions
 B) A single element of data
 C) Multiple elements of data simultaneously
 D) Multiple memory locations simultaneously

Answer: C) Multiple elements of data simultaneously

Q15. Which of the following applications benefits most from array processors?

 A) Database transaction processing

 B) Scientific simulations involving matrix calculations
 C) Text processing
 D) File system management

Answer: B) Scientific simulations involving matrix calculations

B. Answer the following questions :

Q1) What is an Arithmetic Pipeline?

Q2) How does an Arithmetic Pipeline improve performance?
Q3) What type of arithmetic operations can benefit from pipelining?
Q4) What is an Instruction Pipeline?
Q5) What are the common stages of an Instruction Pipeline?
Q6) What are the main types of hazards in Instruction Pipelining?
Q7) How does the RISC Pipeline differ from the CISC Pipeline?
Q8) What is the advantage of a RISC Pipeline?
Q9) What is Vector Processing? How does Vector Processing improve performance?
Q10) What is the difference between scalar and vector processing?
Q11) What is an Array Processor?
Q12) What are the Advantages and Disadvantages of Array Processors ?
Q13) How does an Array Processor implement SIMD (Single Instruction, Multiple Data)? Give Example.