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Nmos - 4

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42 views4 pages

Nmos - 4

Provide step by step solutions.

Uploaded by

agk101
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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NMOS Homework

Question #1: NMOS gate VT = 1V, KL = 0.4mA/V2 Ks=0.8mA/V2, VDD = 5V

a. What is the logic function of this gate?


b. Determine Vo if A = 3V and B = 0.5V
c. Determine Vo if A = B = 3V
d. Is the Vo in part (a) an acceptable VOL? Why?

Question #2: NMOS Inverter


VDD = 5V, CL = 20pF, KL = 0.2 mA/V2, KS = 1 mA/V2, VT = 1V. Assume that QS
is Ohmic. Neglect internal capacitances.

a. Determine approximate VOH.


b. Determine VOL for Vi = VOH (of part (a))
c. Determine the approximate ViL for this inverter.
#2 Cont.
d. Determine ViH for Vo = ViL
e. Determine the fall time, tf of Vo (90% to 10% of VOH) when Vi receives a
0V to VOH step.
f. Determine the Industry Standard values of: ViL, ViH, VoL and VoH.

Question #3:
The NMOS gate shown is designed for QL to operate at the boundary of the
saturation region for one transistor on with V 2L = 0.5V

a. For KL = 0.25mA/V2 and VT = 1.0V, determine the current ID and the


required value of R.
b. What is the required value of KS for the switching transistors, assuming
that the input is driven from a similar gate?
c. With all three switching transistors ON, determine v 2 and find the
operating point for QL.

Question #4:
An n-input NMOS NOR gate has Ks = 4mA/V2, KL = 2 mA/V2, VT = 1.0V, VDD =
5.0V. Find the approximate values for VOH and VOL for n = 1,2 and 3 inputs.
Assume QL = sat and Qs = ohmic, Vi = VOH

Question #5:
A three input NMOS NAND gate has KS = 12 mA/V2, KL = 2mA/V2, VT = 1V
and
VDD = 5V. If ViS = the approximate values of VOH find:
a. VOL
b. VDSS1, VDSS2 and VDSS3
Question #6: NMOS NOR gate
KL = 0.2 mA/V2, KS = 1 mA/V2, VT = 1V (all).
a. What is approximate VOH of this gate if all inputs are grounded.

b. If a 3 volt potential is applied to each input, determine the output


voltage. Assume QL is saturated and QS is in the ohmic region.
c. Determine IDSL.
Question #7: NMOS gate
VT = 1V, K1 = K2 = 2 mA/V2, K3 = 0.2mA/V2, CL = 100 pF, VDD = 5V.
IDS = K/2 *(Vgs – VT)2; IDS = K[(Vgs – VT)*VDS – VDS2/2]
Vds = Vgs - VT – [(Vgs – VT)2 – 2*IDS/K]1/2
a. What is IDS for Q1?
b. What is approximate VOH?
c. What is VOL, assume Q1, Q2 are OHMIC and the gate is driven by NMOS
technology?
d. What is VDS for Q1?
e. What is tf of the output voltage (80% to 20% of VOH) if ViA and ViB receive
a 0V to VOH step with a 0 rise time.

8) NMOS Inverter with Resister Load


Repeat problem (2) using a resister RD of 5K instead of QL

9) NMOS Inverter with Depletion FET. VT=-3V


Repeat problem (2) using a depletion mode QL instead of an
enhancement one.

10) Body Effect. Φ = 0.3, γ = 0.5


Repeat problem 2f but consider the body effect.

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