Dept.

of DDCO LAB
CSE,DBIT MANUAL

Don Bosco Institute of Technology, Bangalore

Kumbalagodu, Mysore Road, Bangalore 74
Department of Computer Science and Engineering

Digital Design & Computer Organisation

(BCS302)

LABORATORY MANUAL

Faculty:
Dr.Manjunath
Swamy Ranjeet
Champa CH(Assisstant Professor,DBIT)
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VISION
To be a center of excellence, enabling students in the area of Computer Science & Engineering
to become successful and socially responsible software professionals.

MISSION

M1: To impart knowledge that builds software skills with logical and structured thinking.
M2: To provide training on the usage of software tools for developing applications in the multiple domains
of Computer Science & Engineering

M3: To create entrepreneurial manpower to serve in industry, academia, and social setting.
M4: To inculcate professional ethics and concern for the environment so that it benefits society.

COURSE OUTCOMES
On the completion of this laboratory course, the students will be able to:

COs COURSE OUTCOMES

BcS302.1 Apply the K—Map techniques to simplify various Boolean expressions.

BcS302.2 Design different types of combinational and sequential circuits along with Verilog
programs.
BcS302.3 Understanding VHDL models
BcS302.4 Design basic adders and subtractors
BcS302.5 Design and implement multiplexer and demultiplexers
BcS302.6 Counters and registers using flip-flops.

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Sl No. EXPERIMENT CO’s

Experiment-1 Given a 4-variable logic expression, simplify it using appropriate 1,3

technique and simulate the same using basic gates.
Experiment-2 Design a 4 bit full adder and Subtractor and simulate the same using 2, 4
basic gates.

Experiment-3 Design Verilog HDL to implement simple circuits using 1,2,3

structural, Data flow and Behavioral model.
Experiment-4 Design Verilog HDL to implement Binary Adder-Subtractor — Half
and Full Adder, Half and Full Subtractor 1,2,4
Experiment-5 Design Verilog HDL to implement Decimal adder. 1,2,4

Experiment-6 Design Verilog program to implement Different types of

multiplexer like 2:1, 4:1 and 8:1 1,2,5
Experiment-7 Design Verilog program to implement types of De-Multiplexer.
1,2,5
Experiment-8 Design Verilog program for implementing various types of Flip-
1,2,6
Flops such as SR, JK and D

P PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PS PSO

COURSE O1 2 3 4 5 6 7 8 9 0 1 2 1 O2 3
OUTCOMES
BcS302.1 CO1 2 2 2
BcS302.2 CO2 2 2 2
BcS302.3 CO3 2 2 2
BcS302.4 CO4 2 2 2 2
BcS302.5 CO5 2 2 2
BcS302.6 CO6 2 2 2

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Split-up of Marks used Practical Sessions

Rubrics No. Practical Sessions- Continuation Evaluation Marks

(CE)
Methodology / Process Steps per Experiment
R1 Observation 10
R2 Record writing : Write up of Procedure / Algorithm/ Program 30
and Execution/conduction of experiment
R3 Viva – Voce (Questions & Answers on relevant Experiment 10
/Topic)
Total Marks 50
(Scale down to 15)

Rubrics No. Practical Sessions-Internal Assessment (IA) Marks

R1 Write-up of Procedure/Program/Algorithm 10
R2 Conduction/Execution 30
R3 Viva-Voce 10
Total Marks 50
(Scale down to 10)

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Language Overview

INTRODUCTION
Verilog HDL is a Hardware Description Language (HDL). A Hardware Description Language
is a language used to describe a digital system, for example, a computer or a component of a
computer. One may describe a digital system at several levels. For example, an HDL might
describe the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip, i. e.,
and the switch level. Or, it might describe the logical gates and flip flops in a digital system,i. e.,
the gate level. An even higher level describes the registers and the transfers of vectors of
information between registers. This is called the Register Transfer Level (RTL). Verilog
supports all of these levels. However, this handout focuses on only the portions of Verilog which
support the RTL level.

What is Verilog?
Verilog is one of the two major Hardware Description Languages (HDL) used by hardware
Designers in industry and academia. VHDL is the other one. The industry is currently split on
Which is better. Many feel that Verilog is easier to learn and use than VHDL. As one hardware
designer puts it, “I hope the competition uses VHDL.” VHDL was made an IEEE Standard
in1987, and Verilog in 1995. Verilog is very C-like and liked by electrical and computer engineers
as most learn the C language in college. VHDL is very Ada-like and most engineers have no
experience with Ada. Verilog was introduced in 1985 by Gateway Design System Corporation,
now a part of Cadence Design Systems, Inc.’s Systems Division. Until May, 1990, with the
formation of Open Verilog International (OVI), Verilog HDL was a proprietary language of
Cadence. Cadence was motivated to open the language to the Public Domain with the expectation
that the market for Verilog HDL- related software products would grow more rapidly with broader
acceptance of the language. Cadence realized that Verilog HDL users wanted other software and
service companies to embrace the language and develop Verilog-supported design tools.
Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as
at the architectural or behavioural level as well as the lower implementation levels (i. e. , gate and
switch levels) leading to Very Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and
chip fabrication. A primary use of HDLs is the simulation of designs before the designer must
commit to fabrication. This handout does not cover all of Verilog HDL but focuses on the use of
Verilog HDL at the architectural or behavioural levels. The handout emphasizes design at the
Register Transfer Level (RTL).

Why Use Verilog HDL?

Digital systems are highly complex. At their most detailed level, they may consists of millions of
elements, i. e., transistors or logic gates. Therefore, for large digital systems, gate-level design is
dead. For many decades, logic schematics served as the lingua franca of logic design, but not
anymore. Today, hardware complexity has grown to such a degree that a schematic with logic
gates is almost useless as it shows only a web of connectivity and not the functionality of design.
Since the 1970s, Computer engineers and electrical engineers have moved toward hardware
description languages (HDLs).

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The most prominent modern HDLs in industry are Verilog and VHDL. Verilog is the top HDL used
by over 10,000 designers at such hardware vendors as Sun Microsystems, Apple Computer and
Motorola. Industrial designers like Verilog. It works.
The Verilog language provides the digital designer with a means of describing a digital system at a
wide range of levels of abstraction, and, at the same time, provides access to computer-aided
design tools to aid in the design process at these levels.
Verilog allows hardware designers to express their design with behavioral constructs, deterring
the details of implementation to a later stage of design in the design. An abstract representation
helps the designer explore architectural alternatives through simulations and to detect design
bottlenecks before detailed design begins.
Though the behavioral level of Verilog is a high level description of a digital system, it is still
a precise notation. Computer-aided-design tools, i. e., programs, exist which will “compile” programs
in the Verilog notation to the level of circuits consisting of logic gates and flip flops. One could then
go to the lab and wire up the logical circuits and have a functioning system. And, other tools can
“compile” programs in Verilog notation to a description of the integrated circuit masks for very large
scale integration (VLSI). Therefore, with the proper automated tools, one can create a VLSI
description of a design in Verilog and send the VLSI description via electronic mail to a silicon
foundry in California and receive the integrated chip in a few weeks by way of snail mail. Verilog
also allows the designer to specific designs at the logical gate level using gate constructs and the
transistor level using switch constructs.
Our goal in the course is not to create VLSI chips but to use Verilog to precisely describe the
functionality of any digital system, for example, a computer. However, a VLSI chip designed by way
of Verilog’s behavioural constructs will be rather slow and be wasteful of chip area. The lower levels
in Verilog allow engineers to optimize the logical circuits and VLSI layouts to maximize speed and
minimize area of the VLSI chip.

The Verilog Language

There is no attempt in this handout to describe the complete Verilog language. It describes
only the portions of the language needed to allow students to explore the architectural aspects of
computers. In fact, this handout covers only a small fraction of the language. For the complete
description of the Verilog HDL, consult the references at the end of the handout.
We begin our study of the Verilog language by looking at a simple Verilog program. Looking at the
assignment statements, we notice that the language is very C-like. Comments have a C++ flavor, I e.,
they are shown by “//” to the end of the line. The Verilog language describes a digital system as a set
of modules, but here we have only a single module called “simple”.

Program Structure
The Verilog language describes a digital system as a set of modules. Each of these
modules has an interface to other modules to describe how they are interconnected. Usually we
place one
module per file but that is not a requirement. The modules may run concurrently, but usually we
have one top level module which specifies a closed system containing both test data and hardware
models. The top level module invokes instances of other modules.
Modules can represent pieces of hardware ranging from simple gates to complete systems, e.
g., a microprocessor. Modules can either be specified behaviorally or structurally (or a

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combination of the two). A behavioral specification defines the behavior of a digital system
(module) using traditional programming language constructs, e. g., ifs, assignment statements.
A structural specification expresses the behavior of a digital system (module) as a
hierarchical interconnection of sub modules. At the bottom of the hierarchy the components must
be primitives or specified behaviorally. Verilog primitives include gates, e. g., nand, as well as
pass transistors (switches).
The structure of a module is the following:
module <module name> (<port list>);
<declares>
<module items>
endmodule
The <module name> is an identifier that uniquely names the module. The <port list> is a list
of input, inout and output ports which are used to connect to other modules. The
<declares> section specifies data objects as registers, memories and wires as wells as
procedural constructs such as functions and tasks.
The <module items> may be initial constructs, always constructs, continuous
assignments or instances of modules.

Simulation

Steps:

1. Start The Xilunx Project Navigator By Using The Desktop Shortcut or By using the Start
→Programs →Xilinx ISE (14.7).
2. Create a New project Select File menu and Then Select New Project.
3. Specify the project Name and Location in pop up Window and click next.
4. To Create New Verilog file Right click on the device name and Select NEW SOURCE.
Select Verilog module in New Source Wizard and Give Suitable name for the Project
Click NEXT for the DefineModule Window.
5. Write Behavioral Verilog code in Verilog Editor.

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Experiment-01
Aim: Given a four variable logic expression. Simplify it
using appropriate technique and simulate the same using
logic gates.

a.)Expression:
Y=AB’CD + A’BCD + ABC’D + ABCD’ + ABCD + A’B’CD
+ ABC’D

K-MAP:

CD AB

00(C’D’) 01(C’D) 11(CD) 10(CD’)

00(A’B’)
1

01(A’B)
1

11(AB)
1 1 1 1

10(AB’)
1

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Logic diagram:

Verilog Module:
Module
variable(A,B,C,D,Y);
Input A,B,C,D;
output Y;
wire
w1,w2;
and G1(w1,A,B);
and G2(w2,C,D);
or G3(Y,w1,w2);
end module

Truth Table:
Inputs Output
A B C D Y
1 0 1 1 1
1 1 1 1 1
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0 0 0 1 0
1 0 1 0 0

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b.) Expression:
Y=m0,m1,m2,m3,m6,m10,m14,m4,m12,m13,m11,m7,m15

K-MAP:
AB CD
C’D’ C’D CD CD’

A’ 1 1 1 1
B’

A’ 1 1 1
B

1 1 1
A
B

1 1 1
Y=C+D’+A’B’
Logic Diagram:

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Verilog module:
module circuit(A,B,C,D,Y);
output Y;
Input A,B,C,D;
wire w1,w2,w3,w4,w5;
not G1(w1,A);
not G2(W2,B);
not G3(w3,D);
and G4(w4,w1,w2);
or G5(w5,w4,c);
or G6(Y,w5,w3);
end module

Truth Table:
A B
INPUT C D OUTPUT Y

0 0 0 0 1

1 1 1 1 1

1 0 1 1 1

0 0 1 1 1

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c.)Expression:
F(w,x,y,z)=(1,3,7,11,15)
D(w,x,y,z)=(0,2,5)
K-MAP:

wx yz y’z’ y’z yz yz’

w’x’
X 1 1 X
w’x
X 1

wx
1

wx’ 1

A=w’x’+yz

Logic diagram:

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Verilog module:
module design(w,x,y,z,a);
output a;
Input w,x,y,z;
wire w1,w2,w3,w4;
not G1(w1,w);
not G2(w2,x);
and G3(w3,y,z);
and G4(w4,w1,w2);
or G5(a,w4,w3);
end module

Truth Table:

Inputs Output
W x y z a

0 0 0 0 1

0 1 0 1 0

1 1 0 0 0

1 0 0 1 0

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d.)Expression:
F=a’b’c’d’+a’b’c’d+a’b’cd’+a’bcd’+ab’c’d’+ab’c’d+ab’cd’
MAP:

ab cd
c’d’ c’d cd cd’

a
F=b’c’+b’d’+a’cd’
’ 1 1 1
b
Logic diagram:
1
a
’
b

a 1 1 1
b

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Verilog Module:
module var(a,b,c,d,f);
output F;
input a,b,c,d;
wire w1,w2,w3,w4,w5,w6,w7;
not g1(w1,a);
not g2(w2,b);
not g3(w3,c);
not g4(w4,d);
and g5(w5,w2,w3);
and g6(w6,w4);
and g7(w7,w1);
or g8(F,w5,w6,w7);
end module

Truth table:

Inputs output
A b c d F

0 1 1 0 0

1 0 1 0 1

0 1 0 1 0

1 1 0 0 0

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Experiment-02
Aim: Design a 4 bit full adder-subtractor and simulate the same
using basic gates.
4-bit adder:
Logic diagram:

Verilog module:
module four_bit sub(
input[3:0] A,
input[3:0] B,
input M,
output[3:0] sum,
output carry,
output overflow);
wire[3:0] x,y,z;
assign x=A&7;M
assign y=(b^{M,M,M,M})&7;
assign z=x+y+M;

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assign overflow=carry^z[3];
assign{carry,sum}=A+(B^{M,M,M,M})+M;
end module

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Experiment-03:
Aim: Design a Verilog HDL to implement simple circuits using
structural and data flow model.

Logic diagram:

F=a+b+a’c’
Structural model:
module ckt(a,b,c,f);
input a,b,c;

output F;

wire w1,w2,w3;

or g1(w1,a,b);

and g2(w2,a,c);

not g3(w3,w2);

or g4(F,w1,w3);

end module

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Data flow model:

module ckt(a,b,c,f);
input a,b,c;
output F;
assign F=(a||b||(!(a&&c)));
endmodule

Truth table:

Inputs Output
A B c F

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

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Experiment-04:
Aim:Design a Verilog module to implement half adder,half
subtractor,full adder,full subtractor.

a.)Half subtractor:
Expression:
Diff=A+B
Br=A’.B

Logic diagram:

Verilog module:
module half_sub(A,B,Diff,Br);
Input A,B;
output Diff,Br;
wire w1;
Xor g1(Diff,w1,B);
and g3(Br,w1,B);
not g2(w1,A);
endmodule

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Truth table:

Inputs Output
A B Diff Br

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

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b.)Half adder:
Expression:
Sum=A+B
Carry=A.B

Logic diagram:

Verilog module:
module half_adder(A,B,Sum,Cr);
Input A,B;

output Sum,Cr;

Xor g1(sum,A,B);

and g2(Cr,A,B);

end module

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Truth table:

Inputs Output
A B Sum Cr

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

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c.)Full adder:
Expression:
Sum=A+’B+’Cin

Carry=BCin+ACin+AB

Logic diagram:

Verilog module:
module full_adder(A,B,Cin,Sum,Cr);
Input A,B,Cin;

output Sum,Cr;

wire w1,w2,w3;

Xor g1(w1,A,B);

and g2(w2,A,B);

Xor g3(Sum,w1,Cin);

and g4(w3,w1,cin);

or g5(Cr,w3,w2);

end module

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Truth table:

Inputs Output
A B Cin Carry Sum

0 0 0 0 0

0 0 1 1 1

0 1 1 1 0

1 0 1 1 0

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d.)Full
subtractor:
Expression:
Diff=A+B+Cin
Br=BCin+A’Cin+A’B

Logic diagram:

Verilog module:
module full_sub(A,B,Cin,Diff,Br);
Input A,B,Cin;

output Diff,Br;

wire w1,w2,w3,w4,w5;

Xor g1(w1,A,B);

not g2(w2,A);

and g3(w4,B,w2);

Xor g4(Diff,w1,Cin);

not g5(w3,w1);

and g6(w5,Cin,w3);

or g7(Br,w5,w4);
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endmodule

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Truth
table:
Inputs Output
A B Cin Diff Br

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

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Program 5:
Aim: Design Verilog HDL to implement Decimal Adder

module
p5deci(a,b,sum,cout);
input [3:0] a;
input [3:0] b;
output [3:0]
sum; output
cout;
reg [3:0]
sum; reg
cout;
always@ (a,b)
begin {cout,sum} =
a+b; if(a>9 || b>9 ||
sum>9) begin
{cout,sum} = sum+6;
en
d
en
d
endmodule

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Program 6:
Aim: Design Verilog program to implement types of Multiplexer
like 2:1,4:1,8:1

a) 2:1multiplexer
Verilog:
Module xyz(xo,
x1,s,z); Input xo,
x1,s;
Output z;
Wire w1, w2, w3;
And g1(w2, xo,
w1);
Not g4(w1, s);
And g3(w3, x1, s);
Or g2(z, w2,
w3);
End module
Boolean function: xo s’ + x1 s

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Truth Table:
INPUT OUTPUT
S XO X1 Z
0 0 X 0
0 1 X 1
1 X 0 0
1 X 1 1

Logic Diagram:

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b)4:1 multiplexer
Verilog:
Module abc(xo, x1, x2, x3, so,
s1, z) Input xo, x1, x2, x3, so, s1;
Output z;
Wire w1, w2, w3, w4, w5,
w6; Not g1(w1, so);
Not g2(w2, s1);
And g3(w3, xo, w1, w2);
And g4(w4, x1, w1, s1);
And g5(w5, x2, so,w2);
And g6(w6, x3, w1, w2);
Or g7(z, w3, w4, w5,w6);
endmodule
Boolean function: xo so’ so’+x1 so’ s1 +x2 so s1’+x3 so’ s1’
TRUTH TABLE:

INPUT OUTPUT
SO S1 Z
0 0 XO
0 1 X
1
1 0 X
2
1 1 X
3
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Logic Diagram:

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c)8:1 multiplexer
Verilog:
Module mux (So, S1, S2 , Ao , A1, A2,A3, A4,A5, AL, A7,
y); input Ao, A1, A2 , A3, A4, A5, A6, A7, So, s1, s2 ;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10,
w11; not g1(w1, s2);
not g2(w2,s1);
not g3(w3, s0);
and g4 (w4, a7, w1, w2, w3);
and g5 (w5, A6, w1, S1, So) ;
and g7 (w7, A4, w1, S1, So);
and g8 (w8, A3, S2, W2, w3);
and g9 (w9, A2 , S2, w2,
So); and g10 (w10, A1, S2,
S1, W3); and g11(w11, Ao,
S2, S1, So);
or
g12(y,w4,w5,w6,w7,w8,w9,w10,w1
1); endmodule

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Truth Table:
INPUT
OUTPUT
S2 S1 So Y
0 0 0 A0
0 0 1 A1
0 1 0 A2
0 1 1 A3
1 0 0 A4
1 0 1 A5
1 1 0 A6
1 1 1 A7

Logic diagram:

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Program 7:
Aim: Design Verilog program to implement types of De-
Multiplexer 1:4, 1:8

a)1:4 Demux
Verilog:
module demux( a, b, d, y0, y1,
y2, y3) input A, B, D;
output y0, y1, y2,
y3; wire w1, w2;
not g1(w1,a);
not g2( W2, B);
and g3(y0,d,w1,w2);
and g4(y1, w1, B, D);
and G5 (y2, A, w2, D);
and g6(y3, a, b,
d); endmodule

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Truth Table:
input Select lines outpu
t
D A B Y0 Y1 Y2 Y3
D 0 0 1 0 0 0
D 0 1 0 1 0 0
D 1 0 0 0 1 0
D 1 1 0 0 0 1

Logic Diagram:

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b)1:8
Verilog:
module demux (So, S1, S2, i, Fo, F1, F2, F3, F4, F5, F6 ,F7);
input I, So, S1, S2 ;
output F0, F1, F2 , F3, F4, F5, F6 ,F7；
wire w1, w2, w
3; not g1 (w1,
S2);
not g2(w2, S1);
not g 3(w3, So);
and g4(F0, w1,w2,w3,i);
and g 5(F1, I , w1, w2, s0);
and g6(F2, I, w1, s1, w3);
and g7 (F3 , I , w1, S, S0);
and g 8 (F4 , I, s2, w2, w3);
and g9 (F5, I, S2, w2, S0);
and g10 (F6 , I,S2 , S1, w3);
and g11 (F2, I, S2, S1, S0);
endmodule

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Truth Table:
INPUT OUTPUT
S2 S1 S0 F7 F6 F5 F4 F3 F2 F1 F0
0 0 0 0 0 0 0 0 0 0 I
0 0 1 0 0 0 0 0 0 I 0
0 1 0 0 0 0 0 0 I 0 0
0 1 1 0 0 0 0 I 0 0 0
1 0 0 0 0 0 I 0 0 0 0
1 0 1 0 0 I 0 0 0 0 0
1 1 0 0 I 0 0 0 0 0 0
1 1 1 I 0 0 0 0 0 0 0

Logic Diagram:

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Program 8:
Aim: Design Verilog program for implementing various
types of Flip- flop such as D,SR,JK
a)D -Flip
flop
Verilog:
module dff(D, C,
P,Ǫ); input D, C;
output P, Ǫ;
wire
w1,w2,w3;
not g1(w1, D);
nand g2(w2, D, C);
nand g3(w3, C, w1);
nand g4(P, w2,Ǫ);
nand g5(Ǫ, w3,
P); endmodule
Boolean
Function: Truth
Table:
INPUT OUTPUT
D C P Ǫ
0 1 0 1
1 1 1 O
X 0 P Ǫ

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Logic Diagram:

b) SR Flip-
flop
Verilog:
module sr_flip flop(S, R, C, P ,Ǫ);
input S, R, C;
output P, Ǫ;
wire W1,
W2;
nand G1(W1, S, C);
nand G2(W2, C, R);
nand G3(P, W1,Ǫ);
nand G4(Ǫ, W2, P3);
e nd module

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Truth Table:
INPUT OUTPUT
S R C P Ǫ
0 0 1 P Ǫ
0 1 1 0 1
1 0 1 1 0
1 1 1 1 1
X X 0 P Ǫ

LOGIC DIAGRAM:

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c)JK Flip-
flop
Verilog:
module jk(J, K, C, P,
Ǫ); input J, K, C;
output P, Ǫ;
wire W1,
W2;
nand G1(W1, J, C, P);
nand G2(W2, C, K, Ǫ);
nand G3(Ǫ, W1, P);
nand G4(P, W2, Ǫ);
endmodul

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Truth Table:
INPUT OUTPUT
J K C P Ǫ
0 0 1 P Ǫ
0 1 1 0 1
1 0 1 1 0
1 1 0 1 1
X X 0 P Ǫ

Logic Diagram

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Viva Questions
1. What is a logic gate?
A logic gate is a fundamental building block of digital circuits that performs a basic logical function (such
as AND, OR, NOT, etc.) on one or more binary inputs to produce a single output.

2. Explain the difference between combinational and sequential circuits.

Combinational Circuits: The output depends only on the present input (e.g., adders, multiplexers).
sequential Circuits: The output depends on both the present input and the past state (e.g., flip-flops,
registers, counters).

3. What is a flip-flop?
A flip-flop is a bistable device that stores a binary value (0 or 1). It has two stable states and is used for
storing and transferring data in sequential circuits.

4. Explain the working of an SR flip-flop.

A SR (Set-Reset) flip-flop has two inputs, Set (S) and Reset (R). When S = 1 and R = 0, the output is set to
1. When S = 0 and R = 1, the output is reset to 0. When both are 0, the output remains unchanged. The
input combination S = 1 and R = 1 is typically considered invalid.

5. What is a multiplexer (MUX)?

A multiplexer (MUX) is a combinational circuit that selects one of many inputs and forwards it to the
output based on control signals. An n-to-1 MUX has n data inputs, 1 output, and log2(n) control lines.

6. Describe the operation of a 4-to-1 multiplexer.

A 4-to-1 multiplexer has 4 data inputs (I0, I1, I2, I3), 2 control lines (S1, S0), and 1 output. The control
lines determine which input is passed to the output. For example, if S1S0 = 00, I0 is passed to the output.

7. What is a decoder?
A decoder is a combinational circuit that converts an n-bit binary input to an output corresponding to one of
2^n possible values. It is commonly used in applications like address decoding in memory.

8. What is the difference between a demux and a mux?

Multiplexer (MUX): Selects one of several inputs and routes it to a single output.

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Demultiplexer (DEMUX): Takes a single input and routes it to one of several outputs based on control
signals.

9. What is a shift register?

A shift register is a type of sequential circuit that shifts its stored data bits to the left or right on each clock
pulse, allowing data to be serially shifted in or out.

10. What is the role of a clock in sequential circuits?

The clock provides timing signals that control the transitions between states in sequential circuits, ensuring
synchronization and the proper sequencing of operations.

11. What is the difference between a register and a memory?

A register is a small, fast storage element within the CPU used for holding data temporarily during
processing, whereas memory refers to larger storage areas (such as RAM) used for storing program data
and instructions.

12. What is a bus in computer architecture?

A bus is a collection of wires that transmits data between different components of the computer system,
such as the CPU, memory, and input/output devices.

18. What is a program counter (PC)?

The program counter is a register in the CPU that holds the address of the next instruction to be fetched and
executed.

19. What is a state diagram?

A state diagram is a graphical representation of a sequential circuit showing its various states and the
transitions between states based on inputs and clock cycles.

20. What is a truth table?

A truth table is a table that shows all possible input combinations for a logic circuit and the corresponding
output values.

21. What are the differences between positive logic and negative logic?

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Positive Logic: Logic 1 represents high voltage and Logic 0 represents low voltage.
Negative Logic: Logic 1 represents low voltage and Logic 0 represents high voltage.

22. What is the significance of the ALU in a CPU?

The ALU performs arithmetic and logic operations, which are essential for computations and decision-
making in a CPU. It processes data and supports control logic.

23. What is a zero flag in a processor?

The zero flag is a status flag in the processor's status register that indicates whether the result of the last
arithmetic or logical operation was zero.

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