Interfaces in Embedded Systems

Computer Bus - Electrical connection or subsystem that transfers data between

computer components: processors, memories and peripheral devices. System bus is
composed of dozens of multiple connections (Parallel Bus) or a few single serial
channels (Serial Bus).

Interface - Electronic or optical device that allows to connect two or more devices.
Interface can be parallel or serial.

Interfaces used in Embedded Systems:

- Parallel Interface PIO (usually 8, 16 or 32 bits),
- Serial interfaces:
Universal (Serial) Asynchronous Receiver-Transmitter (UART/USART), Serial Peripheral
Interface (SPI),
Synchronous Serial Controller (SSC)
I2C, Two-wire Interface (TWI),
Controlled Area Network (CAN),
Universal Serial Bus (USB),
Ethernet 10/100 Mbits (1 Gbit),
Debug/programming interface (EIA RS232, JTAG, SPI, DBGU),
Single Wire Interface (SWI),
and more...

Universal Asynchronous Receiver/Transmitter Module

RS232 is a standard for serial communication transmission of data. The diagram shows
a typical RS232 serial communication setup.
DTE (Data Terminal Equipment): Devices such as computers, teletypewriters.

DCE (Data Circuit-terminating Equipment): Devices like modems that provide a path for
data.

Data flow:
1. The teletype (DTE) sends data to the modem (DCE) using RS232.
2. The modem then sends this data over a phone line to another modem (DCE).
3. The receiving modem sends the data to another teletype (DTE) using RS232.

UART (Universal Asynchronous Receiver/Transmitter) is a hardware communication

protocol that uses asynchronous serial communication. This slide likely relates to
how data is transmitted and received in UART communication.

A shift register is used to hold the data to be transmitted or received. The shift
register takes parallel data (D0-D7) and shifts it out serially on the TxD line (for
transmission). Conversely, for receiving data, it takes serial data from the RxD line and
converts it back to parallel data.

These slides collectively illustrate the process of serial communication using RS232
standard and how UART transceivers use shift registers to manage data transmission
and reception.

Slide 56 explicitly shows RS232 in a typical serial communication setup involving

modems and teletype devices.

Slide 57 details the UART transceiver mechanism, which can operate over an RS232
interface but does not specifically label the RS232 standard in the diagram. The
principles of serial data transmission shown in slide 57 are applicable to RS232
communication.

Slide 58: Data Frame of UART (1)

1. Asynchronous 8-bit Waveform Example:

o The slide shows an example of an 8-bit data transmission using UART.
2. Data Representation:
o The data being transmitted is H'25 which is B'00100101' in binary.
o H'25 is hexadecimal representation, and B'00100101' is binary
representation.
3. UART Frame Structure:
o Start Bit: The frame starts with a 'Start bit' which indicates the beginning
of the data frame. It is typically a low voltage level (space).
o Data Bits: Following the start bit, there are 8 data bits (D0 to D7) that
represent the actual data being transmitted. Here, the bits are 1, 0, 1, 0, 0,
1, 0, 0 from D0 to D7.
o Stop Bit: The frame ends with one or more 'Stop bits' which indicate the
end of the data frame. It is typically a high voltage level (mark).
4. Mark and Space:
o 'Mark' refers to the idle state (usually high voltage).
o 'Space' refers to the active state (usually low voltage).

Slide 59: Data Frame of UART (2)

1. Waveform Diagram:
o The slide shows the actual waveform of the data being transmitted over
time.
o The waveform corresponds to the binary data 01001011.
2. Waveform Explanation:
o Start Bit: The transmission begins with a start bit (low voltage level).
o Data Bits: The data bits are transmitted in the following order: LSB (least
significant bit) first. In this case, the bits are 1, 0, 1, 0, 0, 1, 0, 0.
o Stop Bit: The transmission ends with a stop bit (high voltage level).
3. Voltage Levels:
 oThe diagram shows different voltage levels corresponding to the mark
(high voltage) and space (low voltage).
4. Time Representation:
o The x-axis represents time, showing how the data is transmitted
sequentially.
o Each bit is transmitted for a specific duration determined by the baud
rate.

Summary:

• These slides illustrate how data is transmitted using UART in an asynchronous

manner.
• Slide 58 shows the structure of the UART frame, including start bit, data bits, and
stop bit.
• Slide 59 shows the corresponding waveform for the transmission of a specific 8-
bit data 01001011.
• The process involves converting parallel data to a serial format, transmitting it bit
by bit, and then converting it back to parallel data at the receiving end.

Synchronous Transmission (Top Diagram)

1. Clock Signal:
o In synchronous transmission, a clock signal is sent along with the data.
o The clock signal is used to synchronize the transmitter and receiver.
2. Data Transmission:
o The data bits are sent in a continuous stream.
 oThe clock signal ensures that both the transmitter and receiver are
synchronized, meaning they know exactly when to sample the data bits.
3. Example:
o The diagram shows a transmitter sending data bits (0 1 1 0 0 1 0 1 0 1 1 0
1) along with a clock signal.
o The receiver uses the clock signal to correctly interpret the timing of each
data bit.

Asynchronous Transmission (Bottom Diagram)

1. Internal Clock:
o In asynchronous transmission, there is no external clock signal sent along
with the data.
o Instead, both the transmitter and receiver have their own internal clocks.
o These clocks must run at a similar reference frequency to ensure proper
timing.
2. Data Transmission:
o Data is sent in frames consisting of a start bit, data bits, and a stop bit.
o The start bit indicates the beginning of the frame, and the stop bit
indicates the end.
o The receiver's internal clock is used to sample the incoming data bits
based on the timing derived from the start bit.
3. Synchronization:
o Synchronization happens at the start of each data frame using the start
bit.
o The internal clocks of the transmitter and receiver must be calibrated to
have similar frequencies to maintain proper timing during the frame.
4. Example:
o The diagram shows a transmitter sending data bits (0 1 1 0 0 1 0 1 0 1 1 0
1) with its internal clock.
o The receiver uses its internal clock to sample and interpret the data bits
correctly, relying on the start bit for initial synchronization.

Summary

• Synchronous Transmission: Utilizes an external clock signal to keep the

transmitter and receiver in sync, allowing for continuous data transmission
without start and stop bits.
• Asynchronous Transmission: Relies on start and stop bits for synchronization
within each data frame and uses internal clocks in both the transmitter and
receiver that need to be running at similar frequencies.
Slide 62: Null-Modem Cable EIA 232

1. Null-Modem Cable:
o A null-modem cable is used to connect two DTE (Data Terminal
Equipment) devices directly without a DCE (Data Circuit-terminating
Equipment) such as a modem.
o The diagram shows the wiring connections for a DB9 female connector.
2. Pin Connections:
o Pin 2 (Rx) of Connector 1 is connected to Pin 3 (Tx) of Connector 2.
o Pin 3 (Tx) of Connector 1 is connected to Pin 2 (Rx) of Connector 2.
o Pin 5 (Signal Ground) is connected to Pin 5 (Signal Ground) of both
connectors.
o This setup allows for direct communication between two devices by
swapping the transmit and receive lines.

Slide 63: Hardware Flow Control

1. Flow Control Signals:

o DTR (Data Terminal Ready): Indicates that the DTE is ready to
communicate.
o DSR (Data Set Ready): Indicates that the DCE (modem) is ready to
communicate.
o RTS (Request to Send): Indicates that the DTE wants to send data.
o CTS (Clear to Send): Indicates that the DCE is ready to receive data.
o TxD (Transmit Data): The actual data being transmitted.
2. Line State and Remarks:
 o The table explains the line states for each signal and their corresponding
remarks.
o For example, DTR being high indicates that the computer (terminal) is
ready, and RTS being high indicates a request to send data.

Slide 64: Null-Modem Cable EIA 232 with Hardware Flow Control

1. Additional Pin Connections for Flow Control:

o The diagram includes connections for flow control signals in addition to
the basic data and ground connections.
o Pin 2 (Rx) of Connector 1 to Pin 3 (Tx) of Connector 2, and vice versa.
o Pin 6 (DTR) of Connector 1 to Pin 4 (DSR) of Connector 2, and vice versa.
o Pin 7 (RTS) of Connector 1 to Pin 8 (CTS) of Connector 2, and vice versa.
o This setup supports hardware flow control to manage data transmission
between devices.

Slide 65: Voltage Levels of EIA RS232

1. Processor Output:
o The diagram shows the logic levels used by a processor for UART
communication.
o Logic '1' is represented by +5V or +3.3V, and Logic '0' is represented by 0V.
o This is a typical CMOS or TTL logic level.
2. EIA RS232 Voltage Levels:
o The RS232 standard defines different voltage levels for signaling.
o Mark (Logic '1') is represented by a voltage between -3V and -25V
(typically -10V).
o Space (Logic '0') is represented by a voltage between +3V and +25V
(typically +10V).
o The waveform diagram illustrates the voltage levels during data
transmission.

Summary

• Slide 62 shows a basic null-modem cable connection for direct communication

between two DTE devices using RS232.
• Slide 63 explains hardware flow control signals used in RS232 communication to
manage data transmission.
• Slide 64 extends the null-modem cable connections to include hardware flow
control signals.
• Slide 65 explains the voltage levels used in RS232 communication compared to
processor output levels.

Mobile phone interfaces with an RS232 serial port using a voltage level translator.
RS232 voltage levels (typically ±12V) are different from the voltage levels used by
modern digital devices (usually 5V or 3.3V).
MAX232: A voltage level translator for devices operating at 5V.
MAX3232: A voltage level translator for devices operating at 3.3V.
These ICs (integrated circuits) convert the voltage levels between RS232 and TTL
(Transistor-Transistor Logic) levels.

Slide 66 explains the need for voltage level translation when interfacing modern digital
devices with RS232 ports and introduces ICs like MAX232 and MAX3232 for this
purpose.

Slide 67 lists various software tools that can be used for RS232 communication,
highlighting their use in setting up and managing serial connections:
Hyper terminal
Minicom
ssh
Terminal

Low-Power Universal Asynchronous Receiver Transmitter (LPUART)

Slide 70: Features of LPUART

1. Full-duplex asynchronous data transmission:

o Supports simultaneous two-way communication.
o Compatible with the RS232 standard.
2. Programmable data packet size:
o Allows configuration of data packets to be 7, 8, or 9 bits.
3. Programmable data order:
o Data can be sent in either Least Significant Bit (LSB) first or Most
Significant Bit (MSB) first.
4. Configurable stop bits:
o The number of stop bits can be set to 1 or 2.
o Parity bit configuration is also possible.
5. Single-wire half-duplex communication support:
o Supports communication where the transmitter and receiver share the
same signal path, but only one can communicate at a time.
6. Limited power consumption:
 oEfficient power usage, even available in STOP mode to conserve power.
7. Hardware support for Direct Memory Access (DMA):
o Facilitates high-speed data transfer without CPU intervention.
8. Swappable Tx/Rx pin configuration:
o Transmit (Tx) and Receive (Rx) pins can be reconfigured as needed.
9. Hardware flow control:
o Supports flow control for modems and RS-485 transceivers with Driver
Enable (DE) control.
o Supports hardware flow control signals: Clear to Send (CTS) and Request
to Send (RTS).

Slide 71: Additional Features of LPUART

1. Transfer detection flags:

o Receive buffer full: Indicates that the receive buffer is full.
o Transmit buffer empty: Indicates that the transmit buffer is empty.
o Busy and end of transmission flags: Indicate whether the UART is
currently transmitting or has finished transmission.
2. Parity control:
o Can transmit a parity bit to help detect errors.
o Checks the parity of received data bytes to ensure data integrity.
3. Error detection flags:
o Overrun error: Indicates data loss because the receiver buffer was full
when new data arrived.
o Noise detection: Detects unwanted interference in the received signal.
o Frame error: Indicates that the received frame does not have a valid stop
bit.
o Parity error: Indicates that the received data byte does not match the
expected parity.
4. Fourteen interrupt sources with flags:
o Provides multiple interrupt sources for various conditions and flags to
indicate their status.

Summary

• These slides list the comprehensive features of the LPUART module, highlighting
its versatility, power efficiency, and robust communication capabilities.
• The features cover various aspects of UART communication, including data
configuration, flow control, error detection, and power management.
• Understanding these features can help in configuring and utilizing the LPUART
effectively for various applications requiring serial communication
Data Frame:

8-bit Word Length (M = 00): This specifies that the data frame consists of 8 data bits.

1 Stop Bit: Indicates the frame ends with a single stop bit.

Possible Parity Bit: Optional bit used for error checking.

Transmission Elements:
Start Bit: Indicates the beginning of a data frame.
Data Bits (Bit0 to Bit7): The actual data being transmitted.
Stop Bit: Indicates the end of the data frame.
Idle Frame: Period when no data is being transmitted.
Break Frame: Special frame to signal a break condition, often used to indicate an error
or a reset condition.

Timing Diagram:
Clock: Represents the timing signal used to synchronize data transmission.
Data Frame: Shows the sequence of bits (start bit, data bits, stop bit) transmitted over
time.
Idle and Break Frames: Illustrate periods of no data transmission and break conditions.

Clock for LPUART is RCC_APB1ENR2.

Data Structures
Stack or LIFO (Last-In, First-Out) – abstract data type and data structure. A stack can
have any abstract data type as an element, but it is characterized by only two
fundamental operations: push and pop. The push operation adds to the top of the list,
hiding any items already on the stack, or initializing the stack if it is empty. The pop
operation removes an item from the top of the list, and returns this value to the caller. A
pop either reveals previously concealed items, or results in an empty list.

FIFO (First In, First Out) – a linear buffer, the opposite structure to stack. The first
element placed into FIFO is immediately transferred to the end of the queue. Therefore
the first element stored in FIFO is supposed to be processed first.