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14 views

Module Counter

Uploaded by

22119246
Copyright
© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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module Counter_mod10(

input wire clk, reset,


output wire [3:0] q
);
// signal declaration
reg [3:0] r_reg=0;
wire [3:0] r_next;
// body, register
always @(posedge clk, negedge reset)
if (!reset)
r_reg <=0;
else
r_reg<=r_next;
// next state logic
assign r_next = (r_reg>8)?0:r_reg+1;
// output logic
assign q=r_reg;
endmodule
wire clk_i;
Chiaxung_1hz IC1(clk_50m, clk_i);
Counter_mod10 IC2(clk_i, reset, led);
assign clk_1hz = clk_i;
endmodule

begin
// Initialize Inputs
clk = 0;
reset = 0;
#20;
reset=1;
end
always
begin
clk = ~clk;
#10;
end
endmodule

NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;


NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

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