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15EC32T - DIGITAL ELECTRONICS

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Unit-1 Combinational logic circuits

1.1 Combinational digital circuit: Combinational digital Circuits consist of inputs and
outputs. The logic gates are combined in such a way that the output state depends entirely on the
input states. Combinational logic circuits have no memory, timing, there operation is
instantaneous. A combinational logic circuit performs an operation assigned logically by a
Boolean expression or truth table. In other words a combinational logic circuit implement logical
functions where its outputs depend only on its current combination of input values.

Examples of common combinational logic circuits include: half adders, full adders, multiplexers,
demultiplexers

Fig1.1: Block diagram of a Combinational circuit.

1.2 Multiplexers

Difination: Multiplexer(MUX) is a combinational logic circuit the basic multiplexer has several
data inputs lines(2n) and single output line. The selection of a particular input line is controlled
by a set of selection lines(n). Multiplexer is also known as data selector.

Fig1.2: Block diagram of multiplexer 2n:1

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2:1 Multiplexer: 2:1 multiplexer is a combinational circuit that uses one control line (S) to
connect one of two input data lines (D0 or D1) to a single output (Y). Only one of the input data
lines can be connected to the output of the multiplexer at any given time.

Truth table:

Select input(S) Output(Y)

0 D0

1 D1

e i he e e e i f i e e i

Logic Diagram:

Fig1.3: Logic Diagram for 2:1 MUX

Fig1.3 shows the logic diagram for2:1 multiplexer. The logic circuit consists of two And gates
A1 and A2, an OR gate O1 and a Not gate N1. D0 and D1 are input lines and S is the select line.
If select line S=0 then input D0 will be selected to output Y else S=1 then input D1 will be
selected to output Y.

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Applications:
 Data selection.
 Data routing.
 Waveform generation.
 Parallel to serial conversion.
 Analog to digital converter and digital analog converter.

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 Frequency multiplexing system.

 Logic function generation.
Multiplexers to implement logic gates:
Using 2 to 1 MUX we can implement the following 2-input gates:OR ,AND, NOT,
NOR,NAND, XOR ,XNOR.

OR GATE

AND GATE

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NOT GATE

X Z
0 1
1 0

NOR GATE

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NAND GATE

XOR GATE

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XNOR GATE

Expression for XNOR

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Simple sum-of-product equations:

Consider the function:

Expanding to standard sum of products form:

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Note: In the above e e i i ed

The resulting multiplexer implementation is:

TRUTH TABLE

INPUTS OUTPUT
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
I e e he f ci F ∑ , ,3,6,8, , , , 3, 4 i g8 .

Truth table

INPUTS OUTPUT
A B C D F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1

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0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Fig: Implementation table and block diagram

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List of IC multiplexers and their features:

S.No. IC No. Function Output State

1 74157 Quad 2:1 mux. Output same as input given

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2 74158 Quad 2:1 mux. Output is inverted input

3 74153 Dual 4:1 mux. Output same as input

4 74352 Dual 4:1 mux. Output is inverted input

5 74151A 8:1 mux. Both outputs available (i.e., complementary outputs)

6 74151 8:1 mux. Output is inverted input

7 74150 16:1 mux. Output is inverted input

Realization of higher-order multiplexer using lower-order multiplexer ICs:
1. Realization of 4:1 mux using 2:1 mux given below

Fig1.4: 4:1 MUX using 2:1MUX

Fig1.4 shows the implementation of 4:1 multiplexer by using three 2:1 multiplexer, 2 select lines
S0 and S1 they are connected in parallel, 4 inputs I0,I1,I2,I3 are connected to two 2:1
multiplexer and the outputs of this multiplexers are connected as input to the next 2:1
multiplexer.

2. Realization of 16:1 mux using two 8:1 mux and one 2:1mux given below

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Fig 1.5: 16:1 mux using two 8:1 mux and one 2:1 mux
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1.3 Demultiplexer: The demultiplexer is a combinational logic circuit which takes one single
input data line and then connects it to any one of the output lines one at a time depending on
select lines.

Fig1.6: Block diagram of Demultiplexer

1:2 Demultiplexer: 1:2 demultiplexer consists of one input line, two output lines and one
select line. The signal on the select line helps to connects the input to one of the two outputs. The
figure below shows the block diagram of a 1:2 demultiplexer.

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Fig 1.7: Block diagram of 1:2 demultiplexer

In the above figure, there are only two possible ways to connect the input to output lines, When
the select input is low, then the input will be passed to Y0 and if the select input is high then the
input will be passed to Y1.

Truth Table:

Expression: The e e e i f e i e e i d

Realization:
From the above truth table, the logic diagram of this demultiplexer can be designed by using two
AND gates and one NOT gate as shown in below figure. When the select lines S=0, AND gate
A1 is enabled while A2 is disabled.

Then, the data from the input flows to the output line Y1. Similarly, when S=1, AND gate A2 is
enabled and AND gate A1 is disabled, thus data is passed to the Y0 output.

Fig 1.8: Logic diagram of 1:2 demultiplexer

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List the IC’s of demultiplexers and their features:

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S.No. IC No. Function

1 74139 Dual 1:4 demux.
3 74156 Dual 1:4 demux.
4 74138 1:8 demux.
5 74238 1:8 demux.

Demultiplexer applications:

 Serial to Parallel Converter.

 Arithmetic Logic Unit.
 Decoder.
 Data distributer.
 Time division multiplexing at the receiving end as a data separator.
 Implement Boolean expressions.

1.4 Decoders and encoders:

Decoder: Decoders are circuits with two or more inputs and one or more outputs, resulting by
combining various types of gates. Their basic function is to accept a binary word (code) as an
input and create a different binary word as an output. Decoder has n- input lines and 2n output
lines.

Fig1.9(a): Block diagram of encoder

Encoder: An encoder is a digital circuit that performs inverse operation of a decoder. An

encoder has 2n input lines and n- output lines.

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Fig1.9(b): Block diagram of encoder

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Decimal-to-BCD encoder: A decimal to bcd encoder has 10 input lines D0 to D9 and 4

output lines Y0 to Y3. Below is the truth table for a decimal to bcd encoder.

Fig1.10: Block diagram of decimal to BCD encoder

Truth Table:

From the truth table, the outputs can be expressed by following Boolean Function.

Note: Below boolean functions are formed by ORing all the input lines for which output is 1. For
instance Y0 is 1 for D1, D3, D5, D7 & D9 input lines.

Y0 = D1 + D3 + D5 + D7 + D9
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Y1 = D2 + D3 + D6 + D7
Y2 = D4 + D5 + D6 + D7
Y3 = D8 + D9
The decimal to bcd encoder can therefore be implemented with OR gates whose inputs are
determined directly from truth table as shown in the image below.

Fig1.11: Logic diagram of decimal to BCD encoder

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BCD-to-Decimal decoder:

Fig1.12: Block diagram of BCD to decimal decoder

Truth table:

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Logic diagram:

Fig1.13: Logic diagram of BCD to decimal decoder

The above figure (1.12 and 1.13) shows the schematic diagram of BCD to decimal decoder. It
has four inputs and decimal outputs, truth table for BCD to decimal decoder as shown above.

Identification of different decoder and encoder ICs:

IC Number Function
74138 3:8 Decoder
74139 Dual 2:4 Decoder

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7442 BCD to Decimal decoder

7447 BCD to 7-Segment decoder
74147 Decimal to BCD encoder
74148 8-Input priority encoder

BCD to 7-segment decoder: 7-segment LED (Light Emitting Diode) or LCD (Liquid
Crystal Display) type displays, provide a very convenient way of displaying information or
digital data in the form of numbers, letters or even alpha-numerical characters.
Typically 7-segment displays consist of seven individual colored L ’ (called the segments),
within one single display package. In order to produce the required numbers from 0 to 9 on the
display the correct combination of LED segments need to be illuminated.
A standard 7-segment display generally has 8 input connections, one for each segment and one
that acts as a common terminal. some single displays have also have an additional input pin to
display a decimal point in their lower right or left hand corner.
In electronics there are two important types of 7-segment LED digital display.
 The Common Cathode Display (CCD) – In the common cathode display, all the
cathode connections f he L ’ e j i ed ge he gic “ ” g d he
i divid eg e ei i ed by ic i f “HIGH”, gic “ ” ig
the individual Anode terminals.
 The Common Anode Display (CAD) – In the common anode display, all the anode
con ec i f he L ’ e j i ed ge he gic “ ” d he i divid
segments are illuminated by connecting the individual Cathode terminals to a
“LOW”, gic “ ” ig

Fig 1.14: Common cathode and common anode

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The above figure 1.14 shows the electrical connection of the individual diodes for a common
cathode display and a common anode display and by illuminating each light emitting diode
individually, they can be made to display a variety of numbers or characters.

7-Segment Display Format:

Fig1.15: Seven segment display format

Truth table:

From the above truth table using K-map simplified expression for each segment is given below.

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f

Logic Diagram:

Fig 1.16: Logic diagram

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4-bit priority encoder: A priority encoder is a circuit or algorithm that compresses

multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the
binary representation of the ordinal number starting from zero of the most significant input bit.
They are often used to control interrupt requests by acting on the highest priority request. It
includes priority function. If 2 or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.

Truth Table:

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Logic diagram:

Fig 1.17: Logic diagram of 4-bit priority encoder

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Applications:

 Priority encoder can be used for Keyboard Encoder

 Positional Encoders
 Navigation
 Interrupt Requests

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Unit 2: Basic sequential circuits

Introduction to sequential circuits: Sequential circuits use present input variables and
previous input variables by storing the information and putting back into the circuit on the next
clock cycle.

The figure shows sequential circuits are made from combinational logic and storage elements.

There are two types of input to the combinational logic, External inputs which come from
outside the circuit design and are not controlled by the circuit. Internal inputs which are a
function of a previous output states.

Comparison of combinational and sequential

Combinational Logic Circuits Sequential Logic Circuits

Output is a function of clock, present
Output is a function of the present inputs (Time
inputs and the previous states of the
Independent Logic).
system.
Memory is used to store the present states
Does not use memory elements to store data (state). that are sent as control input (enable) for
the next operation.

It involves feedback from output to input

It does not require any feedback. It simply outputs the
that is stored in the memory for the next
input according to the logic designed.
operation.
Used for storing data (and hence used in
Used mainly for Arithmetic and Boolean operations.
RAM).

Flip flops are the elementary building

Logic gates are the elementary building blocks.
unit.
Clocked (Triggered for operation with
Independent of clock.
electronic pulses).

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Example: Adder [1+0=1; Depends only on present Example: Counter [Previous O/P
inputs i.e., 1 and 0]. +1=Current O/P; Depends on present
input as well as previous state].

Definition of clock and triggering

Clock:
A digital clock signal is basically a square wave or rectangular pulse train voltage similar to
the one shown below.

The clock signal has only two levels, one is zero and the other one is high.

Clock Pulse Transition

The movement of a trigger pulse is always from a 0 to 1 and 1 to 0 of a signal. Thus it takes
two transitions in one clock pulse. When it moves from 0 to 1 it is called a positive transition
and when it moves from 1 to 0 it is called a negative transition.

Fig 2.1: Clock pulse transition.

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Triggering

The output of a flip flop can be changed by bringing a small change in the input signal. This
small change can be done with the help of a clock pulse or commonly known as a trigger
pulse. When such a trigger pulse is applied to the input, the output changes and thus the flip
flop is said to be triggered.

Types of triggering and their symbolic representation in logic circuits

There are four types of pulse-triggering methods. They differ in the manner in which the
electronic circuits respond to the pulse. They are

High Level Triggering

When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is
used. It is shown in the figure.

Low Level Triggering

When a flip flop is required to respond at its LOW state, a LOW level triggering method is
used. Low level trigger is indicated by bubble as shown in the figure.

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Positive Edge Triggering

When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge
triggering method is used. Positive edge triggering is indicated by triangle and its shown in
the figure.

Negative Edge Triggering

When a flip flop is required to respond during the HIGH to LOW transition state, a
NEGATIVE edge triggering method is used. Negative edge triggering is indicated by bubble
with triangle and its shown in figure.

2.2 Flip-flops

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A flip-flop is a circuit that has two stable states and can be used to store binary information
(0/1). Flip-flop is a bistable multivibrator. The circuit can be made to change the state by
applying a clock pulse.

Types of flip-flops

Flip-flops can be divided into common types:

 SR (Set-Reset) Flip flop.

 D ( Delay) Flip flop.
 T (Toggle) Flip flop.
 JK Flip flop.
Clocked SR Flip Flop
Logic diagram of SR Flip Flop using NAND Gates

Fig 2.2: Logic diagram of SR flip flop.

Truth table of R S Flip Flop

Timing diagram for SR inputs

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The SR flip-flop consists of basic flip-flop circuit along with two additional NAND gates and
a clock pulse generator. The clock pulse acts as an enable signal for the two inputs. The output
of the gates 3 and 4 remains at logic “1" until the clock pulse input is at 0.

Operation
Let’s assume S=1, R=0 and CP=1. The set state is reached at this condition and since the clock
pulse is 1, information from S and R is allowed to reach output only when clock pulse goes to
1.So when S=1, R=0 &CP=1, both the inputs to the gate3 are 1 and hence its output is 0. This
information is passed to gate1. Since one of the inputs of gate1 is 0, the output Q=1. Since
R=0, the output o tained at Q=0.

Conclusion: hen S=1, R=0 CP=1 = Q=1 and Q=0.

Now to change to reset state, the inputs must be S=0, R=1 & CP=1. The outputs are Q=0
Q=1.When the clock pulse returns to zero, the circuit remains in its previous state. This is
applicable to both Set and Clear states.

When CP=1, inputs S=0 &R=0, that is when both the inputs are 0, the state of the circuit does
not change.

When CP=1, S=1 & R=1, an indeterminate condition occurs because oth the outputs Q and Q
remain at 1. This is not possible because both the outputs are complementary to each other. So
it is better to avoid this condition during practice.

The truth table and timing diagram of the S R flip flop is as shown in the above.

J K flip flop

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Symbol of J K Flip-flop

Logic diagram of J K Flip flop

Fig 2.3: Logic diagram of JK flip flop.

Operation
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J K flip flop is versatile and is a widely used flip flop. The functioning of J K flip flop is same
as that of the S R flip flop in the SET,RESET and NO CHANGE conditions of operation. The
difference is that the J K flip flop has no invalid state as the S R flip flop.

J K means Jack Kilby, a Texas instrument engineer who invented IC. The two inputs of JK
Flip-flop is J (set) and K (reset). A JK flip-flop is nothing but a SR flip-flop along with
two AND gates which are connected to it.

When J=K=0

When both J and K are 0, the clock pulse has no effect on the output and the output of the flip-
flop is the same as its previous value. This is because when both the J and K are 0, the output
of their respective AND gate becomes 0.

When J=0, K=1

When J=0, the output of the AND gate corresponding to J becomes 0 (i.e. S=0 and R=1).
Therefore ̅ =0. This condition will reset the flip-flop. This represents the RESET state of Flip-
Flop.

When J=1, K=0

In this case, the AND gate corresponding to K becomes 0(i.e. S=1 and R=0). Therefore Q=0.
This condition will set the Flip-flop. This represents the SET state of Flip-flop.

When J=K=1

Consider the condition of CP=1 and J=K=1. This will cause the output to toggle. This toggle
operation continues until the clock pulse goes back to 0 which is called as race around
condition. Since this condition is undesirable, we have to find a way to eliminate this
condition. This undesirable behaviour can be eliminated by edge triggering of J K flip-flop or
by using master slave J K Flip-flops.

Race-around problem and Remedies

Toggling of the J K flip flop is more than once in one clock period when both J& K inputs are
high is called race around condition.

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Steps to avoid racing condition in J K Flip flop:
If the Clock On or High, time is less than the propagation delay of the flip flop then racing can
be avoided. This is done by using edge triggering rather than level triggering.

If the flip flop is made to toggle over one clock period then racing can be avoided. This
introduced the concept of Master Slave J K flip flop.

MS flip-flop

Logic diagram of master slave J K flip flop

Fig 2.4: Logic diagram of master slave JK flip flop.

Logic symbol of master slave J K flip flop

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The inputs J and K are connected to the gated “master” flip flop which “locks” the input
condition while the clock (clk) input is at logic level “1”. As the clock input of the “slave” flip
flop is the inverse (complement) of the “master” clock input, the “slave” flip flop does not
toggle. The outputs from the “master” flip flop are only seen y the gated “slave” flip flop
when the clock input goes to logic level “0”.

hen the clock is “LO ”, the outputs from the “master” flip flop are latched and any
additional changes to its inputs are ignored. The gated “slave” flip flop responds to the state of
its inputs passed over y the “master” section.

Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are
fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the
same inputs are reflected on the output of the “slave” making this type of flip flop edge or
pulse-triggered.

The circuit accepts input data when the clock signal is “HIGH”, and passes the data to the
output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is
a synchronous device as it only passes data with the timing of the clock signal.

D flip-flop( Delay flip flop)

The S R and J K flip flops have two data inputs. To store a single bit of information two data
signals has to be generated which is a disadvantage in many applications. Further in S R flip
flop the forbidden condition occurs. To overcome these disadvantages D flip flop is
introduced.

The D flip-flop is called delay flip-flop because the input D is delayed from getting to the
output Q by one clock pulse. The D flip-flop has two inputs including the Clock pulse. D and
clock are the two inputs of the D flip-flop.

The D input of the flip-flop is directly given to S, and the complement value is given to the R
as an input. Similar to S R flip-flop, the outputs of gate 3 and 4 remain at logic “1" until the
clock pulse applied is 0. The value of D will not affect the circuit until clock is in 0 (low)
values. The value of D is sampled only when clock goes from 0 to 1. As the value of clock
changes to 1, the value of D is sampled and the information is passed to the output.

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When clock=1, and if D=1, the output of gate 3 goes to 0 and this makes the output Q=1, Q=0.
This is the set state of the D flip-flop. When =0, the output Q=1 and Q=0, which is the reset
state of the Flip-flop.

Both S and R are given complementary values they can never be 1 at the same time. Thus we
can avoid the indeterminate state that occurs in S R flip-flop.

When the clock pulse returns to zero, the previous state of the output is maintained (or) the
output does not change its state unless it is enabled again by clock pulse.

Fig 2.5: Logic diagram D of flip flop.

T flip flop
T flip-flops are similar to J K flip-flops. T flip-flops are single input version of J K flip-flops.
This modified form of J K flip-flop is obtained by connecting both J and K inputs together.
This flip-flop has only one input along with clock pulse. These flip-flops are called T flip-flops
because of their ability to complement its input (i.e. Toggle). Hence they are called as Toggle
flip-flop.

When T=1 and clk=1, the flip-flop complements its output, regardless of the present state of
the flip-flop. In this case the next state is the complement of the present state.

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When T=0, there is no change in the state of the flip-flop, the next state is same as the present
state of the flip-flop.

Logic symbol of T flip flop

Fig 2.6: Logic diagram T flip flop.

Applications

 It is useful for constructing binary counters.

 Frequency dividers.

 General binary addition devices.

Relevance of asynchronous inputs to flip-flops

The normal data inputs to a flip flop (D, S and R, or J and K) are referred to
as synchronous inputs because they have effect on the outputs (Q& ̅ ) in synchronous with the
clock signal transitions.

Asynchronous inputs can set or reset the flip-flop regardless of the status of the clock signal.
They are called preset and clear.

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When the preset input is activated, the flip-flop will be set (Q=1, ̅ =0) regardless of any of the
synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset
(Q=0, ̅ =1), regardless of any of the synchronous inputs or the clock.

If preset and clear inputs are activated, we get an invalid state on the output, where Q and Q
go to the same state.

Asynchronous inputs, just like synchronous inputs, can be active-high or active-low. If they
are active-low, there will be an inverting bubble at that input on the block symbol, just like the
negative edge-trigger clock inputs.

Sometimes the designations “PRE” and “CLR” will e shown with inversion bars above them,
to further denote the negative logic of these inputs.

Sl
IC’s Type
No
1 7473 Dual J-K flip-flop, asynchronous clear

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Dual D positive edge triggered flip-flop, asynchronous

Identify 2 7474
preset and clear
and list
flip-flop 3 7475 4-bit D latch ICs.
4 7476 Dual J-K flip-flop, preset and clear

Note: For further Flip Flop ICs refer Digital Electronics Practice Using Integrated Circuits by R
P Jain and M M S Anand.

Timer 555:
Internal diagram of IC 555

IC timer 555 is one of the most commonly used general-purpose linear integrated circuits. The
simplicity with which monostable and astable multivibrator circuits can be configured around
this IC is one of the main reasons for its wide use. Figure (a) shows the internal schematic of
timer IC 555. It comprises of two op-amp comparators, a flip-flop, a discharge transistor, three
identical resistors and an output stage. The resistors set the reference voltage levels at the non
inverting input of the lower comparator and the inverting input of the upper comparator at
(+VCC/3) and (+2VCC/3). The outputs of the two comparators feed the SET and RESET inputs
of the flip-flop and thus decide the logic status of its output and subsequently the final output.
The flip-flop complementary outputs feed the output stage and the base of the discharge
transistor. This ensures that when the output is HIGH the discharge transistor is OFF, and when
the output is LOW the discharge transistor is ON. Different terminals of timer 555 are designated
as ground (terminal 1), trigger (terminal 2), output (terminal 3), reset (terminal 4), control
(terminal 5), threshold (terminal 6), discharge (terminal 7) and +VCC (terminal 8).

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Fig 2.7: Internal diagram IC555 timer.

Astable Multivibrator using Timer IC 555

Figure 2.8 shows the basic 555 timer based astable multivibrator circuit. Initially, capacitor C is
fully discharged, which forces the output to go to the HIGH state. An open discharge transistor
allows the capacitor C to charge from +VCC through R1 and R2. When the voltage across C
exceeds +2VCC/3, the output goes to the LOW state and the discharge transistor is switched ON
at the same time.

Capacitor C begins to discharge through R2 and the discharge transistor inside the IC. When the
voltage across C falls below +VCC/3, the output goes back to the HIGH state. The charge and
discharge cycles repeat and the circuit behaves like a free-running multivibrator. Terminal 4 of
the IC is the RESET terminal usually connected to +VCC. If the voltage at this terminal is driven
below 0.4 V, the output is forced to the LOW state, overriding command pulses at terminal 2 of
the IC. The HIGH-state and LOW-state time periods are governed by the charge (+VCC/3 to
+2VCC/3) and discharge (+2VCC/3 to +VCC/3) timings. These are given by the equations

HIGH-state time period THIGH = 0.693(R1+R2)C

LOW-state time period TLOW = 0.693 R2C

The relevant waveforms are shown in Fig. (b). The time period T and frequency f of the output
waveform are respectively given by the equations
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Time period T = 0. 69 (R1+2R2)C

Frequency f = 1/ 0 .69 (R1+R2) C

Fig 2.8: Astable Multivibrator

Fig 2.9: Waveform of Astable Multivibrator

Monostable Multivibrator Using Timer IC 555
Figure 2.9 shows the basic monostable multivibrator circuit configured around timer 555. A
trigger pulse is applied to terminal 2 of the IC, which should initially be kept at +VCC. A HIGH
at terminal 2 forces the output to the LOW state. A HIGH-to-LOW trigger pulse at terminal 2
holds the output in the HIGH state and simultaneously allows the capacitor to charge from
+VCC through R. Remember that a LOW level of the trigger pulse needs to go at least below
+VCC/3. When the capacitor voltage exceeds +2VCC/3, the output goes back to the LOW state.
We need to apply another trigger pulse to terminal 2 to make the output go to the HIGH state
again. Every time the timer is appropriately triggered, the output goes to the HIGH state and
stays there for the time it takes the capacitor to charge from 0 to +2VCC/3. This time period,
which equals the monoshot output pulse width, is given by the equation

T = 1.1 RC

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Fig 2.9: Monostable Multivibrator

Fig 2.10: Waveforms of Monostable Multivibrator.

2.52 Flip-flop as Bistable Multivibrator

Fig 2.11: Flip flop as bistable multivibrator.

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Bistable multivibrator circuit is one in which both LOW and HIGH output states are stable.
Irrespective of the logic status of the output, LOW or HIGH, it stays in that state unless a change
is induced by applying an appropriate trigger pulse.

Figure 2.11 shows the basic bistable multivibrator circuit. The operation of a bistable
multivibrator is identical to that of a flip-flop. In the circuit arrangement it can be proved that
both transistors Q1 and Q2 cannot be simultaneously ON or OFF. If Q1 is ON, the regenerative
feedback ensures that Q2 is OFF, and when Q1 is OFF, the feedback drives transistor Q2 to the
ON state. The output VC1 is complement of VC2 and vice versa.

For Operation of bistable multivibrator refer link Courtesy-

https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ve
d=0ahUKEwjl-
KaXgYfRAhUMKo8KHaCNA1kQFgghMAE&url=https%3A%2F%2Fround-lake.dustinice.workers.dev%3A443%2Fhttp%2Fwww.falstad.com%2Fcirc
uit%2Fe-multivib-bi.html&usg=AFQjCNE2Si9DNpqjOGAlV-KuZWCVoFE-uw

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Unit 3: Registers and counters

Registers: Registers are groups of flip-flops (FF), where each flip-flop(FF) is capable of storing
one bit of information. An n-bit register is a group of n flip-flops. The basic function of a register
is to hold information in a digital system and make it available to the logic elements for the
computing process. (OR) A group of cascaded flip-flops used to store related bits of information
is known as a register.

Classification of registers: Registers can be classified depending on input/output and

application.

Depending on input/output
SISO, serial input and serial output
SIPO, serial input parallel output
PISO, parallel input serial ouput
PIPO, parallel input parallel output
Depending on application
Shift register (SISO)
Storage Register (PIPO)
Serial in Serial out Shift Register(SISO): Serial in Serial out Shift Register (SISO), it is a type
of register which accepts data serially, one bit at a time at the single input line, and shifted to
next flip flop serially. The output is also obtained on a single output line in a same serial fashion.
Now depending upon the data shift within the register, it may be shifted from left to right
using shift-left register, or shifted from right to left using shift-right register.

4-bit SISO: A basic four-bit shift register can be constructed using four D flip-flops, as shown
below. The operation of the circuit is as follows. The register is first cleared, forcing all four
outputs to zero. The input data is then applied sequentially to the D input of the first flip-flop on
the left (FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data
word to be 1011. The least significant bit of the data has to be shifted through the register from
QA to QD.

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Fig3.1: SISO shift register

For example, consider that all the stages are reset and a logical input 1011 is applied at the serial
input line connected to stage A. and see the below table that how the data shifted from one flip
flop to other and finally get the output from D flip flop.

After fourth clock pulse we will get first input after next three clock pulse the complete input
(1011) which we feed at flip flop A will out from flip flop D. Now in bellow see the waveform
of 4 bit serial shift register.

Serial in Parallel out Shift Register(SIPO): Serial in Serial out Shift Register (SISO), it is a
type of register which accepts data serially, one bit at a time at the single input line. The output is
obtained in a parallel fashion.

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Fig3.2:SIPO shift register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel
data output.
If a logic “1” is connected to the data input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs
still remaining LOW at logic “0”. Assume now that the data input pin of FFA has returned LOW
again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output
of FFB and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic
“1” has now moved or been “shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so
on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to
logic level “0” because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the
register. This data value can now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic “1” through the register
from left to right as follows.

Data movement operation:

Clock pulse No QA QB QC QD

0 0 0 0 0

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1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

Waveform:

Parallel in serial out Shift Register(PISO): In PISO shift register data will enter in
parallel that means at a time to all flip flop. And output will get serially. Here the data bits can be
entered parallel into the flip flops simultaneously, rather than a bit-by-bit. Lets take an example
suppose we have to save a 4-bit number (1011). Then all inputs are fed to the respective flip
flop.With single clock pulse all data are enter to all 4 flip flops. In bellow see the block diagram
of 4 bit of parallel in serial out shift register.

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Fig3.3: PISO Shift register

In the above 4 bit parallel in serial out shift register we can see, A, B, C, and D are the four
parallel data input lines and SHIFT / LOAD (SH / LD) is a control input that allows the four bits
of data at A, B, C, and D inputs to enter into the register in parallel or shift the data in serial.
When SHIFT / LOAD is HIGH, AND gates G1, G3, and G5 are enabled, allowing the data bits
to shift right from one flip flop to the other. When SHIFT / LOAD is LOW, AND gates G2, G4,
and G6 are enabled, allowing the data bits at the parallel inputs. When a clock pulse is applied,
the flip-flops with D = 1 will be set and the flip-flops with D = 0 will be reset, thereby storing all
the four bits simultaneously. The OR gates allow either the normal shifting operation or the
parallel data-entry operation, depending on which of the AND gates are enabled by the level on
the SHIFT / LOAD input.

Parallel in Parallel out Shift Register(PIPO): In PIPO shift register data will be
entered in parallel fashion that means at a time to all flip flop. And output will be taken parallel.
Here the data bits can be entered parallel into the flip flops simultaneously, rather than a bit-by-
bit.

Lets take an example suppose we have to store a 4-bit number (1011). Then all input are fed to
the inputs of 4 flip flop. With single clock pulse all data are entered to all 4 flip flops. Another
important thing in this type of register is that there is no interconnection between the flip flops
since no serial shifting is required. A simple parallel in parallel out shift register is shown below.

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Fig3.4: PIPO shift register

From the above diagram we can see the parallel inputs to be applied at A, B, C, and D inputs are
directly connected to the D inputs of the respective flip flops. On applying the clock transitions,
these inputs are entered into the register and are immediately available at the outputs Q1, Q2,
Q3, and Q4.

Concept of universal shift-register: A universal shift register is an integrated logic

circuit that can transfer data in three different modes. Like a parallel register it can load and
transmit data in parallel. Like shift registers it can load and transmit data in serial fashions,
through left shifts or right shifts. In addition, the universal shift register can combine the
capabilities of both parallel and shift registers to accomplish tasks that neither basic type of
register can perform on its own. (OR) A register which is capable of transferring data in both the
shift-right and shift-left, along with the necessary input and output terminals for parallel transfer,
then it is called a shift register with parallel load or universal shift register.

In order for the universal shift register to operate in a specific mode, it must first select the mode.
To accomplish mode selection the universal register uses a set of two selector switches, S1 and
S0. As shown in table, each permutation of the switches corresponds to a loading/input mode.

Operating Mode S1 S0

Locked 0 0

Shift-Right 0 1

Shift-Left 1 0

Parallel Loading 1 1

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List shift-register ICs:

7491 8-bit shift register, serial in, serial out, gated input.
7495 4-bit shift register, parallel in, parallel out, serial input.
7496 5-bit parallel-In/parallel-out shift register, asynchronous preset.
7499 4-bit bidirectional universal shift register.
74164 8-bit parallel-out serial shift register with asynchronous.
74165 8-bit serial shift register, parallel Load, complementary outputs.
74166 parallel-Load 8-bit shift register.
74194 4-bit bidirectional universal shift register.
74198 8-bit bidirectional universal shift register.
74199 8-bit bidirectional universal shift register with J-Not-K serial inputs.
74291 4-bit universal shift register, binary up/down counter, synchronous.
74395 4-bit universal shift register with three-state outputs.
74498 8-bit bidirectional shift register with parallel inputs and three-state outputs.
74671 4-bit bidirectional shift register.
74673 16-bit serial-in serial-out shift register with output storage registers.
74674 16-bit parallel-in serial-out shift register with three-state outputs.

Ring counter: The ring counter is a cascaded connection of flip flops, in which the output of
last flip flop is connected to input of first flip flop. In ring counter if the output of any stage is 1,
then its reminder is 0. The Ring counters transfers the same output throughout the circuit.

That means if the output of the first flip flop is 1, then this is transferred to its next stage i.e. 2nd
flip flop. By transferring the output to its next stage, the output of first flip flop becomes 0. And
this process continues for all the stages of a ring counter. If we use n flip flops in the ring
counter, the „1‟ is circulated for every n clock cycles.
The circuit diagram of the ring counter is shown below.

Fig3.5: 4-bit Ring counter

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Here we design the ring counter by using D flip flop. This is a Mod 4 ring counter which has 4 D
flip flops connected in series. The clock signal is applied to clock input of each flip flop,
simultaneously and the RESET pulse is applied to the CLR inputs of all the flip flops.
Operation of Ring Counter

Initially, all the flip flops in ring counter are reset to 0 by applying CLEAR signal. Before
applying the clock pulse, we apply the PRESET pulse to the flip flops which assigns the value
„1‟ to the ring counter circuit. For each clock signal, the data circulates among all the 4 flip flop
stages of ring counter.
This 4 staged ring counter is called Mod 4 ring counter or 4 bit ring counter. To circulate the data
correctly in the ring counter, we must load the counter with required values like all 0‟s or all 1‟s.
Truth table

Waveform:

Johnson’s counter: The Johnson counter is a modification of ring counter. In this the
inverted output of the last stage flip flop is connected to the input of first flip flop. If we use n
flip flops to design the Johnson counter, it is known as 2n bit Johnson counter or Mod 2n
Johnson counter.

The main difference between the 4 bit ring counter and the Johnson counter is that , in ring
counter we connect the output of last flip flop directly to the input of first flip flop. But in
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Johnson counter, we connect the inverted output of last stage to the first stage input. The Johnson
counter is also known as Twisted Ring Counter.

The Johnson counter or switch trail ring counter is designed in such a way that it overcomes the
limitations of ring counter. Mainly it reduces the number of flip flops required for designing the
circuit.

The circuit diagram of the Johnson counter is shown below.

Fig3.6:Johnson counter

The clock signal in johnson counter is connected to the clock input of each flip flop
simultaneously.

Operation of Johnson counter

The Johnson counter designed with D flip flop is shown below. It has four stages i.e. four flip
flops connected in series type or cascaded. Initially zero / Null is fed to the Johnson counter and
on applying the clock signal, outputs will change to “1000”, “1100”, “1110”, “1111”, “0111”,
“0011”, “0001”, “0000” in a sequence and the sequence will repeat for next clock signal.

The Johnson counter produces a special pattern by passing four 0‟s and then four 1‟s and thus it
produces a special pattern by counting up down.

Truth table

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Waveform

Applications:

Ring counters are used to count the data in a continuous loop.

They are also used to detect the various numbers values or various patterns within a set of
information, by connecting AND & OR logic gates to the ring counter circuits.

2,3,and 4 stage ring counters are used in frequency divider circuits as divide by 2 and divide by
3 and divide by 4 circuits, respectively.

The 3 stage Johnson counter is used as a 3 phase square wave generator which produces 1200
phase shift.

The 5 stage Johnson counter circuit is generally used as synchronous decade (BCD) counter and
also as divider circuit.

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Counters: Counter is an electronic circuit used to count the number clock pulses arriving at the
clock input. Counters are constructed using series of flip-flops. Although any flip-flop can be
suitably connected to form a counter, most widely used are D and JK flip-flops. (OR) A counter
is a digital sequential logic device that will go through a certain predefined states based on the
application of the input pulses. They are utilized in almost all computers and digital electronics
systems.

Modulus of counter: The number of different output states a counter can produce is called the
modulo or modulus of the counter. (OR) The Modulus (or MOD-number) of a counter is the total
number of unique states it passes through in one complete counting cycle with a mod-n counter
being described also as a divide-by-n counter. Its is also called as a natural counter.

In general the mod number can be increased by adding more flip flops to the counter, i.e MOD
number=2N where N is the number of flip flops taken.

Classification: Counters are broadly classified into synchronous and asynchronous counters.

synchronous counters: Synchronous counters are constructed with one common clock
signal as the input to all the flip-flops simultaneously. The clock does not ripple through the
counter stages. Synchronous counters are also referred to as parallel counters due to the parallel
manner that the clock is fed to all the counter stages. The below figure shows the 4-bit
synchronous counter

Fig3.7: 4-bit synchronous counter

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Asynchronous counters: Asynchronous counters are also referred to as ripple counters. The
incoming clock waveform is connected to the first flip flop of the counter, which generates the
LSB of the numbers in the count sequence. The output of the first flip flop is connected as clock
input to the next flip flop. Each flip flop of an asynchronous counter obtains its clock signal from
the output of the prior flip flop, which results in the clock signal rippling through all the flip-
flops of the counter. A 4-bit asynchronous counter is shown in figure.

Fig 3.8: 4-bit asynchronous counter

Synchronous up counters: The 4 bit up counter shown in below diagram is designed by

using JK flip flop. External clock pulse is connected to all the flip flops in parallel.

For designing the counters JK flip flop is preferred .The significance of using JK flip flop is that
it can toggle its state if both the inputs are high, depending on the clock pulse.

The inputs of first flip flop are connected to HIGH (logic 1), which makes the flip flop to toggle,
for every clock pulse entered into it. So the synchronous counter will work with single clock
signal and changes its state with each pulse.

Fig 3.9: 4-bit synchronous up-counter

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The output of first JK flip flop (Q) is connected to the input of second flip flop. The AND gates
(which are connected externally) drives the inputs of other two flip flops. The inputs of these
AND gates, are supplied from previous stage flip flop outputs.

Operation
In the up counter the 4 bit binary sequence starts from 0000 and increments up to 1111. In the
above circuit as the two inputs of the flip flop are wired together. There are only two possible
conditions that can occur, that is, either the two inputs are high or low.

If the two inputs are high then JK flip-flop toggles and if both are low JK flip flop stays in the
previous state. Clock pulse given is edge triggered clock pulse.

 In the first clock pulse, the outputs of all the flip flops will be at 0000.
 In the second clock pulse, as inputs of J and k are connected to the logic high, output of
JK flip flop(FF0) change its state .Thus the output of the first flip-flop(FF0) changes its
state for every clock pulse .
 In the third clock pulse next flip flop (FF1) will receive its J K inputs i.e (logic high) and
it changes its state. At this state FF0 will change its state to 0.
 Similarly, in the fourth clock pulse FF1 will not change its state as its inputs are in low
state, it remains in its previous state. Though it produces the output to FF2, it will not
change its state due to the presence of AND gate. FF0 will again toggle its output to logic
high state.
 In the fifth clock pulse, FF2 receives the inputs and changes its state. While, FF0 will
have low logic on its output and FF1 will also be in low state.

Truth table:

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Waveform:

Synchronous down counters: Down counter counts the numbers in decreasing order. This
is similar to an up counter but is should decrease its count. So inputs of JK flip- flop are
connected to the inverted ) .The 4 bit down counter shown in below diagram is designed by
using JK flip flop. The clock pulse is connected to all the flip flops.

Fig 3.10: 4-bit synchronous down counter

As the counter has to count down the sequence, initially all the inputs will be in high state as they
have to count down the sequence. It will start with 1111 and ends with 0000, similar to the up
counter.

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In the down counter it should be remembered that, preceding flip flop will toggles only if front
flip flop produces low logic at its output.

Asynchronous counters: A three-bit asynchronous counter is shown in the figure below.

The external clock is connected to the clock input of the first flip-flop (FF0) only. So, FF0
changes state at the rising edge of each clock pulse, but FF1 and FF2 changes only when
triggered by the rising edge of the Q output of FF0 and FF1 respectively. Because of the
inherent propagation delay through a flip-flop, the transition of the input clock pulse and a
transition of the Q output of FF0 and FF1 can never occur at exactly the same time. Therefore,
the flip-flops cannot be triggered simultaneously, producing an asynchronous operation.

Fig 3.11: 3-bit asynchronous counter

Waveform:

Truth table:

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Comparison between synchronous and Asynchronous Counters:

Synchronous counter Asynchronous counter

Propagation delay is higher than that of

The propagation delay is very low.
synchronous counters.

The maximum frequency of operation is

Its operational frequency is very high.
very low.

These are faster than ripple counters. These are slow in operation.

Large number of logic gates are required

Less number of logic gates required.
to design

High cost. Low cost.

Synchronous circuits are easy to design. Complex to design.

Standard logic packages available for For asynchronous counters, Standard logic
synchronous. packages are not available.

Realization of higher-mod counters using lower-mod counters: Counter circuits can be

cascaded to increase both the modulus of the count sequence and the frequency division.
Let us see how to build MOD-16 counter using MOD-2 counter. Here MOD-2 counters are
cascaded by routing the output of one stage into clock input of next stage. The overall modulus
of the counter is equal to the modulus of the individual stage multiplied together i.e 2*2*2*2=16.

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Fig 3.12: MOD-16 counter.

The IC7490 is an example of counter circuit that requires cascading in order to obtain decade
counter. The decade counter is formed by cascading MOD-2 counter with a MOD-5 counter. The
final modulus is 2*5=10.
EXAMPLE: Design mod 20 counter using IC7490
7490 is a mod 10 counter. Two ics of 7490 are required.the counter will go through 0 – 19 and
should be reset on state 20 that is 0010 0000.this can be achived by cascading two counters that
is mod10 and mod2.

List of Counter IC’s:

IC‟s Number Description
7468 Dual 4-bit decade counter
7469 Dual 4-bit binary counter
Decade counter(Separate divide by 2 and
7490
divide by 5 sections)
4-bit binary counter(separate divide by 2
7493
and divide by 8 sections)
Synchronous 4-bit decade counter with
74160
asynchronous clear.
Synchronous 4-bit binary counter with
74161
asynchronous clear.

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74168 Synchronous 4-bit up/down decade counter

74169 Synchronous 4-bit up/down decade counter
74190 Synchronous up/down decade counter
74191 Synchronous up/down binary counter
Synchronous up/down decade counter with
74192
clear
Synchronous up/down binary counter with
74193
clear

74LS90 decade counter IC description:

IC 7490 is a TTL MSI decade counter. It contains four master slave flip flops and additional
gating to provide divide by two counter and a three stage binary counter providing a divide by 5
counter as shown below:

Fig3.12:PIN diagram of IC 7490

Pin Configuration:

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Fig3.13: Basic internal structure of IC 7490

Fig3.13 consists of two counters MOD-2 and MOD-5 counters. It can be used as MOD-2 counter
and MOD-5 counter separately. If IC7490 is used as MOD-10 counter connect QA output of
MOD-2 to clock input B of MOD-5 counter.

IC7490 as a Decade counter:

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Unit 4: D/A and A/D Converters

Need of D/A and A/D Converters

An analog quantity is one that can take on any value over a continuous range of values. Most
physical variables are analog in nature. Temperature, pressure, light and sound intensity,
position, rotation, speed etc... are some examples of analog quantities.

A digital quantity takes on any discrete values. The value expressed in a digital code such as a
binary or BCD number.

When a physical process is monitored or controlled by a digital system such as a computer, the
physical variables are first converted into electrical signals using transducers and then these
electrical analog signals are converted into digital signals using analog to digital
converters(ADCs).These digital signals are processed by a digital computer and the output of a
digital computer is converted into analog signals using digital to analog converters(DACs).

The output of DAC is modified by an actuator and output of actuator is applied as the control
variable.

Fig 4.1:Digital control system with analog I/O.

Fig4.1 shows how ADCs and DACs function as interfaces between a completely digital system
such as a digital computer and the analog world.
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Digital to Analog Converter(DAC)

A digital-to-analog converter (DAC, D/A, D–A, D2A, or D-to-A) is a device that converts a digital
signal into an analog signal.

Applications of DAC

Digital Motor Control

Computer Printers

Sound Equipment (e.g. CD/MP3 Players, etc.)

Electronic Cruise Control

Digital Thermostat

DACs are commonly used in

They are used in music players to convert digital data streams into analog audio signals.

Televisions.

In mobile phones to convert digital video data into analog video signals which connect to the
screen drivers to display monochrome or color images.

Digital Motor Control

Computer Printers

Electronic Cruise Control

Digital Thermostat

Symbolic Representation of DAC

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Fig 4.2: Symbolic representation of DAC.

Types of DAC
Binary Weighted Resistor.
R-2R Ladder.
Resistor String
DAC specifications
Some of the important specifications are Resolution, Accuracy, linearity, monotonicity,
conversion time, settling time, speed and stability.

Resolution: Resolution is defined as the number of different analog output voltage levels that
can be provided by a DAC or alternatively resolution is defined as the ratio of a change in output
voltage resulting for a change of 1 LSB at the digital input. Simply, resolution is the value of
LSB.

Accuracy: Absolute accuracy is the maximum deviation between the actual converter output and
the ideal converter output. The ideal converter is the one which does not suffer from any
problem. Whereas, the actual converter output deviates due to the drift in component values,
mismatches, aging, noise and other sources of errors.

The relative accuracy is the maximum deviation after the gain and offset errors have been
removed. Accuracy is also given in terms of LSB increments or percentage of full-scale voltage.
Normally, the data sheet of a D/A converter specifies the relative accuracy rather than absolute
accuracy.

Linearity: Linearity error is the maximum deviation in step size from the ideal step size. Some
D/A converters are having a linearity error as low as 0.001% of full scale. An ideal D/A
converter produces equal increments or step sizes at output for every change in equal increments
of binary input.

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Analog Output Signal

Analog Output Signal

0000 0001 0010 0011 0100 0101 0000 0001 0010 0011 0100 0101
Digital Input Signal Digital Input Signal

Fig 4.3: Linearity (ideal) Fig 4.4: Non -linearity

Monotonicity: A Digital to Analog converter is said to be monotonic if the analog output always
increases or remains constant as the digital input increases. Otherwise it would lead to
oscillations. If a DAC has to be monotonic, the error should be less than ± (1/2) LSB at each
output level. Hence all the D/A converters are designed such that the linearity error satisfies the
above condition. When a D/A Converter doesn‘t satisfy the condition described above, then, the
output voltage may decrease for an increase in the binary input.

Conversion Time: It is the time taken for the D/A converter to produce the analog output for the
given binary input signal. It depends on the response time of switches and the output of the
Amplifier. D/A converters speed can be defined by this parameter. It is also called as setting
time.

Settling time: It is one of the important dynamic parameter. It represents the time it takes for the
output to settle within a specified band ± (1/2) LSB of its final value following a code change at
the input (Usually a full-scale change). It depends on the switching time of the logic circuitry due

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to internal parasitic capacitances and inductances. A typical settling time ranges from 100 ns to
10 μs depending on the word length and type of circuit used.

Speed: Speed is rate of conversion of a single digital input to its analog equivalent. Conversion
rate depends on clock speed of input signal and settling time of converter. When the input
changes rapidly, the DAC conversion speed must be high.

DAC using Resistive Divider Network(Binary-Weighted Resistor DAC)

The binary-weighted-resistor DAC employs the characteristics of the inverting summer Op Amp
circuit. In this type of DAC, the output voltage is the inverted sum of all the input voltages. If the
input resistor values are set to multiples of two: 1R, 2R and 4R, the output voltage V0 would be
equal to the sum of V1, V2/2 and V3/4. V1 corresponds to the most significant bit (MSB) while
V3 corresponds to the least significant bit (LSB).

V0= -( V1+V2/2+ V3/4)

The circuit for a 4-bit DAC using binary weighted resistor network is shown below:

Fig 4.5: Resistive divider network.

The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The value, 0,
represents an open switch while 1 represents a closed switch. The operational amplifier is used as
a summing amplifier, which gives a weighted sum of the binary input based on the voltage, Vref.
For a 4-bit DAC, the relationship between Vout and the binary input is as follows:

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The negative sign associated with the analog output is due to the connection to a summing
amplifier, which is a polarity-inverting amplifier. When a signal is applied to the latter type of
amplifier, the polarity of the signal is reversed (i.e. a + input becomes -, or vice versa). For a n-
bit DAC, the relationship between Vout and the binary input is as follows:

Binary-Ladder Network(R/2R ladder ) DAC

To overcome huge range of resistor used in weighted resistor D/A converter, R-2R ladder D/A
converter is introduced. But the vital problem in weighted register D/A converter is use of huge
range of different resistance. Suppose we have to design 8-bit weighted resistor D/A converter
then we need the resistance value 20R+21R+….+27R. So the largest resistor corresponding to bit
b8 is 128 times the value of the smallest resistor corresponding to b1. But in case of R-2R ladder
D/A converter, Resistors of only two value (R and 2R) are used. The simple ladder network is
shown below.

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Fig 4.6: Binary ladder network for D/A conversion.

In ladder circuit the output voltage is also weighted sum of the corresponding digital input.
Consider an example to convert analog signal correspond of 1000 input bits. For 1000 bits we
can see only MSB got 1 and rest all bits got 0.

Now see at node1 (N1) resistor 2R connecting in b4 parallel with resistor 2R. And those 2R
parallel 2R resistors make equivalent resister of R as shown in below diagram.

Now for N2 same thing happen. 2R at B3 parallel with R + R resistors. It will also make
equivalent resistor R at N3. See the below diagram

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Repeating the same process we got equivalent of R resistor at N4.

Now at N4, if we calculate the output analog equivalent voltage then we will get
VA = VR *2R/(R+R+2R)
= VR/2
Thus when input is 1000 the output is VR/2. Similarly it can be found that using above process
for input 0100 the output will be VR/4, for input 0010 output will be VR/8 and for input 0001
output will be VR/16.
By using superposition theorem we can find in any n-bit ladder network the output voltage will
be
VA = VR/21 + VR/22 + VR/23 + ……. + VR/2n
Where n is the total number of bits at the input.
The practical circuit arrangement of 4-bit R-2R ladder D/A converter using op amp is as shown
below.

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Fig 4.7: 4-bit R-2R ladder D/A converter using op amp.

The inverting input terminal of the op amp works as a summing amplifier for the ladder inputs.
So we can get output voltage by below equation.
V0 = VR*(RF/R)[b1/21 + b2/22 + b3/23 + b4/24]

DAC ICs and their features.

DAC 0800/0802
Features
 Fast Settling Output Current 100 ns current
 Full Scale Error: ±1 LSB
 Nonlinearity Over Temperature: ±0.1%
 Full Scale Current Drift: ±10 ppm/°C
 High Output Compliance: −10V to +18V
 Complementary Current Outputs output
 Interface Directly with TTL, CMOS, PMOS
 Wide Power Supply Range: ±4.5V to ±18V
 Low Power Consumption: 33 mW at ±5V
 Low Cost

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Fig 4.8: DAC 0800.

DAC7625
Features
 Low Power: 20mw
 Unipolar Or Bipolar Operation
 Settling Time: 10µs To 0.012%
 12-Bit Linearity And Monotonicity: –40°C To +85°C
 Reset To Mid-Scale (Dac7624) Or Zero-Scale (Dac7625)
 Data Readback
 Double-Buffered Data Inputs

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Fig 4.9: DAC 7625.

MCP4921 DAC

Features

 12-Bit Resolution
 Single or Dual Channel
 Rail-to-Rail Output
 SPI Interface with 20 MHz Clock Support
 Simultaneous Latching of the Dual DACs w/LDAC
 Fast Settling Time of 4.5 µs
 Selectable Unity or 2x Gain Output
 450 kHz Multiplier Mode
 External VREF Input
 2.7V to 5.5V Single-Supply Operation
 Extended Temperature Range: -40°C to +125°C

Fig 4.10: MCP4921 DAC.

Simple problems

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ADC(Analog to Digital Converter)

An analog-to-digital converter is a device that converts analog signals (continuous quantity) into
digital signals (discrete time digital representation). The analog signal is a continuous sinusoidal
waveform that cannot be read by a computer, hence the need for conversion. By converting the
analog signal, data can be amplified, added or taken from the original signal.

Symbolic Representation of ADC

Fig 4.11: Symbolic representation of ADC.

Types of ADCs
 Flash ADC.
 Successive Approximation Converter.
 Sigma-Delta.
 ADC Comparison.
 Sample And Hold.
 Software.
 Internal Microcontroller ADCS.

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Applications
 Music recording

 Digital signal processing

 Scientific instruments

 Rotary encoder

 Computers use ADC to convert signals from analog to digital before they can be
interpreted. For example modem.

 Fast video ADC is used in TV tuner cards

 Digital storage oscilloscopes

Specifications

 The important specifications of ADCs are

 Resolution,

 Quantization error,

 Conversion time,

 Analog error,

 Linearity error,

 DNL error,

 INL error & Input voltage range.

Resolution: The resolution refers to the finest minimum change in the signal which is
accepted for conversion, and it is decided with respect to number of bits. It is given as 1/2n,
where n is the number of bits in the digital output word. As it is clear, that the resolution can be
improved by increasing the number of bits or the number of bits representing the given analog
input voltage. Resolution can also be defined as the ratio of change in the value of input voltage
Vi, needed to change the digital output by 1 LSB. It is given as

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Linearity Error: It is defined as the measure of variation in voltage step size. It indicates the
difference between the transitions for a minimum step of input voltage change. This is normally
specified as fraction of LSB.

DNL(Differential Non-Linearity)Error: The analog input levels that trigger any two
successive output codes should differ by 1 LSB. Any deviation from this 1 LSB value is called as
DNL error.

INL (Integral Non-Linearity Error): The deviation of characteristics of an ADC due to

missing codes causes INL error. The maximum deviation of the code from its ideal value after
nulling the offset and gain errors is called as Integral Non-Linearity Error.

Accuracy: Accuracy describes the closeness of actual analog input and weighted equivalent of
the corresponding output code. This specifies the maximum sum of all errors from analog and
digital sources of the A to D converters. These errors include gain , offset error and quantization
error.

Conversion time: It the time required to convert an analog signal input to a digital output.

Flash ADC

Flash ADC is called as Parallel ADC . Its response is very fast. It converts analog signal into
digital signal using parallel set of comparators. As its conversion time is very fast it is called as
flash ADC.

Following figure shows circuit diagram of parallel ADC or flash ADC.

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Fig 4.12: Flash ADC.

n-bit Flash ADC consist of parallel combination of 2n-1 comparators. Outputs of all comparators
are connected to an encoder.

Working Principle Of Flash ADC

Analog voltage is applied to non inverting terminals of all comparators using a single line.
Reference voltage is applied to inverting terminals of comparators using divider circuit.

Each comparator produces digital output in the form of 1 or 0. If unknown analog voltage is
greater than reference voltage comparator produces high logic. If analog voltage is less than
reference voltage then comparator produces low logic i.e. 0.

Thus all parallel comparator produces digital representation of analog voltage in the form of zero
and one. These outputs of comparator are then applied to the fast encoder. Encoder converts
those zeros and once into binary number and produces digital binary output.

ANALOG INPUT COMPARATOR OUTPUT OUTPUT

VA C1 C2 C3 C4 C5 C6 C7 B2 B1 B0
V1< 0.125VR 0 0 0 0 0 0 0 0 0 0
0.125VR
1 0 0 0 0 0 0 0 0 1
<V1<0.25VR

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0.25VR<V1<0.375VR 1 1 0 0 0 0 0 0 1 0
0.375VR<V1<0.5VR 1 1 1 0 0 0 0 0 1 1
0.5VR<V1<0.625VR 1 1 1 1 0 0 0 1 0 0
0.625VR<V1<0.75VR 1 1 1 1 1 0 0 1 0 1
0.75VR<V1<0.875VR 1 1 1 1 1 1 0 1 1 0
V1=0.875VR 1 1 1 1 1 1 1 1 1 1

Dual Slop ADC

In dual slope type ADC, the integrator generates two different ramps, one with the known analog
input voltage VA and another with a known reference voltage –Vref. Hence it is called as dual
slope A to D converter. The logic diagram for the same is shown below.

Fig 4.12: Dual slop ADC.

Operation:
The binary counter is initially reset to 0000; the output of integrator reset to 0V and the input to
the ramp generator or integrator is switched to the unknown analog input voltage VA.

The analog input voltage VA is integrated by the inverting integrator and generates a negative
ramp output. The output of comparator is positive and the clock is passed through the AND gate.
This results in counting up of the binary counter.

The negative ramp continues for a fixed time period t1, which is determined by a count detector
for the time period t1. At the end of the fixed time period t1, the ramp output of the integrator is
given by.

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VS= -(VA/RC)*t1
When the counter reaches the fixed count at time period t1, the binary counter resets to 0000 and
switches the integrator input to a negative reference voltage –Vref.

Now the ramp generator starts with the initial value –Vs and increases in positive direction until
it reaches 0V and the counter gets advanced. When Vs reaches 0V, comparator output becomes
negative (i.e. logic 0) and the AND gate is deactivated. Hence no further clock is applied through
AND gate. Now, the conversion cycle is said to be completed and the positive ramp voltage is
given by.
VS=(Vref/RC)*t2

Where Vref & RC are constants and time period t2 is variable.

The dual ramp output waveform is shown below.

Since ramp generator voltage starts at 0V, decreasing down to –Vs and then increasing up to 0V,
the amplitude of negative and positive ramp voltages can be equated as follows.
∴(Vref/RC)*t2=-(VA/RC)*t1
∴t2=-t1×(VA/Vref)
∴VA= - Vref*(t2/t1)

Thus the unknown analog input voltage VA is proportional to the time period t2, because Vref is
a known reference voltage and t1 is the predetermined time period.

The actual conversion of analog voltage VA into a digital count occurs during time t2. The
binary counter gives corresponding digital value for time period t2. The clock is connected to the
counter at the beginning of t2 and is disconnected at the end of t2. Thus the counter counts
digital output as.
Digital output = (Count/Sec)t2

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∴Digital output=(counts/sec)[t1*(VA/Vref) ]

For example, consider the clock frequency is 1 MHz, the reference voltage is -1V, the fixed time
period t1 is 1ms and the RC time constant is also 1 ms. Assuming the unknown analog input
voltage amplitude as VA = 5V, during the fixed time period t1 , the integrator output Vs is

∴VS=-(VA/RC)*t1=(-5)/1ms×1ms=-5V
During the time period t2, ramp generator will integrate all the values to 0V.

∴ t2= (VS/Vref)*RC=(-5)/(-1)×1ms=5ms=5000μs

Hence the 4-bit counter value is 5000, and by activating the decimal point of MSD seven
segment displays, the display can directly read as 5V.

Successive Approximation Type ADC

Successive Approximation type ADC is the most widely used and popular ADC method. The
conversion time is maintained constant in successive approximation type ADC, and is
proportional to the number of bits in the digital output, unlike the counter and continuous type
A/D converters. The basic principle of this type of A/D converter is that the unknown analog
input voltage is approximated against an n-bit digital value by trying one bit at a time, beginning
with the MSB.

The functional block diagram of successive approximation type of ADC is shown below.

Fig 4.13: Successive approximation type of ADC.

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It consists of a successive approximation register (SAR), DAC and comparator. The output of
SAR is given to n-bit DAC. The equivalent analog output voltage of DAC, VD is applied to the
non-inverting input of the comparator. The second input to the comparator is the unknown
analog input voltage VA. The output of the comparator is used to activate the successive
approximation logic of SAR.

The principle of successive approximation process for a 4-bit conversion is explained here. This
type of ADC operates by successively dividing the voltage range by half, as explained in the
following steps.

The MSB is initially set to 1 with the remaining three bits set as 000. The digital equivalent
voltage is compared with the unknown analog input voltage.

If the analog input voltage is higher than the digital equivalent voltage, the MSB is retained as 1
and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the second MSB is set to 1.
Comparison is made as given in step (1) to decide whether to retain or reset the second MSB.
The above steps are more accurately illustrated with the help of an example.

Lets assume that the 4-bit ADC is used and the analog input voltage is VA = 11 V. when the
conversion starts, the MSB bit is set to 1.

Now VA = 11V > VD = 8V = [1000]2

Since the unknown analog input voltage VA is higher than the equivalent digital voltage VD, as
discussed in step (2), the MSB is retained as 1 and the next MSB bit is set to 1 as follows

VD = 12V = [1100]2

Now VA = 11V < VD = 12V = [1100]2

Here now, the unknown analog input voltage VA is lower than the equivalent digital voltage VD.
As discussed in step (2), the second MSB is set to 0 and next MSB set to 1 as

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VD = 10V = [1010]2

Now again VA = 11V > VD = 10V = [1010]2

Again as discussed in step (2) VA>VD, hence the third MSB is retained to 1 and the last bit is set
to 1. The new code word is

VD = 11V = [1011]2

Now finally VA = VD , and the conversion stops.

Advantages:
Conversion time is very small.

Conversion time is constant and independent of the amplitude of the analog input signal VA.

Disadvantages:
Circuit is complex.

The conversion time is more compared to flash type ADC

Simple problems

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ADC IC and Their Features

Features of ADC 0804

 Compatible With 8080-µP Derivatives – No

 Interfacing Logic Needed – Access Time 135 ns
 Easy Interface to All Microprocessors
 Differential Analog Voltage Inputs
 Logic Inputs and Outputs Meet Both MOS and TTL Voltage-Level Specifications
 Works With 2.5-V (LM336) Voltage Reference logic is needed.
 On-Chip Clock Generator
 0-V to 5-V Analog Input Voltage Range With Single 5-V
 No Zero Adjust Required
 0.3-Inch Standard Width 20-Pin DIP Package resolution.
 20-Pin Molded Chip Carrier or Small Outline Package
 Operates Ratiometrically or With 5 VDC, 2.5 VDC,or analog span Voltage Reference

Features of ADC 0809

 Easy interface to all microprocessors

 Operates ratiometrically or with 5 VDC or analog span adjusted voltage reference

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 No zero or full-scale adjust required

 8-channel multiplexer with address logic
 0V to 5V input range with single 5V power supply
 Outputs meet TTL voltage level specifications
 Standard hermetic or molded 28-pin DIP package
 28-pin molded chip carrier package
 ADC0808 equivalent to MM74C949
 ADC0809 equivalent to MM74C949-1

Features of ADC MCP3202

 12-bit resolution
 ±1 LSB max DNL
 ±1 LSB max INL (MCP3202-B)
 ±2 LSB max INL (MCP3202-C)
 Analog inputs programmable as single-ended or pseudo-differential pairs
 On-chip sample and hold
 SPI serial interface (modes 0,0 and 1,1)
 Single supply operation: 2.7V-5.5V
 100 ksps max. sampling rate at VDD = 5V
 50 ksps max. sampling rate at VDD = 2.7V
 Low power CMOS technology - 500 nA typical standby current, 5 μA max. - 550 µA
max. active current at 5V
 Industrial temp range: -40°C to +85°C
 8-pin MSOP, PDIP, SOIC and TSSOP packages.

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Unit 5: Memories and programmable devices

5.1 Introduction:
Computer memory is a physical device capable of storing information temporarily or
permanently. For example, Random Access Memory (RAM).

The term memory meaning primary storage or main memory, is often associated with
addressable semiconductor memory, i.e. integrated circuits consisting of silicon-
based transistors, example as primary storage but also other purposes in computers and other
digital electronics devices.

Most semiconductor memory is organized into memory cells or bistable flip-flops, each storing
one bit (0 or 1). Flash memory organization includes both one bit per memory cell and multiple
bits per cell (called MLC, Multiple Level Cell). The memory cells are grouped into words of
fixed word length, for example 1, 2, 4, 8, 16, 32, 64 or 128 bit. Each word can be accessed by a
binary address of N bit, making it possible to store 2N words in the memory.

The location of a unit of data in a memory is called address. In PCs byte is the smallest unit of
data that can be accessed. In a two dimensional array a byte is accessed by supplying a row
number.
1
2
3
4
5

For example word 4 can be selected by giving row address as 4.

decode the address to determine the specific location. Data is then moved to or from the data
bus.

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Fig5.1: Memory array with address and data bus

The address bus is a group of conductors with a common function. Its size determines the
number of location that can be accessed.

For example if computer has 64k words then this memory unit has 64*1024 = 65536 memory
location. The address of these locations varies from 0 to 65535. In the same way the 32 bit
address bus can access 232 locations, which is approximately 4GB.

In addition to the address bus and data bus, semiconductor memories have read and write control
signals and chip select signals.

Read and write operation

The two main memory operations are called read and write.

Write operation

In the write operation data moves in to the memory. The new data overwrites the original data.
The write operation has the following process

The address is placed on the address bus.

Data is placed on the data bus.

A write command is issued.

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Fig5.2: Write operation.

Consider an example

First the address 101 from the address register is placed on the address bus which selects the
particular address of the memory location.

The data 00010000 from the data register is placed on the data bus. Finally the write command is
issued and data is stored in the location 101.

Read operation

The read operation is a copy operation as the original data is not changed. The read operation as
the following process

The address is placed on the address bus.

A read command is issued.

A copy of the data is placed on the data bus and shifted into the data register.

Fig5.3: Read operation.

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Consider an example

First the address 011 from the address register is placed on the address bus which selects the
particular address of the memory location.

The read command is issued.

The data 10101010 from the memory location is copied into the data bus, and then into the data
register.

Classification of Memories

Memory is primarily of two types

Internal memory: cache memory and primary/main memory.

External memory: Secondary memory /auxiliary memory etc.

Fig5.4(a): Classification of memory.

The another main classification of memories are as below

Fig5.4(b): Classification of memory.

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Refer: https://youtu.be/PVad0c2cljo

Magnetic Memory

Video link of magnetic memory https://youtu.be/f3BNHhfTsvk

Magnetic storage is the storage of data on a magnetized medium. Magnetic storage uses
different patterns of magnetization in a magnetisable material to store data and is a form of non-
volatile memory. The information is accessed using one or more read/write heads.

In magnetic storage hard disks are widely used to store computer data as well
as audio and video signals. In the field audio and video production the term magnetic storage is
preferred and the term magnetic recording is more commonly used. Other examples of magnetic
storage media include floppy disks, magnetic recording tape, and magnetic stripes on credit
cards.

Information is written to and read from the storage medium as it moves past devices called read-
and-write heads that operate very close (often tens of nanometers) over the magnetic surface.
The read/write head is used to detect and modify the magnetization of the material immediately
under it. There are two magnetic polarities, each of which is used to represent either 0 or 1.

The magnetic surface is conceptually divided into many small sub-micrometer-sized magnetic
regions, referred to as magnetic domains, each of which has a mostly uniform magnetization.
Due to the polycrystalline nature of the magnetic material each of these magnetic regions is
composed of a few hundred magnetic grains. Magnetic grains are typically 10 nm in size and
each form a single true magnetic domain. Each magnetic region in total forms a magnetic

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dipole which generates a magnetic field. In older hard disk drive (HDD) designs the regions were
oriented horizontally and parallel to the disk surface, the orientation was changed
to perpendicular to allow for closer magnetic domain spacing.

For reliable storage of data, the recording material needs to resist self-demagnetization, which
occurs when the magnetic domains repel each other. Magnetic domains written too densely
together to a weakly magnetisable material will degrade over time due to rotation of
the magnetic moment one or more domains to cancel out these forces. The domains rotate
sideways to a halfway position that weakens the readability of the domain and relieves the
magnetic stresses. Older hard disk drives used iron oxide as the magnetic material, but current
disks use a cobalt-based alloy.

The heads are kept from contacting the platter surface by the air that is extremely close to the
platter; that air moves at or near the platter speed. The record and playback head are mounted on
a block called a slider, and the surface next to the platter is shaped to keep it just barely out of
contact. This forms a type of air bearing.

ROM

ROM stands for Read Only Memory. It is type of internal memory. The data and instructions in
ROM are stored by the manufacturer at the time of its manufacturing. This data and programs
cannot be changed or deleted after wards. The data or instructions stored in ROM can only be
read but new data or instructions cannot be written into it.

ROM stores data and instructions permanently. When the power is turned off, the instructions
stored in ROM are not lost. That is the reason ROM is called non-volatile memory.

ROM is used to store frequently used instructions and data to control the basic input & output
operations of the computer. Mostly, frequently used small programs like operating system
routines and data, are stored into the ROM. When the computer is switched on, instructions in
the ROM are automatically activated. These instructions help the booting process of computer.

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Internal structure of ROM is as shown in below fig. The internal structure or architecture of a
ROM comprises three basic parts, namely the array of memory cells, the address decoder and the
output buffers. The address decoder comprises a single decoder in the case of small memories.

The basic memory cell is an NPN bipolar transistor, connected in common-collector

configuration, or a MOSFET in common drain configuration as shown in below figure. The
connection of the ‘row line’ to the gate of the MOSFET stores ‘1’ at the location when the ‘row
line’ is set to level ‘1’.

A floating-gate connection is used to store ‘0’ as shown in the below figure.

The array of memory cells stores the data to be programmed into the ROM. The number of
memory cells in a row equals the word size, and the number of memory cells in a column equals
the number of such words to be stored. The data outputs of each of the memory cells in the array
are connected to an internal data bus that runs through the entire circuit. The address decoder,
sets the corresponding ‘row line’ HIGH when a binary address is applied at its input lines. The
output is read from the column lines. The data placed on the internal data bus by the memory
cells are fed to the output buffers. CS is an active LOW input used to select the memory device.

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Fig5.5: ROM array

PROM
Programmable ROM (Programmable Read Only Memory) is a computer memory chip that
can be programmed once after it has been created. Once the PROM has been programmed, the
information written is permanent and cannot be erased or deleted.

The internal structure of PROM is as shown in the below figure.The basic memory cell of a
PROM is similar to that of ROM.. In the case of a PROM, each of the connections that were left
either intact or open in the case of a ROM are made with a thin fusible link, as shown in Fig.
Basic fuse technologies used in PROMs are metal links, silicon links and PN junctions. These
fusible links can be selectively blown off to store desired data. A sufficient current is injected
through the fusible link to burn it open to store ‘0’. The programming operation is done with a
PROM programmer. The programmer circuitry selects each address of the PROM one by one,
burns in the required data and then verifies the correctness of the data before proceeding to the
next address. The data are fed to the programmer from a keyboard or a disk drive or from a
computer.

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Fig5.6: PROM array.

EPROM
This is an Erasable Programmable Read Only Memory. This form of semiconductor memory can
be programmed and then erased at a later time. This is normally achieved by exposing the silicon
to ultraviolet light. To enable this to happen there is a circular window in the package of the
EPROM to enable the light to reach the silicon of the chip.

There are two types of EPROM, namely the ultraviolet-erasable PROM (UV EPROM) and
electrically erasable PROM (EEPROM).

Ultraviolet-Erasable Prom (UV EPROM)

The memory cell in a UV EPROM is a MOS transistor with a floating gate. In the normal
condition, the MOS transistor is OFF. It can be turned ON by applying a programming pulse in
the range 10–25V,that injects electrons into the floating-gate region. These electrons remain
trapped in the gate region even after removal of the programming pulse. This keeps the transistor
ON, once it is programmed to be in that state even after the removal of power. The stored

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information can, be erased by exposing the chip to ultraviolet radiation through a transparent
window on the top of the chip. The photocurrent thus produced removes the stored charge in the
floating-gate region and brings the transistor back to the OFF state. The erasing operation takes
around 15–20 min, and the process erases information on all cells of the chip. It is not possible to
carry out any selective erasure of memory cells.

UV EPROMs suffer from disadvantages such as the need to remove the chip from the circuit if it
is to be reprogrammed, the nonfeasibility of carrying out selective erasure and the
reprogramming process taking several tens of minutes. These are overcome in the EEPROMs
and flash memories.

Electrically Erasable PROM (EEPROM)

The memory cell of an EEPROM is also a floating-gate MOS structure with the slight
modification that there is a thin oxide layer above the drain of the MOS memory cell.
Application of a high-voltage programming pulse between gate and drain induces charge in the
floating-gate region which can be erased by reversing the polarity of the pulse. Since the charge
transport mechanism requires very low current. Erasing and programming operations can be
carried out without removing the chip from the circuit. EEPROMs have another advantage – it is
possible to erase and rewrite data in the individual bytes in the memory array. The EEPROMs
have lower density (bit capacity per square mm of silicon) and higher cost compared with UV
EPROMs.

Flash Memory

Flash memories are high-density nonvolatile read/write memories with high density. Flash
memory combines the low cost and high density features of an UV EPROM and the in-circuit
electrical eras-ability feature of EEPROM without compromising the high-speed access of both.

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Structurally, the memory cell of a flash memory is like that of an EPROM. The basic memory
cell of a flash memory is shown in below Fig.

Fig5.6: Flash memory.

It is a stacked-gate MOSFET with a control gate and floating gate in addition to drain and
source. The floating gate stores charge when sufficient voltage is applied to the control gate. A
‘0’ is stored when there is more charge, and a ‘1’ when there is less charge. The amount of
charge stored on the floating gate determines whether or not the MOSFET is turned ON.

It is called a flash memory because of its rapid erase and write times. Most flash memory devices
use a ‘bulk erase’ operation in which all the memory cells on the chip are erased simultaneously.
Some flash memory devices offer a ‘sector erase’ mode in which specific sectors of the memory
device can be erased at a time. This mode comes in handy when only a portion of the memory
needs to be updated.

Below Figure shows the basic array of a 4 × 4 flash memory. There is an address decoder that
selects the row. During the read operation, for a cell containing a ‘1’ there is current through the
bit line which produces a voltage drop across the active load. This is compared with the
reference voltage, and the output bit is ‘1’. If the memory cell has a ‘0’, there is very little current
in the bit line. Memory sticks are flash memories. They are available in 4, 8, 16, 32, 64 and 128
MB sizes.

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Fig5.7: 4X4 Flash memory.

RAM

The RAM or random access memory is a form of semiconductor memory technology that is used
for reading and writing data in any order as required.

RAM is the place in a computing device where the operating system (OS), application programs
and data in current use are kept so they can be quickly reached by the device's processor. RAM is
much faster to read from and write to than other kinds of storage in a computer, such as a hard
disk drive (HDD), solid-state drive (SSD) or optical drive.

RAM comes in two primary forms

SRAM

DRAM

SRAM (Static Random-Access Memory )

Static random-access memory (Static RAM or SRAM) is a type of semiconductor memory

that uses bistable latching circuitry (flip-flop) to store each bit.

The term static differentiates SRAM from DRAM (dynamic random-access memory) which
must be periodically refreshed. SRAM is faster and more expensive than DRAM. It is typically
used for CPU cache while DRAM is used for a computer's main memory.

A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on
four transistors (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has

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two stable states which are used to denote 0 and 1. Two additional access transistors (M5& M6)
serve to control the access to a storage cell during read and write operations. Access to the cell is
enabled by the word line (WL in figure) which controls the two access transistors M5 and M6.

Fig5.8: SRAM cell.

SRAM Operation
An SRAM cell has three different states: standby (the circuit is idle), reading (the data has been
requested) or writing (updating the contents).

Standby
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit
lines. The two cross-coupled inverters formed by M1 – M4 will continue to reinforce each other
as long as they are connected to the supply.

Reading
In theory, reading only requires asserting the word line WL and reading the SRAM cell state by a
single access transistor and bit line, e.g. M6, BL. Nevertheless, bit lines are relatively long and
have large parasitic capacitance. To speed up reading, a more complex process is used in
practice: The read cycle is started by pre-charging both bit lines BL and BL, i.e., driving the bit
lines to a threshold voltage (midrange voltage between logical 1 and 0) by an external module
(not shown in the figures). Then asserting the word line WL enables both the access transistors
M5 and M6, which causes the bit line BL voltage to either slightly drop (bottom NMOS
transistor M3 is ON and top PMOS transistor M4 is off) or rise (top PMOS transistor M4 is on).
It should be noted that if BL voltage rises, the BL voltage drops, and vice versa. Then the BL
and BL lines will have a small voltage difference between them. A sense amplifier will sense

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which line has the higher voltage and thus determine whether there was 1 or 0 stored. The higher
the sensitivity of the sense amplifier, the faster the read operation.

Writing
The write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0,
we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a
reset pulse to an SR-latch, which causes the flip flop to change state. A 1 is written by inverting
the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. This
works because the bit line input-drivers are designed to be much stronger than the relatively
weak transistors in the cell itself so they can easily override the previous state of the cross-
coupled inverters. In practice, access NMOS transistors M5 and M6 have to be stronger than
either bottom NMOS (M1, M3) or top PMOS (M2, M4) transistors. This is easily obtained as
PMOS transistors are much weaker than NMOS when same sized. Consequently when one
transistor pair (e.g. M3 and M4) is only slightly overridden by the write process, the opposite
transistors pair (M1 and M2) gate voltage is also changed. This means that the M1 and
M2 transistors can be easier overridden, and so on. Thus, cross-coupled inverters magnify the
writing process.
DRAM
Dynamic random-access memory (DRAM) is a type of random-access memory that stores
each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either
charged or discharged. These two states are taken to represent the two values of a bit,
conventionally called 0 and 1. Since even "non-conducting" transistors always leak a small
amount, the capacitors will slowly discharge, and the information eventually fades unless the
capacitor charge is refreshed periodically. Because of this refresh requirement, it is
a dynamic memory as opposed to static random-access memory (SRAM) and other static types
of memory.

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Fig 5.9: DRAM cell structure

In Dynamic Random Access Memory CELL, transistor acts as a switch to Close (allowing
current to flow) when voltage applied in word line or Open (no current flow) when no voltage
applied in word line. Address Line is also known as word line. Which is used to signal the
transistor to close or open.

Write operation: A voltage is applied on the bit line and a signal applied to the address line
to close the transistor. Then the voltage applied on the bit line will transfer to capacitor and store
in the capacitor however the capacitor has the tendency to discharge and has to be refreshed to
maintain the bit.

Reading Operation: To read the data or bit the address line is selected. When the address line is
selected ,the transistor turns on and the charge stored on the capacitor is fled out onto a bit line
and to sense amplifier. Sense amplifiers compare the capacitor voltage to reference value to
determine the logic 1 or logic 0.The read out from cell must be restored to complete the
operation.

DDR memory & its variants

Double data rate synchronous dynamic random access memory is a class of memory integrated
circuits used in computers. DDR SDRAM, also called DDR1 SDRAM.

Double data rate synchronous dynamic random access memory (DDR SDRAM) is similar in
function to regular SDRAM, but offers an improvement over SDRAM by doubling the data

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transfer rate. This is accomplished by transferring data twice per cycle on both the rising and
falling edges of the clock signals. This technique is called double pumping.

DDR SDRAM is also called DDR1 SDRAM. Its variants are DDR2 SDRAM, DD31 SDRAM
and DDR4 SDRAM offering higher speeds and lower power consumption. None of its variants
are compatible with DDR1 SDRAM.

Disk memories
Disk memories are hard disk, optical disc, DVD, BLU - RAY
Hard disk
Refer 5.31 section of memories and programmable devices.
Optical disc
An optical disc (OD) is a flat, circular disc which encodes binary data (bits) in the form
of pits (binary value of 0 or off, due to lack of reflection when read) and lands (binary value of 1
or on, due to a reflection when read) on a special material aluminum on one of its flat surfaces.
The encoding material sits atop a thicker substrate (usually polycarbonate) which makes up the
bulk of the disc and forms a dust defocusing layer.

The data is stored on the disc with a laser or stamping machine, and can be accessed when the
data path is illuminated with a laser diode in an optical disc drive which spins the disc at speeds
of about 200 to 4,000 RPM or more, depending on the drive type, disc format, and the distance of
the read head from the center of the disc (inner tracks are read at a higher disc speed).Optical
discs are most commonly used for storing music (e.g. for use in a a CD player), video (e.g. for
use in a Blu-ray player), or data program for PC’s.

Fig5.10: Optical disk.

DVD:
DVD (digital versatile disc or digital video disc) is a digital optical disc storage format invented
and developed by Philips, Sony, Toshiba, and Panasonic in 1995. The medium can store any kind

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of digital data and is widely used for software and other computer files as well as video programs
watched using DVD players. DVDs offer higher storage capacity than compact discs while
having the same dimensions.

There are several capacities a single DVD disc is capable of holding. Below is a listing of the
different types of DVD's and each of their total capacity.
One of the most common DVD's is the single-sided, single-layer disc, capable of holding 4.7
GB.
The single side’s double layer disc is capable of holding between 8.5-8.7GB.
The double-sided, single-layer disc is capable of holding 9.4 GB.

Blu-RAY: Blu-ray or Blu-ray disc is a digital optical disc data storage format. Conventional Blu-
ray Disc discs contain 25 GB per layer, with dual layer discs (50 GB) being the industry standard
for feature-length video discs. Triple-layer discs (100 GB) and quadruple-layers (128 GB) are
available for BD-XL re-writer drives. The name "Blu-ray" refers to the blue laser used to read the
disc, which allows information to be stored at a greater density than is possible with the longer-
wavelength red laser used for DVDs. The main application of Blu-ray is as a medium for video
material such as feature films and physical distribution of video games for the PlayStation
3, PlayStation 4, and Xbox One. Besides the hardware specifications, Blu-ray is associated with a
set of multimedia formats.

Fig5.11: Blu-ray disk.

Memory word Size Expansion

The expanding of word size of 16 × 4 RAM chip from four bits to eight bits is shown in the
below figure. Where two RAM chips have been used.

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Both chips are selected or deselected together. The input that determines whether it is a ‘read’ or
‘write’ operation is common to both chips. That is Both chips are selected for ‘read’ or ‘write’
operation together. The address inputs to the two chips are common. The memory locations
corresponding to various address inputs store four higher-order bits in the case of RAM-1 and
four lower-order bits in the case of RAM-2. Each of the RAM chips stores half of the word.
Since the address inputs are common, the same location in each chip is accessed at the same
time.

Memory capacity Expansion

The fig 5.11 shows how more than one memory chip can be used to expand the number of
memory locations. Let’s consider the use of two 16 × 8 chips to get a 32 × 8 chip. A 32 × 8 chip
would need five address input lines. Four of the five address inputs, other than the MSB address
bit, are common to both 16 × 8 chips. The MSB bit feeds the input of one chip directly and the
input of the other chip after inversion. The inputs to the two chips are common.

Now, for first half of the memory locations corresponding to address inputs 00000 to 01111 (a
total of 16 locations), the MSB bit of the address is ‘0’, with the result that RAM-1 is selected
and RAM-2 is deselected. For the remaining address inputs of 10000 to 11111 (again, a total of
16 locations), RAM-1 is deselected while RAM-2 is selected. Thus, the overall arrangement
offers a total of 32 locations, 16 provided by RAM-1 and 16 provided by RAM-2. The overall
capacity is thus 32 × 8.

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Fig5.11

Programmable Devices
An IC that contains large numbers of gates, flip flops etc,.. that can be configured by the user to
perform different functions is called a programmable logic device(PLD).

PLDs are typically build with an array of AND gates(AND array) and an array of OR gates(OR
array).

AND Array OR Array

Inputs outputs

Difference between Fixed Logic And Programmable Logic

Fixed Logic Devices Programmable Logic Devices
It requires long time from design It requires less time from design
cycle to production run. cycle to production run.
Process of design validation
Inexpensive software tools can be
followed by incorporation of changes
used for quick validation of design.
could be expensive.
These devices does not allowed
These devices allowed quick testing
quick testing and incorporation
and in quick incorporation changes.
changes.
Users can not change the circuit Users can change the circuit easily as
easily often as they want
These devices are not flexible during These devices are more flexible
design cycle. during design cycle
Preffered choice in applications Preferred choice in applications
requiring highest performance level. requiring quick design cycle

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PLA Architecture
PLA consists of two levels of logic gates: a programmable, wired AND-plane followed by a
programmable, wired OR-plane. A PLA's structure allows any of its inputs (or their
complements) to be ANDed together in the AND plane, each AND plane output can thus
correspond to any product term of the inputs. Similarly, users can configure each OR plane
output to produce the logical sum of any AND plane output. With this structure, PLAs are well-
suited for implementing logic functions in sum-of-products form.

In a PLA, the number of AND functions is independent of the number of inputs, and the number
of OR functions is independent of both the number of inputs and the number of AND functions.

Fig5.12: PLA architecture

Example: Implementation of full adder

Expression : Sum(s) : ̅ ̅ C + ̅ B ̅ +A ̅ ̅ + A B C

Carryout (C0) : ̅ B C + A ̅ C + A B ̅ + A B C
TRUTH TABLE

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LOGIC DIAGRAM

PAL-architecture
It consists of Programmable AND-Plane followed by a fixed OR-Plane .The number of products
in an SOP form will be limited to a fixed number (usually 4-10 product 4 terms). The number of
variables in each product term limited by number of input pins (>=10 inputs) .The number of
independent functions limited by number of output pins.

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Fig5.13: PAL architecture.

Example: Implementation of full adder

Expression :

Sum(s) : ̅ ̅ C + ̅ B ̅ +A ̅ ̅ + A B C

Carryout (C0) : ̅ B C + A ̅ C + A B ̅ + A B C

TRUTH TABLE

LOGIC DIAGRAM

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Unit-VI Digital Integrated Circuit

Logic families: In Digital system Designs, main aim is to create an Integrated Circuit (IC). A
Circuit configuration or arrangement of the circuit elements in a special manner will result in a
particular Logic Family.

Classifications of logic families:

The basic classifications of logic families are,
 Bipolar Families
 MOS Families
 Hybrid Families
Bipolar Families:
 Diode Logic (DL)
 Resistor Transistor Logic (RTL)
 Diode Transistor Logic (DTL)
 Transistor- Transistor Logic (TTL)
 Emitter Coupled Logic (ECL) or Current Mode Logic (CML)
 Integrated Injection Logic (IIL)

MOS Families:
 P-MOS Family
 N-MOS Family
 Complementary-MOS Family
 Standard C-MOS
 Clocked C-MOS
 Bi-CMOS
 Pseudo N-MOS
 C-MOS Domino Logic
 Pass Transistor Logic
Hybrid Families
 Bi-CMOS Family

Voltage and current parameters:

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VIL(max)- Low level input voltage: defines the maximum voltage level that will be interpreted as
a ‘0’ by a digital input.
VIH(min) High level input voltage : defines the minimum voltage level that will be interpreted as
a ‘1’ by a digital input.
VOL(max)- Low level output voltage: defines the guaranteed maximum voltage level that will
appear on a digital output set to ‘0’.
VOH(min) – High level output voltage: defines the guaranteed minimum voltage level that will
appear on a digital output set to ‘1’.
IIH(min) - High-level input current: It is the current that flows into an input when a specified
high-level voltage is applied to that input.
IIL(max) - Low-level input current: It is the current that flows into an input when a specified low-
level voltage is applied to that input.
IOH(min) - High-level output current: It is the current that flows from an output in the logical ‘1’
state under specified load conditions.
IOL(max) - Low-level output current: It is the current that flows from an output in the logical ‘0’
state under specified load conditions.

Definitions:
Fan-in: It determines the number of inputs the logic gate can handle.

Fan-out: The fan-out is defined as the maximum number of inputs (load) that can be connected
to the output of a gate without degrading the normal operation. It is also called as loading factors.

Propagation delay: Propagation delay is the time required for the input to be propagated to the
output. (OR) The propagation delay of a logic gate is defined as the time it takes for the effect of
change in input to be visible at the output.

Power dissipation: Each gate is connected to a power supply VCC (VDD in the case of CMOS).
Draws a certain amount of current during its operation. Since each gate can be in a High state
transition or Low state, there are three distinguish currents drawn from power supply.
ICCH : Current drawn during HIGH state.
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ICCT: Current drawn during HIGH to LOW, LOW to HIGH Transition.
ICCL : Current drawn during LOW state.

For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If we
assume that ICCH and ICCL are equal then,
Average Power Dissipation = Vcc * (ICCH + ICCL)/2

For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power
dissipation is calculated as below.
Average Power Dissipation = Vcc * ICCT.
The total power consumed by an IC is equal to the product of the power dissipated by each gate
in the IC.

Nose margin: Gate circuits are constructed to sustain variations in input and output voltage
levels. Variations are usually results of several different factors. Batteries lose their full potential,
causing the supply voltage to drop.

High operating temperatures may cause a drift in transistor voltage and current characteristics.
Spurious pulses may be introduced on signal lines by normal surges of current in neighboring
supply lines.

All gates designed to tolerate a certain amount of noise on their input and output ports. The
maximum noise voltage level that is tolerated by a gate is called a noise margin.

TTL NAND Gate:

Circuit of standard TTL NAND gate:

Fig 6.1: TTL NAND gate.

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Operation: If A or B is low, the base-emitter junction of Q1 is forward biased and its base-
collector junction is reverse biased. Then there is a current from Vcc through R1 the base emitter
junction of Q1 and into the LOW input, which provides a path to the ground for the current.
Hence there is no current into the base of Q2 and making it into cut-off. The collector of Q2 is
HIGH and turns Q3 into saturation. Since Q3 acts as an emitter follower, but providing a low
impedance path from Vcc to the output, making the output into HIGH. At the same time, the
emitter of Q2 is at ground potential, keeping Q4 OFF.

When A and B are high, the two input base emitter junctions of Q1 are reverse biased and its
base collector junction is forward biased. This permits current through R1 and the base collector
junction of Q1 into the base of Q2, thus driving Q2 into saturation. As a result Q4 is turned ON
by Q2, and producing LOW output which is near ground potential. At the same time, the
collector of Q2 is sufficiently at LOW voltage level to keep Q3 OFF.
Truth table:
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

CMOS Inverter:
Circuit diagram of CMOS inverter

Fig 6.2: CMOS inverter

Operation:
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to
the drain terminals. It is important to notice that the CMOS does not contain any resistors, which

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makes it more power efficient that a regular resistor-MOSFET inverter. As the voltage at the
input of the CMOS device varies between 0 and 5 volts, the state of the NMOS and PMOS varies
accordingly.

When VIN is low, the NMOS is ‘off’, while the PMOS is ‘on’, so VOUT is set to logic high.
When Vin is high, the NMOS is ‘on’ and the PMOS is ‘off’, draining the voltage at VOUT to
logic low.

Voltage levels in TTL: TTL gates operate on a nominal power supply voltage of 5 volts.
Ideally, a TTL ‘high’ signal would be 5.00 volts exactly, and a TTL ‘low’ signal 0.00 volts
exactly. However, real TTL gate circuits cannot output such perfect voltage levels, and are
designed to accept ‘high’ and ‘low’ signals deviating substantially from these ideal values.
Acceptable input signal voltages range from 0 volts to 0.8 volts for a ‘low’ logic state, and 2
volts to 5 volts for a ‘high’ logic state. Acceptable output signal voltages range from 0 volts to
0.5 volts for a ‘low’ logic state, and 2.7 volts to 5 volts for a ‘high’ logic state

Fig 6.3: Acceptable TTL I/O voltage levels.

Voltage levels in CMOS: CMOS gate circuits have input and output signal specifications
that are quite different from TTL. For a CMOS gate operating at a power supply voltage of 5
volts, the acceptable input signal voltages range from 0 volts to 1.5 volts for a ‘low’ logic state,
and 3.5 volts to 5 volts for a ‘high’ logic state. Acceptable output signal voltages range from 0
volts to 0.05 volts for a ‘low’ logic state, and 4.95 volts to 5 volts for a ‘high’ logic state

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Fig 6.4: Acceptable CMOS I/O voltage levels.

Unlike TTL, which is restricted to a power supply voltage of 5 volts, CMOS may be powered by
voltages as high as 15 volts (some CMOS circuits as high as 18 volts).

Comparison characteristics of TTL, ECL, CMOS and I2L logic families:

Specification TTL ECL CMOS I2L

Basic gate NAND OR/NOR NAND/NOR NAND
Fan out 10 25 >50 8-12
Power per
1-22 4-55 1 @ 1MHz 5-25
gate(mWatt)
High(because
Noise it operates by
Very Good Good Excellent
Immunity current
instead
Speed 100 100 0.7 4(small)
Propagation 2(ECL
10 70 25-250
delay in (ns) 10K)
High speed LSI functions
Laboratory Portable
Applications switching and large
instruments instruments
applications computers
Clock rate
15-60 60-400 5 ---
(M Hz)

Interfacing of TTL and CMOS devices: To achieve optimum performance in a digital

system, devices from more than one logic family can be used, taking advantages of the
characteristics of each family for different parts of the system. For example, CMOS logic ICs
can be used in those parts of the system where low power dissipation is required, whereas TTL
can be used for those portions of the system which require high speed of operation. Also, some

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function may be easily available in TTL and others may be available in CMOS. Therefore, it is
necessary to examine the interface between CMOS and TTL devices.
CMOS and TTL are the two most widely used logic families. Although ICs belonging to the
same logic family have no special interface requirements, that is, the output of one can directly
feed the input of the other, the same is not true if we have to interconnect digital ICs belonging to
different logic families. Incompatibility of ICs belonging to different families mainly arises from
different voltage levels and current requirements associated with LOW and HIGH logic states at
the inputs and outputs.

CMOS driving TTL: The first possible type of CMOS-to-TTL interface is the one where both
ICs are operated from a common supply. The TTL family has a recommended supply voltage of
5 V, whereas the CMOS family devices can operate over a wide supply voltage range of 3–18 V.
In the below figure both ICs operate from 5 V. As far as the voltage levels in the two logic states
are concerned, the two have become compatible. The CMOS output has a VOH(min.) of 4.95V
(for VCC =5 V) and a VOL(max.) of 0.05 V, which is compatible with VIH(min.) and VIL(max.)
requirements of approximately 2 and 0.8V respectively for TTL family devices. In fact, in a
CMOS-to- TTL interface, with the two devices operating on the same VCC, voltage level
compatibility is always there. It is the current level compatibility that needs attention.

The below figure shows a CMOS-to-TTL interface with both devices operating from 5V supply
and the CMOS IC driving a low-power TTL or a low-power Schottky TTL device.

Fig 6.5: CMOS driving TTL.

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TTL Driving CMOS: In the TTL-to-CMOS interface, current compatibility is always there. The
voltage level compatibility in the two states is a problem. VOH (min) of TTL devices is too low as
regards the VIH (min) requirement of CMOS devices. When the two devices are operating on the
same power supply voltage, that is, 5 V, a pull-up resistor of 10 k achieves compatibility as
shown in below figure.

Fig 6.6: TTL driving CMOS using pull up resistor.

The pull-up resistor causes the TTL output to rise to about 5V when HIGH. When the two are
operating on different power supplies, one of the interface techniques is to use a transistor in
between the two, as shown below.

Fig 6.7: TTL driving CMOS using transistor

Features of HMOS and CHMOS:
Features of HMOS Features of CHMOS

Smaller chip area per transistor Low power consumption

Higher density. Higher noise immunity

Higher speed. Higher speed

Architecturally compatible with their

Less propagation delay.
HMOS counter parts

It can provide power down and idle modes

of operation

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Concept of ESD: Electrostatic discharge (ESD) is the release of static electricity when two
objects come into contact. Familiar examples of ESD include the shock we receive when we
walk across a carpet and touch a metal door knob and the static electricity we feel after drying
clothes in a clothes dryer. While most ESD events are harmless, it can be an expensive problem
in many industrial environments.

ESD first requires a build-up of an electrostatic charge. This occurs when two different materials
rub together. One of the materials becomes positively charged, the other becomes negatively
charged. The positively charged material now has an electrostatic charge. When that charge
comes into contact with the right material, it is transferred and we have an ESD event. The heat
from the ESD event is extremely hot, although we do not feel it when we are shocked. However,
when the charge is released onto an electronic device such as an expansion card, the intense heat
from the charge can melt or vaporize the tiny parts in the card causing the device to fail.
Sometimes an ESD event can damage a device, but it continues to function. Which is hard to
detect and significantly shortens the life of the device.

Remedy for ESD:

 Keep all synthetic materials at least 4 inches away from electronic equipment.
 When cleaning printed circuit boards, use a spray labeled as non-static forming.
 When troubleshooting electronic equipment, always wear a static wrist strap that is
grounded to the frame of the device. Also wear the wrist strap when handling printed
circuit boards.
 Treat carpets and floors with compounds that reduce the buildup of static charges.
 Use static floor mats where necessary.
 Make sure the grounding system for equipment has low impedance for ESD currents to
dissipate to an earthing reference.

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