Sample Midterm 2017
Sample Midterm 2017
Sample Midterm
1) Perform the following addition operations on two signed decimal numbers by representing
them as 8-bit signed numbers in 2’s-complement format and performing binary addition. Show
the range of the decimal numbers that can be represented as 8-bit signed numbers in 2’s-
complement format. Show all the intermediate steps and indicate whether there is an overflow
or not.
+117 +117
+ +98 + + -98 +
-117 -117
+ +98 + + -98 +
CS303 – Logic & Digital System Design
2) Optimize the following Boolean function F together with the don’t care conditions d. Find all
prime implicants, essential prime implicants, and simplified boolean expression for F in sum-of-
products form and product-of-sums form.
3) Design a combinational circuit that divides a 2-bit unsigned binary number A = (a1 a0) by
another 2-bit unsigned binary number B = (b1 b0) and generates a 2-bit unsigned binary number
D = (d1 d0) that gives the remainder of the division (i.e. D = A%B). Note that division-by-0 is
not defined. Therefore, you can assume that the input combinations causing division-by-0 are
not applied.
a1 a0 b1 b0 d1 d0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
b. Derive simplified boolean expressions for the outputs in sum-of-products form using
K-maps.
CS303 – Logic & Digital System Design
c. Implement d0 output using NOR gates only and draw the circuit.
d. Implement d1 output using the smallest multiplexer. Do not use any other gate. Just
show the selection inputs (Si) and data inputs (Ii) of the multiplexer.
CS303 – Logic & Digital System Design
4) Design a magnitude comparator that takes two 3-bit signed numbers in 2’s complement
format, A = (a2 a1 a0) and B = (b2 b1 b0), and outputs g = 1 if A > B, otherwise g = 0. Show the
boolean expression for the output g.
CS303 – Logic & Digital System Design
5) Show how to implement a 5x32 decoder using smaller 3x8 and 2x4 decoders shown
below. Label the minterms the resulting 5x32 decoder generates given that the inputs
are (x, y, z, t, w) in this order.
0 0
1 1
2x4
I0 2 I0 2
I1 3 I1 3
3x8 e
4
I2
5
6
e 7
CS303 – Logic & Digital System Design
6) Consider the following circuit with three inputs (A, B, C) and one output (F).
0
I0
B 21
2x4
1 2x1
decoder 2 MUX
C I1 F
20 S
3
b. Derive the truth table of the function that the circuit implements.
A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1